JPH0658655B2 - Serial I / O method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an interface system between device constituent units of a terminal device including a car telephone terminal device that is required to be small in size.

[Problems to be Solved by Prior Art and Invention]

Conventionally, a serial interface has been used as this kind of interface.
There are cases where a standard interface such as 2C is used, and cases where the algorithm is executed by software through the general-purpose I / O port of the microprocessor. The former does not increase the software for controlling with a microprocessor, but is a general-purpose LS prepared for a standard interface.
Since 1 is required, the increase in the amount of hardware cannot be avoided. The latter does not increase the amount of hardware because the serial interface is performed using unused I / O ports prepared for the functional operation of the device configuration unit, but the load on the software is large and the serial speed is high. The interface was difficult to implement and often caused problems in terms of operating speed.

Recently, in order to meet the demands for downsizing and portability of devices, it is an urgent task to make both hardware and software extremely smaller than the current situation, and a serial interface suitable for them has been desired.

An object of the present invention is to provide a serial interface system (that is, a serial I / O system) that sufficiently satisfies the requirements as an interface for such small-sized and portable devices.

[Means for solving problems]

The present invention realizes a serial interface in which both hardware and software are the smallest and can operate at high speed, and therefore clocks, data inputs, and data for multiple CPUs, which have recently been incorporated in microprocessors. The first means is to use an output serial I / O line, and a control line is added to the serial I / O line as an interface to add a serial I / O line.
By installing a program with a line control function in one of the microprocessors, the serial interface can be made into a bus, and multiple microprocessors can be connected on the same interface line. There is no need to prepare one-to-one like an interface, and one-to-many or many-to-many connections can be made possible and expandability can be provided.

Further, the microprocessor having the control function outputs the clock of the serial I / O line, and the other microprocessors input and output data in synchronization with this clock, so that the algorithm is simple and the reliability is high enough for high-speed operation. It is a guaranteed serial interface method (that is, a serial I / O method).

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a serial interface according to an embodiment of the present invention, in which 1 is a microprocessor having a control function, and 2 and 3 are microprocessors using the serial interface of the present invention, which are designed respectively. It performs the same functional processing and inputs / outputs the necessary data through the serial interface. 4-7
Is a serial I / O connecting the microprocessors 1 to 3
It is a line. Reference numeral 4 denotes a serial input data line when viewed from the microprocessor 1, and a serial output data line when viewed from the processors 2 and 3. 5 is a microprocessor 1
It is a serial output data line when viewed from above, and is a serial input data line when viewed from the microprocessors 2 and 3. Reference numeral 6 is a synchronous clock line for data transmitted / received by the serial data lines 4 and 5, and the synchronous clock is output by the microprocessor 1 and the microprocessors 2 and 3 treat it as an input signal. It is assumed that the data transmitted and received on the serial data lines 4 and 5 are processed in synchronization with this clock. Reference numeral 7 is a control line for activating the signal line by its output signal when the microprocessors 2 and 3 want to output serial data and notifying the microprocessor 1 having a control function of a control request for serial data output. .

As can be seen from FIG. 1, the microprocessor is added by connecting a microprocessor having the same software for the serial interface built in the microprocessor 2 or 3 to the serial I / O lines 4 to 7. By doing so, it can be done easily.

Next, the operation of the serial I / O lines 4 to 7 in FIG. 1 will be described with reference to the timing chart in FIG. In the following description, the signal on the serial input data line 4 is SI, the signal on the serial output data line 5 is SO, the signal on the synchronous clock line 6 is SCK, and the signal on the control line 7 is REQ.
Further, in the embodiment shown in FIG. 1, a maximum of 16 microprocessors can be connected, and the maximum number of serial data transfer bytes between the microprocessors is 16 bytes.

In FIG. 2, the serial output data SO shows the case where 8 bits are used as one frame, and the synchronous clock SCK is the serial output data SO at the rising point thereof.
8 are transmitted at a timing such that sampling is required. FIG. 2 shows a case where data is transferred from the microprocessor 1 having a control function to the microprocessor 2 or 3, in which case the control line REQ remains inactive and the serial input data SI contains data. No signal is generated. Data transfers are sent to both microprocessors 2 and 3 by serial output data SO. Although the microprocessors 2 and 3 always receive the serial output data SO, the microprocessor 2 and 3 determine whether or not the data signal is necessary for themselves by the control algorithm shown below and determine whether or not to take it in. That is, as the transfer procedure, the 8-bit data sent from the microprocessor 1 in the first frame has the ID number 8 and the transfer byte number 9 of the transfer destination, and in this embodiment, 8 and 9 are respectively. There are 4 bits each. From the subsequent frame, the data of the number of data shown in the first frame is transmitted as the serial output data SO by the synchronous clock SCK. This transmission data is shown at 10 in FIG. When sending data to multiple processors, repeat the above operation as many times as necessary. Further, when the same data signal is sent to all the connected microprocessors, it can be performed by allocating the number of the content to the ID number 9 sent in the first frame in advance.

Next, an algorithm for sending data from the microprocessor 3 to the microprocessor 1 having a control function will be described with reference to the timing chart of FIG. In FIG. 3, when the microprocessor 3 activates the control line REQ as a data transmission request, the microprocessor 1 having a control function recognizes this and polls which microprocessor the data transmission request is from. First, the sending request confirmation signal 11 is sent to the serial data output SO to the microprocessor 2. The signal 11 is first sent to the microprocessor 2 because the ID number is smaller than that of the microprocessor 3. After sending the sending confirmation signal 11, the microprocessor of the ID number sends the serial input data S by sending the synchronous clock SCK of 8 bits.
It is checked whether or not a transmission request is issued to I. In FIG. 3, since the microprocessor 2 has no transmission request and does not output data to the serial input data SI in synchronization with the synchronization clock SCK, the microprocessor 1 having a control function issues a transmission request from the microprocessor 2. Can recognize that there is no. Subsequently, the microprocessor 1 sends a transmission request confirmation signal 1 to the microprocessor 3.
2 is similarly transmitted, and then 8 bits of the synchronization clock SCK are transmitted. In this case, since the microprocessor 3 has a transmission request, the transmission request signal 13 is added to the serial input data SI.
Is output. Since the sending request signal 13 includes the ID number of the microprocessor 3 and the number of sending bytes as contents, the microprocessor 1 sends the synchronization clock SCK and receives the sending data from the microprocessor 3 for that number of bytes. To do. When the data transmission is completed, the microprocessor 3 inactivates the control line REQ,
It notifies the other microprocessor that the transmission is completed, and ends the transmission algorithm. The microprocessor 1 having a control function is connected as described above.
Since data sent from a plurality of microprocessors can be received, a one-to-many connection is possible.

Next, as another embodiment, a case of transmitting data from the microprocessor 2 to the microprocessor 3 will be described with reference to FIG. First, the microprocessor 2 activates the control line REQ in the same manner as described with reference to FIG. 3, and notifies the microprocessor 1 of the transmission request.
The microprocessor 1 starts polling and sends a send request confirmation signal 14 to the microprocessor 2. In response to this, the microprocessor 2 sends the send request signal 15 to the serial input data SI, so that the microprocessor 1 can recognize that there is a send request from the microprocessor 2. Further, in the transmission request signal 15,
Since the ID number of the microprocessor 2 and the ID number of the microprocessor 3 are included, it can be simultaneously recognized that the data transfer from the microprocessor 2 to the microprocessor 3 is necessary. Subsequently, the microprocessor 1 and the microprocessor 2 are interlocked with each other, and serial input data SI and serial output data S of the serial I / O lines are connected.
O switching operation is performed. That is, the serial output data SO line which has been output by the microprocessor 1 having the control function and has been used as an input by the microprocessors 2 and 3 until now can be used as an output by the microprocessor 2 and can be input by the microprocessors 1 and 3. Serial input data S used as an input by the microprocessor 1 and as an output by the microprocessors 2 and 3 at the same time when the switching is performed.
The switching is performed so that the I-line can be used by the microprocessor 2 as an input and the microprocessors 1 and 3 can use it as an output. Then microprocessor 1
When the 8-bit synchronous clock SCK is transmitted, the microprocessor 2 sends the serial output data SO with the ID of the transmission destination.
By sending out a signal 16 containing the number and the number of sending bytes, it is possible to cause the microprocessor 3 to receive data. The microprocessor 1 switches the serial I / O line to the destination I of the signal 16 described above.
Since the D number and the number of transmitted bytes can be recognized, the synchronous clock SCK for that number of bytes is transmitted, and the microprocessor 2
After making the microprocessor 3 transfer the data, the microprocessor 2 finishes the transmission and the serial I
Switch SI / SO of / O line to the original state, and control line RE
After confirming that Q has been returned to inactive, serial I
The sequence is completed by switching based on SI and SO of the / O line. Although the algorithm shown in FIG. 4 is slightly different from the algorithm described in FIG. 3, in this case, the data transfer of microprocessors having the same hardware configuration but no control function is possible. It also enables many-to-many connections.

〔The invention's effect〕

As described above, according to the present invention, the serial I / O for the multi-CPU system built in the microprocessor is used.
By adding one control line in addition to the line, the serial interface can be made into a bus, and the serial interface with the least hardware and software and with expandability can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram partially showing an embodiment of the present invention, FIG. 2 is a timing chart showing an example of use of the serial I / O line shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a timing chart showing another usage example of the serial I / O line shown in FIG. 4, and FIG. 4 is a timing chart showing still another usage example of the serial I / O line shown in FIG. 1 ... Microprocessor having control function, 2 ... Microprocessor connected to serial I / O line (1),
3 ... Microprocessor (2) connected to serial I / O line, 4 ... Serial input data line, 5 ... Serial output data line, 6 ... Synchronous clock line, 7 ... Control line,
8 ... 4 bits indicating the ID number in the serial output data, 9 ... 4 bits indicating the number of sending bytes in the serial output data, 10 ... Data transferred using the serial output data, 11 ... Sending request Confirmation signal (1), 12 ...
Transmission request confirmation signal (2), 13 ... Transmission request signal, 14 ...
… Sending request confirmation signal, 15 …… Sending request signal, 16 ……
Serial output data including the ID number of the transmission destination and the number of transmission bytes.

Claims (4)

[Claims] 1. A multi-CPU system in which a serial I / O line including a clock line, a data input line, and a data output line is used as a serial interface for a multi-CPU system having a plurality of microprocessors. By installing a program for controlling the serial I / O line in one of them, a microprocessor having a control function is formed, and in addition to the serial I / O line, control is performed. By adding a control line, the control line and the microprocessor having the control function can share the serial I / O line by forming a bus, and a plurality of microprocessors other than the microprocessor having the control function can be used. The microprocessor always receives data and sends data In this case, by activating the control line, the microprocessor having the control function is notified of the transmission request, and the microprocessor having the control function is caused to control the serial interface before transmitting the data. Is a serial I / O system in which the serial interface is used as a bus by using the above-mentioned method, and a microprocessor having the control function supplies a clock to the control line to the clock line of the serial I / O lines. Output to another microprocessor in response to the active state, and the microprocessor having the control function checks the transmission request for the data input line and the data output line of the serial I / O lines in synchronization with the clock. The signal is output to the other microprocessor and the other microprocessor is Processor is a serial I / O system, wherein the sending request signal in synchronization with the clock output to microprocessor with the control function performs further data input, the data output in synchronism with the clock. 2. When data is transmitted from a processor other than the microprocessor having the control function to the microprocessor having the control function, the control line is activated to indicate that there is a transmission request. Notifying the processor and causing the microprocessor having the control function to send polling data sequentially including one by one the ID numbers assigned to the microprocessors other than the microprocessor having the control function in synchronization with the clock, When the processor which has activated the control line receives polling data for itself, in response to the polling data, a response signal including its own ID number and the number of data to be transmitted is transmitted in synchronization with the clock output from the microprocessor having the control function. By controlling the ID microprocessors activate the control line to the microprocessor Capable
The number of data and the number of transmitted data are confirmed, and the microprocessor having the control function transmits a clock corresponding to the number of transmitted data to receive the transmitted data from the microprocessor that has issued the transmission request. The serial I / O method described in item 1. 3. When data is transferred between microprocessors other than the microprocessor having the control function, the microprocessor having the transmission request activates the control line and sends the transmission request to the microprocessor having the control function. The fact that there is something is notified in synchronization with the clock output by the microprocessor having the control function, and the ID number assigned by the microprocessor having the control function to a microprocessor other than the microprocessor having the control function is 1 The polling data sequentially including one by one is transmitted in synchronization with the clock, and when the microprocessor which activated the control line receives the polling data for itself, as a response, its own ID number and the microprocessor of the data transfer destination are sent. ID number By sending out a response signal including the signal in synchronization with the clock, the microprocessor having the control function is made to recognize the ID number of the microprocessor which activated the control line and the ID number of the microprocessor of the data transfer destination. , The control of the serial I / O line is transferred from the microprocessor having the control function to the microprocessor that activates the control line, and the microprocessor that activates the control line sends the ID number and the data transfer destination. A send request signal including the number of data is sent in synchronization with the clock to notify the transfer destination microprocessor, and also the microprocessor having the control function receives the send request signal to supply the clock required for data transfer. Request for data transfer Range Serial I / O method described in paragraph 1. 4. When data is transferred between microprocessors other than the microprocessor having the control function, the microprocessor having the transmission request activates the control line to send the transmission request to the microprocessor having the control function. The microprocessor having the control function notifies the serial I / O
A microprocessor that activates the control line by sending polling data including ID numbers assigned to a plurality of microprocessors connected to the O line in synchronization with a clock output from the microprocessor having the control function is When the polling data for itself is received, a response signal including its own ID number and the ID number of the microprocessor of the data transfer destination is sent as a response in synchronization with the clock, thereby sending to the microprocessor having the control function. The ID number of the microprocessor that activated the control line and the ID number of the microprocessor of the data transfer destination are recognized, and
The control of the serial I / O line is transferred from the microprocessor having the control function to the microprocessor that activates the control line, and the microprocessor that activates the control line determines the ID number of the data transfer destination and the number of transmitted data. A sending request signal including the signal is sent in synchronization with the clock to notify the transfer destination microprocessor,
The serial I / O system according to claim 1 or 2, wherein a microprocessor having the control function is made to receive the transmission request signal, and a clock necessary for data transfer is supplied to transfer the data. .