JPH0652677A - Fifo memory - Google Patents

Abstract

PURPOSE:To reduce a read spacing from an external and to speed up the entire FIFO memory. CONSTITUTION:The memory consists of plural FIFO memory circuits which have a same number of stages and a same number of bits, an input switching circuit 3 which successively distributes the inputted data to these FIFO memory circuits, an output switching circuit 4 which successively switches the data from the plural FIFO memories and outputs them and switching timing generating circuits 50 and 51. While data are read from a specific FIFO memory circuit, a data transfer is performed by another FIFO memory circuit and the data are always ready in the last stage of any one of the FIFO memory circuits. Thus, the reading spacing from an external is reduced and the entire FIFO memory is speeded up.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a FIFO memory.

[0002]

2. Description of the Related Art In a data input / output operation, a buffer memory that outputs data in the order in which it is fetched is a FIFO memory.
It is called an O (First In First Out) memory. This FIFO memory is mainly used in a digital electronic circuit and has a function of adjusting a shift in operation timing in data transfer between devices that operate asynchronously.

As an example of a conventional FIFO memory, a schematic block diagram of a shift register type FIFO memory,
Is shown in FIG. In FIG. 7, the shift register type FIFO memory is composed of one FIFO memory circuit, and FIG. 8 shows a detailed block diagram in the case of 8 bits × n stages.

The FIFO memory shown in FIG. 7 has an ISR (indication shift register) section 1 and a DSR (data shift register) section 2, and has data DI0, D1.
0 to D7 are input, and the data output signal DI (n + 1),
D (n + 1) 0 to D (n + 1) 7 are output, and clear signals CLR (n + 1) to CLR0 are also input. I in FIG.
The SR unit 1 includes an n-stage ISR circuit 13 as shown in FIG.
The DSR unit 2 of FIG. 7 is composed of n stages of DSR circuits 23 as shown in FIG. 8, and is composed of eight registers according to the data input signals DO0 to DO7 of the DSR circuits 23 of each stage.

In FIGS. 7 and 8, a shift register type FIFO memory circuit includes a 1-bit × n-stage indication shift register (hereinafter abbreviated as ISR) unit 1.
And an 8-bit × n-stage data shift register (hereinafter abbreviated as DSR) unit 2. I of each stage
The SR circuit 13 is for managing information on whether or not the data to be latched has arrived at the DSR circuit 23 at the same stage. The DSR circuit 23, under the control of the ISR circuit 13,
This is a register for latching the data that has arrived at the FIFO memory circuit.

FIG. 9 shows the logical configuration of the n-th stage ISR circuit.
FIG. 10 shows the operation timing. The operation of the asynchronous FIFO memory will be described with reference to FIGS. 7 to 10.

In FIG. 9, the logical structure of the indication shift register of this shift register type FIFO memory circuit is as follows.
R flip-flop 102 and 2-input AND gate 1
03 and a 3-input AND gate 104.

In FIG. 10, signal waveforms of respective portions of the shift register type FIFO memory circuit (FIGS. 7 to 1)
0, signals of the same part are indicated by the same alphabet). The arrows in the figure show the causal relationship of signal flow.

In FIGS. 7 to 10, the data FIFO
At the start of the operation of storing in the memory circuit, the DI signal and CLR signal of each stage are cleared to "0". In this state,
When data arrives at the nth stage, that is, when the DIn signal becomes "1", the CLR (n +) signal and DI (n + 1) signal
Since all of the signals are "0", the STBn signal becomes active and the 8-bit data Dn0 to Dn7 arriving at the nth stage DSR circuit 23 is latched in the DSR circuit 23. Next, the operation proceeds to the preparation of data transfer to the (n + 1) th stage and the operation of notifying the completion of latching in the nth stage to the (n-1) th stage. That is, DI rises when the STBn signal rises.
The (n + 1) signal is activated to notify that the data to be latched has arrived at the (n + 1) th stage. Also,
When the STBn signal drops and the CLRn signal becomes active and the DIn signal becomes “0”, it is possible to complete data storage in the nth stage and store new data in the n−1th stage. To the n-1th stage ISR circuit 13. By repeating the above operation, the data arriving at the first stage is transferred to the latter stage by shogi. Thus, in order for data to propagate through the FIFO memory circuit one stage, the following operations (1), (2), and (3) are required.

(1) Acquisition of data from the previous stage.

(2) Output of data to the next stage.

(3) Clear the ISR circuit in the previous stage.

Next, data propagation in the 8-bit × n-stage FIFO memory circuit will be specifically described. First, when 1-byte data arrives at the 0th stage, the above operation is performed for n stages, and the data is latched in the DSR circuit 23 at the nth stage and DI
Activate the (n + 1) signal. At this time, CLR
If the (n + 1) signal is not active, this data is held in the n-th stage DSR circuit 23. CLR (n +
1) If the signal is active,
That is, it means that data is taken from this FIFO memory circuit. Therefore, the CLR (n + 1) signal can be rephrased as a read signal (RD signal) for the FIFO memory circuit.

When the interval between external read operations to the FIFO memory is shorter than the data propagation for one stage in the FIFO memory circuit, the read interval from the final stage is the data propagation time for one stage of the FIFO memory circuit. Limited to.

[0015]

As described above, the conventional F
In the IFO memory, it is impossible to make the reading interval from the outside smaller than the data propagation time for one stage.
Further, it is difficult to shorten the data propagation time for one stage due to the circuit configuration, and this data propagation time has been a limitation for speeding up the FIFO memory.

It is an object of the present invention to provide a FIFO memory which solves the above-mentioned drawbacks, shortens the reading interval from the outside, and speeds up the entire FIFO memory.

[0017]

The structure of the FIFO memory of the present invention comprises a plurality of FIFO memory circuits having the same number of stages and the same number of bits, and input data to the plurality of FIFO memory circuits. An input switching circuit for sequentially distributing, an input switching timing generation circuit for generating a switching timing signal upon completion of data input to the FIFO memory circuit, and an output switching circuit for sequentially switching and outputting data from the plurality of FIFO memory circuits, And an output switching timing generation circuit for generating an output switching timing signal when data output from the FIFO memory circuit is completed.

[0018]

1 is a block diagram showing a FIFO memory according to a first embodiment of the present invention. In FIG. 1, in the present embodiment, an 8-bit × n-stage FIF is adopted by the shift register method.
The case of an O memory circuit is assumed. The circuit of this embodiment includes two FIFO memory circuits each including an ISR section and a DSR section, an input switching circuit 3, and an output switching circuit 4.
And switching timing generation circuits 50 and 51 that generate switching timing signals.

The A side ISR section 10 and the B side ISR section 11 in FIG. 1 have the same structure, and the conventional F shown in FIGS.
It has the same circuit configuration as the ISR unit 1 of the IFO memory circuit,
Do the same. Also, the A side DSR unit 20 and the B side D
The SR unit 21 also has the same circuit configuration, and the conventional F of FIG.
The circuit configuration is the same as that of the DSR unit 2 of the IFO memory circuit, and it is composed of a latch circuit of 8 bits × n stages and operates in the same manner.

An internal block diagram of the input switching circuit 3 is shown in FIG.
As shown in FIG. In FIG. 2, the input switching circuit 3 uses the demultiplexer (DMRX) 33 to convert the 8-bit data D0 to D7 input to the FIFO memory to the A side or the B side.
It is distributed to the DSR unit on the side, that is, the DSR unit 20 or the DSR unit 21. Further, it has a function of switching between the DI0 signal and the CLR0 signal which are control signals of the ISR unit 10 and the ISR unit 11. The input DI0 signal is changed to DI0A signal or DI
Switching to the 0B signal is a demultiplexer (DMP
X) 31 selects either the CLR0A signal or the FLR0B signal and outputs it to the outside as the CLR0 signal by the selector (SEL) 32.

At this time, the switching timing is controlled by the switching timing generation circuit 50, and its logical configuration is shown in FIG. In FIG. 4, in this example, the D-type flip-flop 52 is used to output the CLR0A signal or the CLR0A signal.
At the rising edge of the 0B signal, a short pulse signal is generated, and this short pulse is alternately input to the set (S) input or the reset (R) input to the RS flip-flop 54, whereby the RS flip -The output (Q) of the flop 54 changes to a toggle. The CLR0A signal is output to the flip-flop 52 via the inverter 53, and the CLR0B signal is output to the flip-flop 52 via the inverter 53.

An internal block diagram of the output switching circuit 4 is
As shown in FIG. In FIG. 3, the output switching circuit 4 uses the selector (SEL) 43 to connect the ASR side DSR section 20 and the B side DSR section 20 to the B side.
8-bit data D (n + 1) from the DSR unit 21 on the side
One of 0 to D (n + 1) 7 is selected. Furthermore, IS
DI (n +) which is a control signal for the R section 10 and the ISR section 11
1) It has a function of switching between the signal and the CLR (n + 1) signal. The selector (SEL) 41 selects one of the DI (n + 1) A signal and the DI (n + 1) B signal and outputs it as a DI (n + 1) signal to the outside.
The R (n + 1) signal is changed to CLR (n + 1) A or CLR (n +
1) Switching to B is the demultiplexer (DMP
X) 42. At this time, the switching timing is controlled by the switching timing generation circuit 51 in FIG.
The output changes to toggle at each falling edge of the LR (n + 1) A signal and the CLR (n + 1) B signal. The logical configuration and operation of the output side switching timing generation circuit 51 are the same as those of the input side switching timing generation circuit 50.

Next, the operation of the embodiment of FIG. 1 will be described in detail with reference to the timing chart of FIG.

In FIGS. 1 and 5, the ISR section 10 and the DSR section 20 which are the FIFO memory circuits on the A side have the circuit configuration of the conventional FIFO memory circuit shown in FIG. 8 and have the same functions. That is, n of the A-side FIFO memory circuit
When the data arrives at the stage, the DInA signal becomes "1", and both the CLR (n + 1) signal and the DI (n + 1) A signal are "0", so the STBnA signal becomes active and the DSR circuit at the nth stage is reached. The arriving 8-bit data Dn0 to Dn7 is latched in the DSR circuit.

Next, the operation proceeds to the preparation of data transfer to the (n + 1) th stage and the operation of informing the n-1th stage of the completion of latching in the nth stage. That is, the DI (n + 1) A signal is activated by the rising edge of the STBnA signal, and n +
Notify that the data to be latched has arrived at the first stage. Further, the CLRnA signal is activated by the fall of the STBnA signal and the DInA signal becomes “0”, whereby the storage of data in the nth stage and the storage of new data in the n−1th stage can be performed. This is notified to the n-1th stage ISR circuit.

Similarly, the ISR section 11 and the DSR section 21, which are B-side FIFO memory circuits, also have the conventional FI shown in FIG.
The circuit configuration is the same as that of the FO memory circuit, and the A-side FIF
Functions like an O memory circuit. By the functions of the input circuit 3 and the switching timing generation circuit 50, 8
Bit data is alternately input to the A-side and B-side FIFO memory circuits, and the data is shifted toward the final stage inside each FIFO memory circuit. The data reaching the final stage activates the DI (n + 1) signal and indicates that the data can be read to the outside.

At this time, as shown in the timing chart of FIG.
Output switching circuit 4 and switching timing generation circuit 51
Of data D (n + 1) 0 output to the outside by
~ D (n + 1) 7 are alternately switched to the A side and the B side. The switching timing is the CLR of the selected side.
When the A side is selected by the n + 1 signal, CLR (n +
1) When A signal and B side are selected, CLR (n +
1) It becomes a B signal. Therefore, as shown in the timing chart of FIG. 5, data is alternately output from the FIFO memory circuit on the A side and the B side. Further, since the B side data is propagated while the A side data is being output, and conversely, the A side data is propagated in the B side data, so that either FIF is always transmitted.
Data is prepared in the final stage of the O memory circuit, and data can be output immediately after switching.

As a result, the data read interval from the FIFO memory becomes smaller than the data propagation time for one stage of the built-in FIFO memory circuit, and the output interval of the FIFO memory circuit as a whole (read interval from the outside).
However, it is greatly reduced. Comparing FIG. 5 showing the operation of this embodiment with FIG. 10 showing the operation of the conventional example, as can be seen from D (n + 1) 0 to D (n + 1) 7 showing the data output intervals, the data output of this embodiment The interval can be expected to be reduced to 1/2 or less.

Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram of the second embodiment. Figure 6
In this embodiment, the FI of 8 bits × n stages is internally provided.
It has three built-in FO memory circuits.

That is, the A side ISR unit 10 and the A side DSR unit 2
0, B side ISR section 11, B side DSR section 21, and C side I
An SR unit 12 and a C-side DSR unit 22 are provided.

By the operation of the output switching circuit 4 and the switching timing generation circuit 51, the data D (n + 1) 0 to D (n + 1) 7 output to the outside are switched to the A side, B side, C side in this order. To be In this embodiment, higher speed can be realized as compared with the first embodiment. It is also possible to further increase the number of built-in FIFO memory circuits.

In the above description, the shift register type FIFO memory path is used as an embodiment, but the present invention is not limited to this, and may be applied to a counter type FIFO memory circuit or the like. The same effect can be obtained. Further, the input / output switching circuit and the switching timing generation circuit can be realized by various circuit configurations other than the circuit configurations shown in the above-mentioned embodiments.

[0033]

As described above, the FIFO of the present invention
In the memory, the reading interval from the outside can be made shorter than the data propagation time for one stage, and the reading interval from the outside can be shortened, and the speed of the entire FIFO memory can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a FIFO memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an input switching circuit of the embodiment shown in FIG.

FIG. 3 is a block diagram of an output switching circuit of the embodiment shown in FIG.

4 is a logic diagram of a switching timing generation circuit of the embodiment shown in FIG.

5 is a timing diagram of the embodiment shown in FIG.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a schematic block diagram of a conventional shift register type FIFO memory.

FIG. 8 is a detailed block diagram of a conventional shift register type FIFO memory circuit.

FIG. 9 shows an ISR (Indication Shift Register) of a shift register type FIFO memory circuit.
is a logical diagram of (ter).

FIG. 10 is a timing diagram of ISR of a shift register type FIFO memory circuit.

[Explanation of symbols]

1 ISR (Indication Shift R
egister) 2 DSR (Data Shift Register)
r) 3,63 Input switching circuit 4,64 Output switching circuit 10 A side ISR section 11 B side ISR section 12 C side ISR section 20 A side DSR section 21 B side DSR section 22 C side DSR section 23 DSR circuit 31, 33 , 42 Demultiplexer 32, 41, 43 Selector 50, 60 Input side switching timing generation circuit 51, 61 Output side switching timing generation circuit 52 D-type flip-flop 53 Inverter 54, 102 RS flip-flop 101 Latch circuit with clear 103 2-input AND gate 104 3-input AND gate

Claims (2)

[Claims] 1. A plurality of FIFO memory circuits having the same number of stages and the same number of bits, an input switching circuit for sequentially distributing input data to the plurality of FIFO memory circuits, and data to the FIFO memory circuits. An input switching timing generation circuit that generates a switching timing signal upon completion of input, an output switching circuit that sequentially switches and outputs data from the plurality of FIFO memory circuits, and an output switching timing signal upon completion of data output from the FIFO memory circuit. And an output switching timing generation circuit for generating 2. The FIFO memory according to claim 1, wherein each of the FIFO memory circuits has 8 bits and comprises 3 circuits.