JPH0652091A - Interruption processing system/method and multiprocessor system - Google Patents

Abstract

PURPOSE:To perform a floating interruption processing system at a high speed in a symmetrical multiprocessor system and at the same time to minimize the increase of signal pins in accordance with conversion of a processor into a VLSI owing to the advancement of the semiconductor technology. CONSTITUTION:A signal line 6 is provided to transmit the floating interruption requests to all processors from an external interruption control part 3. At the same time, a control bus 4 and a data bus 5 are provided to transfer the floating interruption reception information and the floating interruption accessory information between each processor 1 and the part 3. Furthermore a floating interruption reception control means is added to immediately start the floating interruption reception information processing if each processor 1 is ready to receive an interruption and also set in a waiting state where an instruction is not carried out and the interruption is waited for after the processor 1 has recognized the floating interruption request or in an interruption receivable state is set after each delay equivalent to the number of cycles set independently for each processor if no waiting state is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, interrupt processing of an information processing apparatus having a multiprocessor structure, and more particularly to floating interrupt processing.

[0002]

2. Description of the Related Art FIGS. 7 and 8 show a conventional multiprocessor system configuration and a floating interrupt processing system in the system. Figure 7 shows, for example, IEEE standard P89
This is an example of a multiprocessor system configuration realized using Futurebust specified in 6.1.

In the figure, reference numeral 1 is a processor for executing data processing and interrupt processing. Reference numeral 2 is a main storage device that stores instructions and data. This main memory 2 is shared by all processors 1 in the configuration. An external interrupt control unit (hereinafter referred to as ITC) 3 is provided. The ITC 3 issues a floating interrupt request to all the processors 1. Further, the ITC 3 issues detailed information associated with the floating interrupt request in response to the floating interrupt acceptance notification from one certain processor. The ITC 3 also performs processing for canceling the accepted floating interrupt request.

Reference numeral 4 denotes a plurality of control common signal lines (hereinafter referred to as control buses) for transferring control information. The control bus 4 controls the information transfer operation between each processor 1 and the main memory 2. Further, the control bus 4 transfers a signal for controlling a floating interrupt request issuing operation between the processor 1 and the ITC 3. The control bus 4 also transfers a signal for controlling the interrupt acceptance notification operation.

Reference numeral 5 is a plurality of data common signal lines (hereinafter referred to as data buses) for transferring information. The data bus 5 transfers information between each processor 1 and the main storage device 2. Further, the data bus 5 transfers the floating interrupt accompanying information between the processor 1 and the ITC 3.

FIG. 8 shows a multiprocessor system configuration having individual floating interrupt request signal lines between each processor and the external interrupt control unit. In the figure, all 1 to 5 are the same as those shown in FIG.

Next, the operation will be described. A method called a floating interrupt method is generally known as a method for equalizing load distribution among processors and improving system throughput. The floating interrupt method, for example, in a symmetric multiprocessor system, requests one interrupt such as an input / output interrupt to a plurality of processors,
In this method, only the processor that receives the interrupt the earliest performs the interrupt reception process in the system.

In FIG. 7, assume that the ITC 3 first detects a floating interrupt factor. The ITC 3 that has detected the floating interrupt factor performs bus arbitration with the processor 1 and acquires the bus use right of the control bus 4 and the data bus 5. Since the operation of the bus arbitration is not the essence of the floating interrupt processing described here, the description is omitted here. The ITC 3, which has acquired the bus use right as a result of the bus arbitration, broadcasts the floating interrupt request to all the processors 1 in the system configuration using the control bus 4 and the data bus 5. Each processor 1 recognizes from the signal value of the control bus 4 that a floating interrupt has been broadcast from the ITC 3.

Subsequently, inside each processor 1, the acceptance permission conditions such as the interrupt mask are independently judged. If the processor 1 is in the acceptance non-permission state in which it does not accept the broadcasted floating interrupt request, the processor 1 keeps suspending the activation of the floating interrupt acceptance notification process until it transits to the interrupt acceptance enabled state. If the processor 1 is in the acceptance enabled state for accepting the floating interrupt request broadcast, the processor 1 activates the floating interrupt acceptance process.

Here, there must be only one processor in the system that accepts one floating interrupt request and performs interrupt processing. The processor 1 that has started the floating interrupt acceptance processing performs the following operations only for itself to perform the floating interrupt acceptance processing. The processor 1 that has started the floating interrupt acceptance process first broadcasts the declaration of the floating interrupt acceptance process start to all the processors 1 other than itself by using the control bus 4. The broadcast causes the processor 1 to cancel the floating interrupt acceptance processing of the other processors 1. Here, since the floating interrupt request is broadcast from the ITC 3 to all the processors 1 at the same time, there is a case where a plurality of processors 1 simultaneously start the floating interrupt acceptance processing. In this case, there is a possibility that a plurality of processors 1 may simultaneously issue a declaration of the start of floating interrupt acceptance processing by using the control bus 4. However, the resolution of this race condition is achieved by using bus arbitration. That is, the control bus 4 can be used by one processor 1 which first acquires the bus use right by the bus arbitration. Only the processor 1 that has acquired the usage right broadcasts the declaration of the start of floating interrupt acceptance processing. Upon receipt of this, all other processors 1 cancel all the operations that are pending or that the floating interrupt acceptance process is being activated internally.

One processor 1 which has completed the declarative operation for starting the floating interrupt acceptance processing on the control bus 4 subsequently transmits a floating interrupt acceptance notification to the ITC 3 via the control bus 4. The processor 1 completes the floating interrupt process after receiving the accompanying information of the floating interrupt from the ITC 3 via the data bus 5.

On the other hand, the ITC 3 clears the corresponding floating interrupt factor when the response to the notification of floating interrupt acceptance via the control bus 4 and the data bus 5 is completed, and proceeds to the next floating interrupt request operation.

Next, a conventional floating interrupt request issue control operation will be described with reference to FIG. In the figure, each processor 1 outputs the wait state from each processor to the ITC 3 using the wait state signal lines WAIT_0 and WAIT_1. Then, the ITC 3 refers to the wait state of each processor 1 and determines which processor 1
Determines whether to issue a floating interrupt request to. And I
The TC3 sends the floating interrupt request signal line FINT_0 to each processor 1 of the floating interrupt request detected by itself.
It is issued using FINT_1.

The method of determining the floating interrupt request output is as follows, for example. That is, (1) When one or a plurality of processors 1 are in the wait state, the floating interrupt request is issued only to all the processors 1 in the wait state. (2) If all the processors 1 are not in the wait state, issue a floating interrupt request to all the processors 1. The declaration operation of the floating interrupt acceptance process start and the interrupt acceptance process in each processor 1 for the floating interrupt request are executed by using the control bus 4 and the data bus 5 as in FIG. 7, and therefore the description thereof is omitted here.

[0015]

Since the conventional interrupt processing method is performed as described above, in the system configuration shown in FIG. 7, a plurality of processors 1 communicate with the main memory 2 via the control bus 4 and data. Information is frequently transferred using the bus 5. In addition, in the system configuration shown in FIG. 7, the ITC 3 uses the control bus 4 and the data bus 5 to broadcast a floating interrupt request to all the processors 1. In addition, the control bus 4 and the data bus 5 are also used to broadcast the declaration of the start of acceptance processing of floating interrupt requests issued from one processor 1 to all other processors 1. In addition, one processor 1 that executes floating interrupt acceptance processing
The floating interrupt acceptance notification issued by the ITC 3 to the ITC 3 also uses the control bus 4 and the data bus 5. For this reason, there is a problem that the bus usage rate becomes high, and the transfer capacity of the control bus 4 and the data bus 5 becomes a bottleneck of system performance and floating interrupt processing performance.

In addition, in the system configuration shown in FIG.
The control bus 4 and the data bus 5 commonly handle the data stored in the main memory 2 and the floating interrupt request information. For this reason, a floating interrupt request is issued to all processors 1.
In contrast, when broadcasted, all processors must receive the broadcasted interrupt information regardless of the internal state of each processor 1.
If the processor 1 cannot receive the broadcast interrupt information, the broadcast operation needs to be re-executed. Re-executing broadcast operations on the bus will increase bus utilization even more. There is a problem that additional hardware resources are required for the processor 1 to receive the broadcast information at any time.

Further, in the interrupt processing system configured as shown in FIG. 8, the wait state of each processor 1 can be determined. Therefore, it is possible to reduce the bus use cost required for issuing the floating interrupt request broadcast. In addition, it is possible to reduce the cost of using the bus required for determining the processor that accepts the floating interrupt. With the interrupt processing system configured as shown in FIG. 8, it is possible to reduce the total cost of floating interrupt processing in the entire system. On the other hand, however, a wait state signal line uniquely connecting each processor 1 and the ITC 3 and a unique floating interrupt request signal line from the ITC 3 to each processor 1 are required. There is a problem that the number of signal pins of the LSI is increased when the processor 1 and the ITC 3 are each configured by one LSI, or when the number of the processors 1 is increased.

The present invention has been made in order to solve the above problems, and provides an interrupt processing system or the like in which the use of the memory bus by the floating interrupt processing is reduced as much as possible to minimize the influence on the system performance. The purpose is to do. Further, the floating interrupt processing is performed for each processor 1 by controlling the acceptance processing activation of the floating interrupt request by individually using the internal state of each processor 1 while minimizing the number of signal lines between each processor 1 and the ITC 3. It is an object of the present invention to provide an interrupt processing method or the like that further reduces the total cost of the above.

[0019]

An interrupt processing system according to the present invention is, for example, a floating interrupt common signal line (an example of an interrupt line) for transmitting a floating interrupt request from the ITC to all the processors, and between the ITC and all the processors. And a plurality of control common signal lines (an example of control lines) for connecting signals to control the signal transfer operation between the processor and the ITC, and for notifying the ITC of the floating interrupt from each processor, and the ITC and all the processors. And a common signal line for data (an example of a data line) of data for transferring floating interrupt incidental information from the ITC in response to a floating interrupt acceptance notification issued from one processor via a control common signal line. It has the following elements. (A) an interrupt line for transmitting an interrupt request, (b) a control line for transmitting control information, (c) a data line for transmitting data information, (d) connected to the interrupt line and the control line and the data line, and from the interrupt line. Interrupt request is sent to the control line, interrupt processing is performed based on the data information from the data line, the control line is monitored, and another processor receives the interrupt information. A plurality of processor means for canceling the processing relating to the interrupt request of its own processor, (e) connected to the interrupt line, the control line and the data line, and sending the interrupt request to the plurality of processor means through the interrupt line Of the processor means that accepted the interrupt request, The interrupt controller for delivering using the data line data information necessary to interrupt processing on the processor means.

Furthermore, in each processor in the interrupt processing method according to the second aspect of the present invention, after recognizing an interrupt request, the processor is in a wait state in which it is ready to accept an interrupt and is not executing instructions and waiting for an interrupt. Immediately starts interrupt acceptance notification processing,
Further, when not in the wait state, an interrupt acceptance control means for activating the interrupt acceptance notification process in the interrupt acceptable state after delaying by the number of cycles independently determined for each processor is provided.

In the multiprocessor system according to the third invention, the processor monitors the interrupt line and the control line,
It can recognize interrupt acceptance notifications of other processors and has the following elements. (A) Send an interrupt request to a plurality of processors, receive an interrupt acceptance notification from one processor, transmit additional information related to the interrupt request to the processor, and end the interrupt request upon receiving confirmation that the interrupt request has been accepted An external interrupt control device, (b) an interrupt line for connecting the external interrupt control device and the processor, and transmitting an interrupt request from the external interrupt control device to the processor, (c) connecting the external interrupt control device and the processor, A control line for transmitting a control signal between the external interrupt control device and the processor and an interrupt acceptance notification from one of the processors to the external interrupt control device, (d) connecting the external interrupt control device and the processor, and performing the control In response to the interrupt acceptance notification on the line, the above interrupt request Data lines for transmitting additional information about, (e) provided in each processor, monitors control lines and the interrupt lines, the processor means for recognizing the interrupt request.

An interrupt processing method according to a fourth aspect of the present invention comprises a plurality of processors connected by an interrupt line, a control line and a data line, and an interrupt control section, and comprises the following steps. (A) an interrupt request sending step of sending an interrupt request from the interrupt control unit via the interrupt line; (b) a recognition step of recognizing the interrupt request via the interrupt line; (c) the above interrupt by at least one processor. A receiving step for receiving the request, (d)
A notification step of sending the interrupt acceptance notification on a control line by one of the processors that accepted the interrupt request; (e) a transmission step of transmitting information about the interrupt request from the interrupt control unit to the data line; f) A clear step of clearing the acceptance of the interrupt request by detecting the acceptance notification on the control line from one processor.

An interrupt processing method according to a fifth aspect of the present invention includes a plurality of processors connected by an interrupt line, a control line, and a data line and an interrupt control unit, and efficiently determines a processor for interrupt acceptance processing. The interrupt processing method includes the following steps. (A) an interrupt request sending step of sending an interrupt request from the interrupt control unit via the interrupt line; (b) a recognition step of recognizing the interrupt request via the interrupt line; (c) at least one processor c1) An acceptance notification step of issuing an acceptance request for the interrupt request in any of the following cases: when the processor is in a waiting state and waiting for an interrupt, and (c2) when the processor runs out of a predetermined delay time for each processor.

[0024]

The interrupt line according to the present invention makes it possible to issue an interrupt request to all processors independently of the memory bus, suppress the influence on the system performance, and minimize the number of signal lines between each processor and the interrupt control unit. Limit the increase in the number of signal pins.

Furthermore, the control line is constantly monitored by all the processors, and when one processor issues an interrupt acceptance notification to the interrupt control unit, all the other processors see the floating interrupt acceptance notification. By voluntarily canceling the internal interrupt request and acceptance notification pre-processing, it becomes unnecessary for the processor that executes the interrupt acceptance process to cancel the interrupt acceptance process for all other processors.

Further, by transmitting the interrupt request and recognizing the interrupt request via the interrupt line, it is possible to avoid the system efficiency from being lowered due to the excess of the usage rate of the control line and the data line.

Further, as interrupt acceptance control provided inside each processor, when an interrupt request is recognized, an interrupt waiting state or a processor having the shortest interrupt delay time is preferentially accepted based on the state of each processor. By handling the processing, the processing efficiency of the entire multiprocessor system is improved.

[0028]

【Example】

Example 1. FIG. 1 is a block diagram of a multiprocessor system for explaining an embodiment of the present invention. In the figure, 1, 2,
Reference numerals 3, 4 and 5 show the same parts as those of the conventional example shown in FIGS. 6 connects between the ITC 3 and all processors 1
A floating interrupt line (hereinafter referred to as FINT) that transmits a floating interrupt request from the TC 3 to all the processors 1.

FIG. 2 is an internal block diagram of one processor for explaining an embodiment of the present invention. In the figure,
Reference numeral 7 is an interrupt processing unit that controls floating interrupt processing transmitted from the floating interrupt common signal line, 8 is a data processing unit that is in charge of executing instructions and interrupt processing in the processor 1,
A bus request unit 9 interfaces with the control bus 4 and the data bus 5 based on a request from the data processing unit.

Further, FIG. 3 is a circuit diagram showing an internal configuration of the interrupt processing section 7. In the figure, 10, 13, and 2
3 is a latch. 11, 12, 14, 18, 26, 2
Reference numerals 7 and 29 are AND gates. Reference numerals 15, 19, and 28 are OR gates. Reference numeral 16 is a flip-flop. The flip-flop 16 holds that the processor 1 recognizes a floating interrupt request. Reference numeral 17 is a floating interrupt acceptance mask latch. The floating interrupt acceptance mask latch 17 holds the floating interrupt acceptance mask information in the processor 1. 20 is a priority circuit. The priority circuit 20 gives priority among interrupt types in the processor 1. After taking priority, the priority circuit 20 issues a request for interrupt acceptance notification processing to the data processing unit 8. Reference numeral 21 is a floating interrupt delay cycle register that holds the number of cycles. The number of cycles held in the floating interrupt delay cycle register 21 is used to delay the activation of the floating interrupt acceptance / notification process after recognizing the floating interrupt request. 22 is a selector.
24 is a decrementer. The decrementer 24 subtracts the value of the flip-flop 16 from the value of the latch 23 and outputs the subtraction result. The decrementer 24 also outputs a flag indicating that the subtraction result is zero. Reference numeral 25 is a flop-flop that indicates that the number of cycles set in the latch 21 has elapsed since the floating interrupt request was set in the flip-flop 16.

The operation will be described below based on an embodiment of the present invention. The following description is roughly divided into three parts.
The first part is called a floating interrupt request recognition process, and mainly corresponds to the operation of the interrupt processing part 7 of the processor 1. The operation relates to a floating interrupt request recognition operation before the floating interrupt request reaches the data processing unit 8. The second part is called an acceptance notification process, and mainly corresponds to the operation of the data processing unit 8 in the processor. The operation relates to a floating interrupt acceptance operation. The last part is called an interrupt request acceptance notification process, and mainly relates to the operation between one processor and another processor and the ITC 3. This operation relates to a floating interrupt request acceptance / notification operation including the inside and outside of the processor 1, that is, the ITC 3, the control bus 4, and the data bus 5.

First, the process of recognizing a floating interrupt request inside each processor 1 will be described. In FIG. 3, it is assumed that the floating interrupt delay cycle register 21 in the interrupt processing unit 7 of each processor 1 is preset to a value other than zero which is independent for each processor 1. Further, it is assumed that the value is already set in the latch 23 through the selector 22.

In FIG. 1, it is assumed that the ITC 3 detects the presence of a floating interrupt. ITC3 outputs a floating interrupt request to FINT6. Then, all the processors 1 that input FINT6 take the rising differential of FINT6 by the latch 10 and the AND gate 11 in the interrupt processing unit 7. Then, based on the differentiation result, the floating interrupt request passes through the OR gate 15 and the flip-flop 16
Is set to. The floating interrupt request once set in the flip-flop 16 is output from the flip-flop 16. Floating interrupt acceptance mask latch 1
When 7 is set to the acceptance permitted state and the signal line WAIT indicating that the processor 1 is in the wait state is output from the data processing unit 8, the AND gate 18 is opened. When the AND gate 18 opens, the floating interrupt request set in the flip-flop 16 is input to the priority circuit 20 through the OR gate 19.

The floating interrupt request set in the flip-flop 16 is input to the decrementer 24 as a decrement value. When the floating interrupt request is set in the flip-flop 16, the decrementer 24 outputs the result of subtracting 1 from the value set in the latch 23 and the zero flag of the subtraction result. The subtraction result output from the decrementer 24 is input to the decrementer 24 after being set in the latch 23 through the selector 22 in the next cycle. Thus, the value set in the latch 23 in advance continues to be decremented by one every one cycle while the floating interrupt request is output from the flip-flop 16. When the subtraction result becomes zero, the decrementer 24 outputs a zero flag and the flip-flop 2
Set 5. If the latch 17 is in the acceptance-permitted state of the floating interrupt mask within the period in which the flip-flop 25 is set or a reset condition is generated in the subsequent cycles, the AND gate 26 opens and the floating interrupt request becomes the OR gate 19. Through priority circuit 20
Entered in.

The priority circuit 20 takes priority between another interrupt request and the floating interrupt request transmitted from the OR gate 19 in accordance with a predetermined priority definition. If there is no interrupt factor higher in priority than the floating interrupt, the floating interrupt request is sent to the data processing unit 8 as the floating interrupt activation request signal FIN.
T_RQ is issued.

The conditions for setting the floating interrupt request to the flip-flop 16 include the conditions described below in addition to the conditions detected by the differentiating circuit already described. The process of recognizing, accepting and notifying a floating interrupt request consists of bus operations using the control bus 4 and the data bus 5 between one processor and the ITC 3. ITC3 may detect another floating interrupt for the next operation by the end of the bus operation for the notification process of acceptance of floating interrupt acceptance. In this case, the ITC 3 does not negate the FINT signal on the FINT line 6 even after the bus operation is completed,
Leave as N ".

However, in this case, each processor cannot recognize another floating interrupt request. This is because the differentiating circuit rises from the FINT signal which is still "ON" and the differential can not be detected. Therefore, if the FINT signal continues to be asserted in the ITC3 at the end of the bus operation, it is necessary for all the processors to recognize that a new floating interrupt request is being generated.

In order to solve such a problem, the BEND signal and the FACK signal are for notifying the end of the bus operation for the floating interrupt acceptance notification process. Since one of the processors recognizes the floating interrupt acceptance notification to the ITC 3, the F
Output an ACK signal. After that, the ITC 3 outputs the BEND signal via the control bus 4 at the end of the bus operation. The BEND signal means the end of information transmission on the data bus 5 for bus operation. When recognizing the BEND signal on the control bus 4, the control device which has output the FACK signal negates the FACK signal.

For the above reason, the end of the bus operation for the notification process of the floating interrupt acceptance is terminated by the FAC.
It is detected by checking both the K and BEND signals. The AND gate 12 detects the FACK signal and the BEND signal and sets them in the flip-flop 13. The flip-flop 13 indicates the end of the bus operation. If the FINT signal is "ON" at that time, A
The ND gate 14 is opened, and the flip-flop 16 is ITC.
Set another floating interrupt request output from 3.

Incidentally, in one certain processor 1,
The condition for issuing the floating interrupt activation request by the signal FINT_RQ to the data processing unit 8 after setting the recognized floating interrupt request in the flip-flop 16 is that the floating interrupt mask set in the floating interrupt acceptance mask latch 17 is in the acceptance enabled state. It is not decided on the basis of only one thing. The floating interrupt activation request is issued immediately when the processor 1 is in the wait state waiting for an interrupt or enters the wait state. When the processor 1 is not in the wait state, the floating interrupt activation request is issued after the time has elapsed by the number of cycles specific to the processor 1 set in the floating interrupt delay cycle register 21. If the floating interrupt acceptance mask latch 17 is set to the acceptance disapproval state, the AND gates 18 and 26 are closed and the floating interruption request is not transmitted to the priority circuit 20. Therefore, the floating interrupt activation request by the signal FINT_RQ is not output to the data processing unit 8. The floating interrupt request recognition process 100 will be summarized based on FIGS. 3 and 4. In order to issue the floating interrupt activation request signal FINT_RQ to the data processing unit 8, a condition for issuing FINT_RQ must be set in the logic circuit shown in FIG. As shown, the outputs of flip-flop 16 open AND gates 18 and 26. As shown in FIG. 3, the AND gate 18 has a flip-flop 1
6, there are three inputs of the WAIT signal of the latch 17 and the data processing unit 8. Further, the AND gate 26 has a latch 1
7. There are two inputs to flip-flop 26. AND
The gate opens only when all the elements that affect the AND gate are filled.

This condition is shown in FIG. First, there is a WAIT signal sent from the data processing unit 8 as an element for opening the AND gate 18. The WAIT signal indicates that the processor is ready to accept an interrupt in a waiting state. Regarding the WAIT state of the processor, there are the following three conditions. (1) When the processor is in the WAIT state (i.e., the AND gate 18 is a signal WA indicating that interruption is possible).
Open when IT is output). (2) The AND gate 18 has the W
Upon receiving the AIT signal, it is opened promptly. (3) The AND gate 18 does not open when the processor is not in the WAIT state, but when the processor is in BUSY and W
When not in the AIT state, the AND gate 26 opens after a lapse of the number of unique cycles set in the floating interrupt delay cycle register 21.

The AND gate 26 is opened when the output from the decrementer 24 becomes zero and the floating interrupt acceptance mask latch 17 becomes ready to accept. Finally,
In order for the AND gates 18 and 26 to open so that the floating interrupt can be accepted, the floating interrupt acceptance mask latch 17 must be in the acceptance enabled state. If the floating interrupt acceptance mask latch 17 is set to the acceptance-disabled state, the AND gate 1
8 and 26 are closed and no floating interrupt request is transmitted to the priority circuit 20. When all the above conditions shown in FIG. 4 are satisfied, the signal FINT_RQ is sent to the data processing unit 8.
A floating interrupt activation request by is output.

Next, the interrupt processing unit 7 outputs the signal FINT_.
The acceptance process 200 when the floating interrupt activation request issued by the RQ is accepted by the data processing unit 8 will be described with reference to FIG. When the floating interrupt activation request signal FINT_RQ is issued, the data processing unit 8 receives the interrupt activation request in a cycle in which the interrupt processing can be activated as an internal state. The data processing unit 8 sets the IACK signal indicating that the floating interrupt request has been accepted. Even if the interrupt processing unit 7 makes an interrupt start request with the FINT_RQ signal, depending on the state of the data processing unit 8, I
The ACK signal may not be returned immediately. In this case, the interrupt processing unit 7 holds the floating interrupt request set in the flip prop 16 or 25 and continues to output the interrupt activation request by the FINT_RQ signal. When an interrupt activation is reported to the interrupt processing unit 7 by the IACK signal from the data processing unit 8, the AND gate 27 is opened in the interrupt processing unit 7, and the floating interrupt request held in the flip-flop 16 is transmitted through the OR gate 28. clear. And the delayed floating interrupt request held in the flip-flop 25 is cleared. In addition, the selector 22 resets the value set in the floating interrupt delay cycle register 21 to the register 23 through the selector 22. In this way, I
Prepare for the next floating interrupt request transmitted by signal FINT6 from TC3.

Next, the floating interrupt acceptance process in the processor 1 and the floating interrupt acceptance notification process performed between the processor 1 and the ITC 3 via the control bus 4 and the data bus 5, that is, the interrupt request shown in FIG. The notification process 300 of the acceptance of will be described. The data processing unit 8 that has received the floating interrupt activation request starts the floating interrupt processing. The data processing unit 8 uses the ITC3
A bus request is issued to the bus request unit 9 to notify the reception of the floating interrupt and to receive detailed information of the interrupt. Then, the bus request unit 9 performs a bus arbitration operation for using the control bus 4 and the data bus 5, and tries to acquire the right to use the control bus 4 and the data bus 5. Since the bus arbitration operation is not an essential part of the present invention, a detailed description of the operation will be omitted here.

If the right to use the control bus 4 and the data bus 5 can be obtained, the bus request unit 9 sets a FACK signal, which means a floating interrupt acceptance notification, as a signal in the control bus 4. In addition, NA indicating that the processor 1 is not using the bus for the interrupt processing unit 7.
Negate the CK signal. Further, the BSTA signal which means the start of the bus transfer operation is asserted. The BSTA signal and the FACK signal are transmitted to all the other processors 1, the main memory 2, and the ITC 3 and evaluated at the same time. This evaluation determines which of the other processor 1, the main memory 2, and the ITC 3 performs the response operation to the bus transfer operation started by the processor 1. In this case F
Since the ACK signal is asserted, the ITC 3 responds, and the other processors 1 and the main memory 2 do not respond.

Here, all the other processors 1 that have not started the bus transfer operation of the floating interrupt acceptance notification do not directly respond to the bus transfer operation. But,
In the interrupt processing unit 7 of each of the other processors, BS
The TA and FACK signals are asserted. And NAC indicating that the control bus 4 and the data bus 5 are being used by others
The K signal stands inside the processor. Therefore, AN
The D gate 29 is opened to clear the flip-flops 16 and 25 which are the floating interrupt information internally set through the OR gate 28. Further, the value held by the floating interrupt delay cycle register 21 is reset in the latch 23 through the selector 22. In this way, the floating interrupt request is cleared in all the processors 1 other than the bus transfer operation being activated. By this clearing operation, all the processors 1 other than the processor 1 which has acquired the bus use right earliest and has output the floating interrupt acceptance notification on the control bus 4 are activated to accept the same one floating interrupt request. Can be deterred. Within a certain processor 1, the data processing unit 8
After _RQ has already been accepted, another processor 1 may activate the bus transfer operation of the floating interrupt acceptance notification. In this case, the cancel processing unit 7 cancels the floating interrupt acceptance processing.
The L signal is output to the data processing unit 8 and the bus request unit 9. Data processing unit 8 according to the CANCEL signal
Cancels the bus request for the floating interrupt acceptance notification. Further, the data processing unit 8 cancels the interrupt acceptance process and returns to the continuation of the operation before the interruption.

The ITC 3 recognizes the bus transfer operation of the floating interrupt acceptance notification from the processor 1 by the BSTA and FACK signals. The ITC 3 outputs the signal F to the data bus 5.
Outputs detailed interrupt information associated with the floating interrupt request for which INT6 is being asserted. If the ITC3 does not have a new floating interrupt factor, the ITC3 outputs the signal FIN.
Negate T6. If ITC3 has a new floating interrupt factor, ITC3 continues to assert the FINT3 signal. Then, the ITC3 asserts the BEND signal which means the completion of the bus transfer operation. Processor 1 which issued the bus request is B from ITC3.
The floating interrupt detailed information is received from the data bus 5 by observing the assertion of the END signal, and the bus transfer operation of the floating interrupt acceptance notification is ended. Further, the processor 1 transfers the floating interrupt detailed information from the bus request unit 9 to the data processing unit 8. Then, the processor 1 completes the bus request of the floating interrupt acceptance notification, and completes the floating interrupt acceptance processing.

As described above, this embodiment is a multiprocessor system composed of two or more processors. (1) The same interrupt is simultaneously requested to a plurality of processors and the interrupt is accepted earliest. Issued a floating interrupt request in which only the specified processor accepts the interrupt, and issued detailed information associated with the floating interrupt request based on the notification of acceptance of the floating interrupt from one processor, and performed processing for canceling the accepted floating interrupt request. An external interrupt control unit, (2) a floating interrupt common signal line that connects the external interrupt control unit and all the processors, and transmits a floating interrupt request from the external interrupt control unit to all the processors, and (3) external It is connected between the interrupt controller and all processors, and the processor and external interrupts A control common signal line composed of a plurality of signal lines used to control the signal transfer operation between the control units and to send a floating interrupt acceptance notification from each processor to the external interrupt control unit; ) It is connected between the external interrupt control unit and all processors, and responds to the floating interrupt acceptance notification issued from one processor using the control common signal line, and transfers the floating interrupt incidental information from the external interrupt control unit. A common signal line composed of one or more signal lines is provided, and each processor constantly monitors the floating interrupt common signal line and the control common signal line, and when a floating interrupt request is started or within the processor. Floating interrupt acceptance notification is controlled between any one of them and the external interrupt control unit. Characterized in that it recognizes the floating interrupt request with a one when is still held asserted by the interrupt common signal line.

Further, in this embodiment, after each processor recognizes the floating interrupt request, it is immediately or not in the wait state in which the interrupt can be accepted and the instruction is not being executed and is waiting for the interrupt. In this case, the floating interrupt acceptance control means for activating the floating interrupt acceptance notification process under any condition when the interrupt acceptance is enabled after the delay is inserted independently for each processor is provided. Is characterized by.

Further, the setting of the time for delaying the activation of the floating interrupt acceptance notification processing after recognizing the floating interrupt request in each processor is variable.

Further, the derecognition after recognizing the floating interrupt request in each processor is performed when it is confirmed that the floating interrupt acceptance notification processing is activated by the processor itself, or when a processor other than itself is in control common signal line. It is characterized by performing any of the cases when it is confirmed that the notification of acceptance of the floating interrupt request is issued to the external interrupt control unit by using.

As described above, according to this embodiment, since the floating interrupt common signal line for broadcasting the floating interrupt request from the ITC to all the processors in the system configuration is provided, the floating interrupt request is sent to the memory bus. And the effect on system performance can be suppressed and the number of signal lines between each processor 1 and the ITC 3 can be minimized to suppress an increase in the number of signal pins.

Furthermore, by providing a plurality of control common signal lines for transmitting the floating interrupt acceptance notification to the external interrupt control unit and constantly monitoring the values on the control common signal lines by all the processors, a certain one processor accepts the floating interrupt. When the notification is issued to the ITC3, all the other processors see the floating interrupt acceptance notification on the control common signal line, recognize the floating interrupt request inside the processor, and control the floating interrupt acceptance notification already activated. By voluntarily canceling the internal state before outputting to the signal line, the processor executing the floating interrupt acceptance process controls the cancellation operation of the floating interrupt acceptance process for all other processors by using the common signal line etc. A single processor that does not need to perform processing and accepts floating interrupts There is an effect that the time required for the determination is shortened.

Further, the floating interrupt acceptance control means provided inside each processor gives priority to the interrupt waiting state or the processor having the shortest interrupt delay time based on the state of each processor when recognizing the floating interrupt request. By handling the floating interrupt acceptance processing, it becomes possible to adjust the work load between the processors and eventually achieve the processing efficiency of the entire multiprocessor system.

Example 2. In the above embodiment, the control bus 4
Also, an example is shown in which the data bus 5 is also used as a memory bus that transfers data between the main memory device 2 and the processor 1, but it may be configured separately and the same effect is obtained.

Example 3. Further, in the above-described embodiment, as shown in FIG. 1, an example of a multiprocessor system including two processors 1 is shown, but the same effect can be obtained in a multiprocessor system configuration including three or more processors.

Example 4. Further, in the above embodiment, as shown in FIG. 2, one processor connected to the control bus 4 and the data bus 5 is composed of one interrupt processing unit 7 and one data processing unit 8. As shown in FIG. 6, a configuration having two or more interrupt processing units 7a and 7b and two or more data processing units 8a and 8b may be provided, and the same effect is obtained.

Example 5. Although not specifically mentioned in the above embodiment, one or a plurality of processors may be formed on the same semiconductor.

Example 6. In the above-described embodiment, an example in which the floating interrupt delay cycle register 21 in the interrupt processing unit 7 of each processor 1 is set to an independent value in advance for each processor 1 is shown. May be set to a non-zero value and shared by two or more processors. In this case, all the processors sharing the value start the interrupt acceptance notification all at once, but the collision of the processors can be avoided by the bus arbitration system.

[0060]

As described above, according to the present invention, the floating interrupt processing method in a multiprocessor system can be performed at high speed, and the number of signal pins can be increased corresponding to the VLSI implementation of the processor with the progress of semiconductor technology. Can be kept to a minimum.

Further, the control line is constantly monitored by all the processors, and the processors other than the processor which has issued the interrupt acceptance notification voluntarily cancel the interrupt request and the acceptance notification pre-processing in the processor by seeing the floating interrupt acceptance notification. As a result, it becomes unnecessary for the processor that executes the interrupt acceptance processing to cancel the interrupt acceptance processing for all other processors.

Further, by transmitting the interrupt request and recognizing the interrupt request through the interrupt line, it is possible to avoid a decrease in system efficiency due to excess of the usage rate of the control line and the data line.

Further, in the interrupt acceptance control provided in each processor, when the interrupt request is recognized, the interrupt waiting state or the processor having the shortest interrupt delay time is prioritized to accept the interrupt based on the state of each processor. Since it is in charge of processing, the processing efficiency of the entire multiprocessor system is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the inside of one processor according to an embodiment of the present invention.

FIG. 3 is a logic diagram showing a configuration of an interrupt processing unit inside a processor according to an embodiment of the present invention.

FIG. 4 is a processing flow chart showing a procedure of an interrupt processing unit inside a processor according to an embodiment of the present invention.

FIG. 5 is a processing flow chart showing a procedure of an interrupt processing unit inside a processor according to an embodiment of the present invention.

FIG. 6 is an internal block diagram of a processor according to another embodiment of the present invention.

FIG. 7 is a configuration diagram showing a conventional multiprocessor system.

FIG. 8 is a configuration diagram showing another conventional multiprocessor system.

[Explanation of symbols]

 1 processor 3 external interrupt control unit 4 control common signal line 5 common signal line 6 floating interrupt common signal line 7 interrupt processing unit 8 data processing unit 9 bus request unit 100 recognition process 200 acceptance process 300 notification process

Claims (5)

[Claims] 1. An interrupt processing system having the following elements: (a) an interrupt line for transmitting an interrupt request, (b) a control line for transmitting control information, (c) a data line for transmitting data information, and (d) the interrupt line. It is connected to a control line and a data line, receives an interrupt request from the interrupt line, sends an interrupt acceptance notification to the control line, performs interrupt processing based on the data information from the data line, and controls the control line. A plurality of processor means for monitoring and canceling the processing relating to the interrupt request of the own processor when another processor means receives the interrupt information, (e) is connected to the interrupt line, the control line and the data line, and is connected to the processor means. The interrupt line is sent to the interrupt request line, and the interrupt line is the highest among the processor means that accepted the interrupt request. The interrupt controller for delivering using the data line data information necessary for interrupt processing to the processor unit which issued the interrupt acceptance notification to. 2. The processor means, after recognizing an interrupt request, in a wait state in which an interrupt can be accepted and is not executing an instruction and is waiting for an interrupt, and when not in a wait state, for each processor. Claims characterized in that interrupt acceptance control means for activating interrupt acceptance notification processing is provided under any condition when interrupt acceptance is enabled after the delay is inserted independently for a predetermined time. The interrupt processing method described in item 1. 3. A multiprocessor system having a plurality of processors and having the following elements: (a) An interrupt request is sent to the plurality of processors, an interrupt acceptance notification is received from one processor, and additional information on the interrupt request is sent to the processors. And (b) connecting the external interrupt control device to a processor and receiving an interrupt request from the external interrupt control device to the processor. An interrupt line for transmission, (c) connecting the external interrupt control device and the processor, and transmitting a control signal between the external interrupt control device and the processor, and an interrupt acceptance notification from one of the processors to the external interrupt control device. Control line, (d) External interrupt controller and plug A data line that connects a sessor and transmits additional information related to the interrupt request in response to the interrupt acceptance notification on the control line, (e) is provided in the processor, monitors the interrupt line and the control line, and issues an interrupt request. Recognizing processor means. 4. A plurality of processors connected by an interrupt line, a control line, and a data line, and an interrupt control unit,
An interrupt processing method including the following steps: (a) an interrupt request sending step of sending an interrupt request from an interrupt control unit via an interrupt line; (b) a recognition step of recognizing an interrupt request via an interrupt line; ) A receiving step of receiving the interrupt request by at least one processor, (d)
A notification step of sending the interrupt acceptance notification on a control line by one of the processors that accepted the interrupt request; (e) a transmission step of transmitting information about the interrupt request from the interrupt control unit to the data line; f) A clear step of clearing the acceptance of the interrupt request by detecting the acceptance notification on the control line from one processor. 5. A plurality of processors connected by an interrupt line, a control line, and a data line, and an interrupt control unit are provided,
An interrupt processing method including the following steps: (a) an interrupt request sending step of sending an interrupt request from an interrupt control unit via an interrupt line; (b) a recognition step of recognizing an interrupt request via an interrupt line; c) At least one processor accepts the interrupt request in any of the following cases: (c1) the processor is in a waiting state and waiting for an interrupt, and (c2) the processor runs out of a predetermined delay time for each processor. Receiving notification step to notify.