JPS6132161A - Information transfer device of processing system - Google Patents

Abstract

PURPOSE:To open a bus immediately at congestion of processing of a slave module by acquiring a bus cycle in a synchronizing system and returning a reply to a command in data transfer and interruption to the bus. CONSTITUTION:When a request of data transfer takes place in a master module 30 at first, a bus request line ARB is set in a clock period succeeding thereto and a bus mater is acquired. The master module 30 adopts address bus processing flow at the succeeding clock period and transmits a bus ID, a command CMD and an address ADR. A command response CR is returned to the master module 30 at the next clock period from the slave module 32 receiving the address corresponding to the own logical address. In this case, if the execution is disabled, since, e.g., 01 is returned, the master module 30 gives up the said data transfer and opens the bus 10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing system, and particularly to an information transfer device used therein.

11. The bus system used in processing systems such as computers has a common signal bus, or bus, that interconnects each component or module that makes up the system, and a master module that causes data transfer on the bus. Data transfer is performed between the slave module and the slave module that accepts the activation of this data transfer.

As is well known, there are two types of bus systems: synchronous and asynchronous. The synchronous type has the advantage of using slower circuit elements than the asynchronous type, and therefore consumes less power. However, since the circuit operation proceeds in synchronization with a lock common to each module, the data transfer rate depends on the clock speed (frequency). Therefore, in order to transfer a large amount of data in a short time, a high-speed clock must be used.

For example, in a processing system that handles image data, the higher the resolution of the image, the greater the overall amount of information. Furthermore, in order to handle a large number of images, the processing capacity of the entire system must be large. For example, large systems require multiple modules to operate simultaneously on the bus at transfer rates of several megabytes per second. In order to increase the processing capacity of a system in this way, one factor is the high speed of data transfer within the system.

In the conventional bus transfer method, there is a method in which a master module specifies an address to a slave module and then waits until data is actually transferred. For example, when receiving data from a slave module, the address space of the slave module is specified. At that time, if the slave module is engaged in other operations,
The master module will wait until the operation is completed. Therefore, during the waiting period, the bus is occupied by that module and cannot be used by other modules.

Generally, interrupt requests are generated asynchronously from each module of the processing system. The interrupt control requires an interrupt control line that is independent of the control line for normal data transfer control. For example, by arranging interrupt request lines and response lines for each module or module group,
Setting interrupt priorities and transferring interrupt vectors used separate signal lines or address or data lines.

1--In view of these demands, it is an object of the present invention to provide an information transfer device with a simple configuration that requires less time for data transfer.

imitate 1j According to the present invention, there is a common transfer path that commonly connects a plurality of structural units constituting a processing system and transfers information, and a common transfer path that is provided in each of the structural units and that transfers information in synchronization with a clock having a predetermined frequency. In an information transfer device in a processing system, the common transfer path includes a first signal line that defines the priority order of each of the plurality of constituent units, and at least: a second signal line for transmitting a second signal including designation information specifying one of the plurality of structural units; and a third signal line for transmitting a third signal indicating that the structural unit is responsive to information transfer. and a fourth signal line for transferring information, the control means includes:
When requesting the use of a common transfer path from one's own constituent unit to another constituent unit in synchronization with the clock, the first signal is output to the first signal line and the constituent unit is prioritized over the own constituent unit. monitoring the state of the first signal line from the higher constituent unit;
When the first signal is not present on any of the first signal lines, the second signal is output to the second signal line after the first signal output, while the self-constituent unit When receiving a second signal specifying a signal from the second signal line, if the own constituent unit is capable of responding to this, it outputs a third signal to the third signal line and outputs the second signal. Thereafter, when the third signal is received, subsequent information transfer proceeds, and when the third signal is not received, the common transfer path is opened.

According to one aspect of the invention, the plurality of structural units include a central processing system, and the second signal includes a request signal requesting an interrupt to the central processing system.

Next, embodiments of the information transfer device according to the present invention will be described in detail with reference to the accompanying drawings.

In the processing system shown in FIG. 1, each of the constituent units (elements) or modules 12, 14 and 18 making up the system are commonly connected to a common signal transfer path (bus) or bus IO. For example, the module 12 in this embodiment is a memory module having a system memory 18 and a switch interface (BIF) 2o.

In addition, the module 14 includes an input/output device Cl1 in this embodiment.
0) I10 module with 22 and BIF 2G. Ilo 22 is not only a normal input/output device, but also a
Includes external storage devices and communication line interfaces.

In this embodiment, the module 18 includes a central processing system and a BIF.
This is a central processing system module having 21. The central processing system includes a central processing unit 24, a local memory 26, and an Il
o 28 are interconnected to the BIF 20 by an internal bus 30. The BIF 21 may have substantially the same configuration as the BIF 20 of other modules, but differs from the other BIFs 20 in that it includes an interrupt processing circuit 800, which will be described later.

These modules 12, 14 and 18 are understood to be understood as logical building blocks, i.e. logical modules, for the purpose of understanding the present invention, which may consist of a single physical unit or may be physically separated. It may be composed of multiple units.

Also, each module may be provided in multiple numbers,
It may also be singular. Therefore, a plurality of central processing system modules IB may be connected, and there may be a plurality of CPUs 24 within the central processing system module 16.

Of course, the CPU may be included in the Ilo 22 of the I10 module 14. Bus 10 and Each Module] 2. A bus system is constituted by the BIF 20 included in 14 and 16. In this embodiment, the connection lines between each module are bus claw, BCLK, address bus AB,
Command response CR, data bus DB, f-Thalesbons DR, and arbitration bus A
Consists of RB etc. Note that each of these connection lines does not necessarily consist of a single connection line, but may include a plurality of connection lines.

Among the modules 12, 14 and 1B, the module that initiates data transfer on the bus 10 is referred to as the master module, and is designated by reference numeral 30 in FIG. is called a slave module and is designated by the reference numeral 32.

As shown by dotted lines 34 and 38 in the figure, in this embodiment, when the master module 30 specifies an address to the slave module 32, a command response is sent back from the slave module 32 to the master module 30. Further, when data is transferred between the master module 30 and the slave module 32, a data response is sent back from the slave module 32 to the master module 30.

The bus clock BCLK is supplied from any module included in this system. Alternatively, the clock may be supplied from a clock source independent of these modules.

In this embodiment, the address bus AB consists of a bus identification line It), a command line CHID, an address line ADR, and a mask line MSK, as shown in FIG. 3, and its data format is shown in FIG. 4A. As you can see,
The bus identification I11 consists of 3 bits and indicates the type of information content. For example, rGQOJ is free (I
II) LE), rllllJ indicates an interrupt, and the command CHD also consists of 3 bits, for example, rooo J
Indicates a read (CREAII) and data is transferred from the slave module to the master module, and in roll indicates a write (%1RIT) and data is transferred from the master module to the slave module.

The address ADH consists of 24 bits and can specify the logical address space of FFFFFF(H) including all modules in the system. In this embodiment, the data bus [l
B consists of 16 bits, that is, 2 bytes, and the mask line MSK of the address bus AO has 2 bits for selectively masking the upper and lower bytes of the 16 bits of data transferred based on the address designation. have

This simplifies the circuit configuration of the module's receiving register.

As shown in FIG. 5, in this embodiment, arbitration bus ARB consists of one hold line HOLD and 16 bus request lines BRO to BR15. The priority is
Highest in order of BRO to BR15 and HOLD. That is, H.O.
The LD line has the highest priority. For example, if module A's priority is 3rd and module B's priority is 2nd, higher than module A, module A is assigned to BR13 and module B is assigned to +3R]4, as shown in Figure 5. . Hold line) 10L [l is commonly connected to each module.

Each module is also connected to monitor the BR line of a module higher in rank than its own module. That is, module A is BRI4, BR15 and H
Monitor the status of OLD. Also, module B is all
! 15 and HOL[1] status.

For example, the arbitration control circuit 100 in the BIF 20 of module A is configured as shown in FIG. 6, for example. This control circuit 100 is provided in each module 12, 14 and 1B, respectively, and is connected to a NOR game (NOR game) 102. NAN [l gate 104. and three 7 lip-flops (FF) 108.108.110.

The NOR gate inputs the HOLD line and the BR lines of modules with higher priority than itself, in this case BR14 and BR15, and its output 112 is N
It is connected to the input of AND gate 104, and its own bus request BR13 is input to the other input of the latter.

3 flip-flops 1041.108 and 110
are supplied with a system clock BCLK, and constitute a shift register that shifts in response to the clock BCLK. The output of each stage is used as a signal that defines each timing in the arbitration process.

For example, the output 114 of the first stage 10B defines the timing for sending out the address ADH, command CHD, etc. from that module.

This will be explained in detail later.

Referring to FIG. 7, bus acquisition and inter-module arbitration processing by this system are performed according to the illustrated flow. For example, as shown in FIGS. 15(E) and 15(F), at time t1, module A
In step 2, if module B issues a data transfer request to each other module using bus lO (
200), and in response to the bus clock BCLK that arrives next to the generation of these requests (202, FIG. 8).
204), these modules make the signal BR significant (2QB).

In this example, module A first makes signal BR13 significant. At this time, module A must monitor the BR wires of all modules with higher priority than its own module22.
4) If a bus request BR is issued from another high-priority module at that time, it waits (242. Fig. 10). Therefore, in this example, module B makes signal BR14 significant on the next subsequent clock while module A takes the bus mask (22B). The module A that has performed the bus cycle acquisition process 244 receives the signal BR.
is turned off (248) and the process moves to data transfer processing. Therefore, module B becomes the bus master in the next clock cycle.

For example, when a transfer request occurs at times t3 and t4,
At the next clock, both modules simultaneously make signal BR significant. In this example, since module B has a higher priority than A, that is, module B does not monitor the signal BR of module A, which has a lower priority, module B becomes the bus master in the next clock cycle. Therefore, module A can become the bus master in the next clock cycle.

When the same module wants to continuously transfer data 2 bytes at a time (248), it makes the signal line HOLD significant in the next cycle following the previous transfer cycle (hold request 250), as shown in Figure 18. When module A becomes the bus master and transfers data over two clock cycles, the signal line 10LD from module A becomes significant in the next clock cycle. As a result, even if there is a bus request BR from another module B with a higher priority, it will be queued until the signal HOLD is released.

The operation of this system will be explained by taking the READ operation shown in FIG. 17 as an example. As will be explained below, in this system, data transfer is normally performed using six cycles of the pass clock BCLK. The overall flow of the data bus DB is as shown in FIG. In the transfer condition specification step 300, first, as shown in FIG. 17(B),
When a data transfer request occurs in the master module 30 at time tlG, the bus request BR is set as described above in the following clock cycle (C').
, acquires bus mastership (same (El)).

In the following clock cycle, the master module 30 sends out the bus 10, command CHD, and address ADH as shown in the address bus processing flow at 304 in FIG. 12 ((D), (F), and (G) in FIG. 17). . In this example, since a READ command is sent, the command beat 2 is roooJ.

The slave module 32 that has received the address corresponding to its own logical address sends the command response OR back to the master module 30 in the next clock cycle (FIG. 17(H)).
consists of 2 bits in this embodiment; "00" indicates no response, "Ol" indicates executable, "10" indicates operating (not executable),
Also, "11" indicates an error.

For example, when slave module 32 was occupied with other operations, "lO" is returned. When the address ADH sent from the master module 30 indicates a write-prohibited area, an error "11" is returned. Furthermore, if it is out of the logical address space, the command response CR will not be returned (00) in this bus clock cycle. If these cannot be executed, the master module 30 abandons the data transfer and retries to acquire the bus mastership later.

The BIF 20 of each module is provided with a command response processing circuit 700 as illustrated in FIG. This circuit consists of three types of signal lines I of the address bus AH.
D, a decoder (D
EC) 702, which outputs a signal 5ELECT when its module is addressed as a slave module 32. Further, the decoding result 712 is transferred to the error detection circuit 704, and the latter performs a logic check such as parity.

Received address data 10. Once the normality of CMD and ADR is established, signal k is output. As shown, these signal lines are input to an encoder circuit (ENC) 710 through an AND gate 706 along with a signal line BUSY indicating that the module 32 is in use. The output 14 of AND gate 708 indicates that the module 32 is in use even though address data is successfully received. In addition, the input cuff 1B of the encoder 710 has an AND
Signals 5ELECT, M- and BT from gate 708
The AND output of IT'f is given. This output indicates that the module 32 is free and available for the data transfer.

These signals 7]4 and 718 are encoded into the aforementioned 2-bit command response CR by the encoding circuit 710 and sent back to the master module 30. Note that each circuit element of the command response processing circuit 700 performs these operations in synchronization with the bus clock BCLK.

In a system that returns a command response in this way, in addition to returning a data response (described later), the redundancy of response processing increases, improving reliability.

This greatly improves bus usage efficiency, especially when a slave module encounters an error handling situation or is busy, since the bus can be handed over to another module without occupying the bus until the problem is resolved. Contributing.

Upon receiving the command response CR, the master module 30 performs command response processing 320. If executable is "01", mask MSK is executed in the next clock cycle.
(FIG. 17(I)), and further, in the subsequent bus clock cycle, the master module 30:
Data is transferred (same (J)).

Since the example being described is a READ operation (344 FIG. 13), the slave module 32 to the master module 30
The data is transferred to (34B). Of course, during the WRITE operation, data is transferred from the master module 3o to the slave module 32 (34B, Figure 18 (J
)).

From the slave module 32, R
In the case of EAD operation, a data response OR indicating the data reception result is sent back to the master module 3o (first
Figure 7 (K)). If it is a WRITE operation, the data response OR indicating the end of data transmission is the master module 3.
0 (FIG. 18(K)).

In this embodiment, the data response DR consists of 2 bits, "00" indicates normal, r IOJ indicates data transfer error,
Further, "11" indicates an error, and "ol" is not defined. For example, when the slave module 32 detects a transfer error in WRITE, "10" is returned, and when another error occurs in the slave module 32, "11j" is returned.

In response, the master module 30 performs data response processing 380.

As can be seen from the previous explanation, Fig. 17 and 1
The data transfer operation shown in FIG. 8 is performed in a pipeline manner between each module. If a module outputs one information unit, such as a bus command, in one cycle of the bus clock BC:LK, other modules can issue a bus command in the next clock cycle. Of course, the same applies to subsequent responses, data transmission, etc. If we look at one module, the bus request BR
When a command response CR is received for a module, subsequent processing automatically proceeds in that module, so if another module issues a new bus request, there is a possibility that it will be effectively accepted.

In this way, the bus transfer operation is performed by bus clock BCLK.
Completed in a cycle. In the conventional synchronous bus transfer method, there was no return of a command response, and there was a system that sent data following a bus command and waited for the return of a data response. However, in the method of this embodiment, if the slave module 32 encounters an error process or is busy after sending the bus command, the master module 30 releases the bus 10 upon reception of the command response, so from then on modules can use bus IO. Therefore, the usage efficiency of the bus 10 is improved.

In a system that performs 6-cycle pipeline transfer, uses TTL devices as circuit elements, and uses llRAM with an average memory access time of about 100 to 300 nanoseconds, the bus clock BCLK is about 100 nanoseconds.
~200 nanoseconds (approximately 10M in frequency) Iz~5MH2)
, preferably a clock period of around 150 nanoseconds (about (1,?MHz)) can be advantageously used.

Regarding the above operations, the processing on the slave module 32 side is shown as the processing flow of the response bus in the 14th section.
It is a diagram. Slave module 3 from now on
2, when the transfer condition is specified by receiving the command CHD (400), the command is analyzed and the result is returned to the master module 30 (420). In response, the master module 30 executes command response processing 32G and transfers data with the slave module 32 (480). slave module 32
In the case of READ, the normality of the received data is checked and the status is sent to the master module 30. Also W
In the case of RITE, status information is sent to the master module 30 upon completion of data sending. In response to this, the master module 30 performs data response error processing (500).

In this embodiment, interrupt requests generated in each module to the central processing system module 16 are processed using the address bus AB. As previously mentioned, address bus AH has the data format shown in FIG. 4A, but interrupts are identified by setting all 1's on the ID line, as shown in FIGS. 4B and 4C. Ru. As shown in FIG. 4B, an interrupt request sends command CHD to rooIJ or WRITE (C:P
write to U24), and the interrupt response sets it to all ``0''.
'', that is, READ (read from peripheral module). Further, the address field ^DR is set to the interrupt priority level of the module in question. Further, in a system in which there are a plurality of central processing system modules 16 or a plurality of CPUs 24, information specifying them may be included in the address portion ADR.

In this embodiment, the interrupt priority level can be set to 7 levels for the main level and 8 levels for the sub level, that is, 58 levels in total can be set. In other words, interrupts can be issued from 56 modules at the same time without returning an interrupt vector.

An interrupt request is generated in a peripheral module asynchronously with a clock. As shown in FIG. 20, for example, at time t14
When an interrupt request occurs in a certain module (19th
In interrupt request processing 802, the bus request line BR of the module is activated in response to the first arriving bus clock 7 (FIG. 20(C)). Therefore, as mentioned above, when the contention with other modules is adjusted through the arbitration process and /< master is taken, the module with the highest priority at that time sends interrupt request data to the address bus AH in the format shown in FIG. 4B. (Figure 20 (D) ~
(G)). The central processing system module 18 that received this
The command response OR is returned in the next clock cycle ((H)). Therefore, if execution is possible at this time, "01" is returned (804). This completes the interrupt request processing.

As described above, this interrupt request data includes the interrupt priority level, and the central processing module 16 analyzes the priority level (80B). The module analyzes the interrupt request and returns an interrupt response to the module with the highest priority at that time. This is also done by activating the normal bus request line BR, as shown in FIG.

In interrupt response processing 808, the central processing system module 1B activates the bus request line BR of the central processing system module IB in synchronization with the bus clock BCLK (FIG. 21(B)).
. Therefore, as mentioned above, when the conflict with other modules is adjusted through arbitration processing and the bus master is taken over, interrupt request data is sent to the address bus AB in the format shown in FIG. 4C (FIG. 21 (C) to ( F)). The module that receives this returns a command response CR in the next clock cycle ((G)). Therefore, if execution is possible at this time, "01" is returned.

Therefore, the module that requested the interrupt transfers data necessary for processing the interrupt to the central processing system module 1B in synchronization with the bus clock ((H)). In response, the central processing system module 18 sends the data response D
R is returned and the corresponding interrupt service processing 808 is executed. In service processing 808, processing based on an interrupt request is performed in the same way as normal data transfer.

As can be seen from the above description, in this embodiment, the processing specific to the interrupt request is completed in three pass clock cycles until the return of the command response OR.

Thereafter, interrupt priority level information and the like can be transferred using the normal bus transfer former (/).

In this embodiment, the interrupt response described above is sent back to the master module via the system bus 10 by an interrupt response circuit provided in the bus interface 21 of the central processing module IB. The interrupt response circuit notifies the CPU 24 of the occurrence of an interrupt request as described above, and returns an interrupt response to the master module. This interrupt response simply means that the CPU 24 has been notified of the occurrence of an interrupt request.

However, it is not necessarily necessary to provide hardware for returning interrupt responses in this way. For example, the CPU 24 accepts the occurrence of an interrupt request, does not return the above-mentioned interrupt response, and then, after the CPU 24 starts a service corresponding to the interrupt request, sends data according to the content of the service. , the interrupt may be returned to the module that requested the interrupt through normal data transfer processing.

In the latter system configuration, an interrupt response in the sense described above will not be returned.

As described above, the present invention is configured to secure bus cycles in a synchronous manner for normal data transfers and interrupts via the bus, and to return the status of responses to the commands. Therefore, even when processing in the slave module becomes congested, the bus is immediately released instead of waiting and occupying the bus until the congestion is resolved as in the prior art. Therefore, the time required for data transfer is shortened, and the transfer capacity of the entire system is increased. This is effective when there is a sudden error or when the system is busy.

Furthermore, if the interrupt request is configured to use the same synchronous format as the normal bus request, the device configuration is simplified because an interrupt request line and its response vector return line are not required.

Furthermore, compared to the asynchronous transfer method, low-speed, low-power consumption standard elements such as TTL elements are advantageously used, and the transfer efficiency of the entire system is maintained high.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information transfer device of a processing system according to the present invention, FIGS. 2, 3 and 5 are explanatory diagrams showing the configuration of a bus system, and FIGS. i4A to 4C are address An explanatory diagram showing the bus format; FIG. 6 is a circuit functional diagram showing an example of the arbitration circuit included in each module shown in FIG. 1; FIGS. 7 to 14 show the operation of the device shown in FIG. 1. 15 to 18 are timing diagrams to explain the operation of the device shown in FIG. 1, and FIG. 19 is an operation flow diagram to explain the interrupt operation of the device shown in FIG. 1. 20 and 21 are timing diagrams for explaining the interrupt operation of the device shown in FIG. 1, and FIG. 22 is a configuration example of a command response return circuit in each module of the device shown in FIG. 1. FIG. 1 10,, bus 20.21. , bus interface 30, . . . master module 32, . . . slave module +00. , Arbitration circuit 800, Interrupt processing circuit AB, Address bus ADR, Address line BR, Bus request line CHD, Command line CR, Command response/<SDB, Data Bus DR, Data Response Bus 10, Bus III Line Patent Applicant Fuji Photo Film Co., Ltd. - Atsushi / Figure #2 Concave #3 Concave 47 Figure Tail ar3 L9 Concave #to Figure Qin 11 Figure #12 Figure Vermilion /3 drawings/, d drawing Book lq drawing L15 concave tail/ro drawing (E) r<”sma 2ri
a'4tsotD) B
a JQ procedural amendment February 14, 1985

Claims (1)

[Claims] 1. A common transfer path that commonly connects a plurality of structural units constituting a processing system and transfers information; An information transfer device in a processing system including a control means for controlling information transfer on the transfer path,
The common transfer path transfers a first signal line that defines the priority order of each of the plurality of structural units, and a second signal that includes at least designation information that specifies one of the plurality of structural units. a second signal line; a third signal line for transferring a third signal indicating that the structural unit is capable of responding to information transfer; and a fourth signal line for transferring the information; The control means outputs a first signal to the first signal line when requesting the use of the common transfer path from the own constituent unit to another constituent unit in synchronization with the clock; The first constituent unit from the constituent unit with a higher priority than the constituent unit of
monitors the state of the signal lines, and if the first signal is not present on any of the first signal lines, after outputting the first signal, the second signal is output to the second signal line. On the other hand, when receiving a second signal specifying its own constituent unit from the second signal line, if the own constituent unit is able to respond to this, it outputs a third signal to the third signal line. line, and when a third signal is received after outputting the second signal, the subsequent information transfer proceeds, and when the third signal is not received, the common transfer path is opened. An information transfer device for a processing system characterized by: 2. In the information transfer device according to claim 1, the plurality of structural units include a central processing system, and the second signal includes a request signal requesting an interrupt to the central processing system. An information transfer device characterized by: 3. The information transfer device according to claim 2, wherein the control means associated with the central processing system has an interrupt processing means for processing the request signal according to a predetermined interrupt priority order, and a second The signal includes a response signal for allowing an interrupt requested to the central processing system, and the interrupt processing means responds to the interrupt request signal when allowing the requested interrupt for the central processing system. An information transfer device characterized in that a second signal is sent back to a related structural unit. 4. In the information transfer device according to claim 1, the plurality of structural units include a central processing system, and the common transfer path defines a predetermined interrupt priority and transmits interrupts to the central processing system. An information transfer device, further comprising a fifth signal line for requesting an interrupt, wherein the control means uses the fifth signal line to request an interrupt asynchronously with the clock. 5. In the information transfer device according to claim 1, the common transfer path includes a sixth signal line that transfers a sixth signal indicating a reception state of the information from a fourth signal line. . An information transfer device, wherein the control means inspects the reception state of the information from the fourth signal line and outputs a sixth signal to the sixth signal line. 6. In the information transfer device according to claim 1, the frequency of the clock is about 5 MHz to about 10 MHz.
An information transfer device characterized by being in the Hz range.