JPH06342983A - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JPH06342983A
JPH06342983A JP13037993A JP13037993A JPH06342983A JP H06342983 A JPH06342983 A JP H06342983A JP 13037993 A JP13037993 A JP 13037993A JP 13037993 A JP13037993 A JP 13037993A JP H06342983 A JPH06342983 A JP H06342983A
Authority
JP
Japan
Prior art keywords
layer pattern
surface layer
pattern
holes
inner layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13037993A
Other languages
Japanese (ja)
Inventor
Kotaro Takigami
耕太郎 滝上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP13037993A priority Critical patent/JPH06342983A/en
Publication of JPH06342983A publication Critical patent/JPH06342983A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits

Abstract

PURPOSE:To enable a continuity between patterns of different layers without necessity of a plating step by putting a surface layer pattern, an inner layer pattern and the surface layer patterns in a continuity with conductive paste. CONSTITUTION:A surface layer pattern 1, an inner layer pattern 2, an inner layer pattern 3 and a surface layer pattern 4 are formed on both surfaces of boards 11, 12. Then, through holes 5a, 5b passed through the pattern 1, the board 11 and the pattern 2, and through holes 5c, 5d passed through the pattern 3, the board 12 and the pattern 4 are formed. The holes 5a-5d are filled with conductive pastes 7a-7d by printing, the boards 11, 12 are laminated by holding a prepreg material 17 at a center, and through holes 6a, 6b passing the entirety are formed. Then, conductive paste 8a is selectively filled in the hole 6a by printing, and the hole 6b remains as it is. The pastes 7a-7d and 8a protruding from the patterns 1, 4 are polished to the same plane.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多層配線基板に関し、特
にパターンの層数がより多いものに適用して有用なもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and is particularly useful when applied to a board having a larger number of pattern layers.

【0002】[0002]

【従来の技術】電子機器の機能の高度化,複雑化に伴な
い1素子内での電極数の増加や、同一パッケージ内での
多数の素子の組合せが必要になってくる。このため、最
近ではプリント基板も多層化が進められている。
2. Description of the Related Art As the functions of electronic devices have become more sophisticated and complicated, it is necessary to increase the number of electrodes in one element and to combine a large number of elements in the same package. For this reason, in recent years, multilayer printed circuit boards have been promoted.

【0003】従来技術における多層配線基板において
は、表層パターンと内層パターンとを導通する場合等、
異なる層のパターン同志を導通する場合には、表層から
所定の層に向かって設けた貫通孔にスルーホールメッキ
を施したバイアホール(導通のみのスルーホール)を形
成している。
In a conventional multi-layer wiring board, when the surface layer pattern and the inner layer pattern are electrically connected,
When the patterns of different layers are made conductive, a through hole provided from the surface layer toward a predetermined layer is plated with a through hole to form a via hole (through hole for conduction only).

【0004】[0004]

【発明が解決しようとする課題】上述の如く従来技術に
おいては、異なる層のパターン同志の導通は、スルーホ
ールメッキを有するバイアホールにより得ているため、
多層配線基板の製造工程においてメッキ工程が必要とな
る。このメッキ工程に要する設備、特に電気設備は大嵩
のものであるため、生産設備が大形となるばかりでな
く、メッキ工程が必要であるために工程も複雑になると
いう問題を有する。
As described above, in the prior art, since the conduction of the patterns of different layers is obtained by the via hole having the through hole plating,
A plating process is required in the manufacturing process of the multilayer wiring board. Since the equipment required for the plating process, especially the electric equipment, is bulky, not only the production equipment becomes large, but also the plating step is required, which complicates the process.

【0005】本発明は、上記従来技術に鑑み、メッキ工
程を必要とすることなく異なる層のパターン同志を導通
し得る多層配線基板を提供することを目的とする。
In view of the above-mentioned conventional technique, it is an object of the present invention to provide a multi-layer wiring board capable of conducting patterns of different layers without requiring a plating process.

【0006】[0006]

【課題を解決するための手段】上記目的を達成する本発
明の構成は、三層以上のパターンを形成した多層配線基
板において、表層パターンと内層パターン及び表層パタ
ーン同志の導通を確保するための貫通孔に印刷により導
電性ペーストを充填したことを特徴とする。
Means for Solving the Problems The structure of the present invention which achieves the above-mentioned object is a through-hole for ensuring continuity between a surface layer pattern, an inner layer pattern and a surface layer pattern in a multilayer wiring substrate having a pattern of three or more layers. The hole is filled with a conductive paste by printing.

【0007】[0007]

【作用】上記構成の本発明によれば表層パターン同志及
び表層パターンと内層パターンとは導電性ペーストによ
り導通が確保される。
According to the present invention having the above-mentioned structure, the surface layer patterns are electrically connected to each other, and the surface layer pattern and the inner layer pattern are electrically connected by the conductive paste.

【0008】[0008]

【実施例】以下本発明の実施例を図面に基づき詳細に説
明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0009】図1に示すように、本実施例に係る多層配
線基板Iは表層パターン1,4及び内層パターン2,3
を有する四層の基板であり、表層パターン1と内層パタ
ーン2とは印刷により貫通孔5a,5bに充填した導電
性ペースト7a,7bで、また表層パターン4と内層パ
ターン3、及び表層パターン1,4同志は同様に貫通孔
5c,5d,6aに充填した導電性ペースト7c,7
d,8aによりそれぞれ導通してある。このときの導電
性ペースト7a〜7d,8aとしては銀パラジウムもし
くは銅のペーストが好適である。
As shown in FIG. 1, the multilayer wiring board I according to the present embodiment has surface layer patterns 1 and 4 and inner layer patterns 2 and 3.
The surface layer pattern 1 and the inner layer pattern 2 are conductive pastes 7a and 7b filled in the through holes 5a and 5b by printing, and the surface layer pattern 4 and the inner layer pattern 3 and the surface layer pattern 1, 4 are conductive pastes 7c, 7 filled in the through holes 5c, 5d, 6a in the same manner.
They are electrically connected by d and 8a. As the conductive pastes 7a to 7d and 8a at this time, silver palladium or copper paste is suitable.

【0010】図2は上記多層配線基板Iの作製時の各工
程の態様を示す断面図である。同図に基づき多層配線基
板Iの作製方法を説明する。
FIG. 2 is a cross-sectional view showing an aspect of each step in manufacturing the multilayer wiring board I. A method of manufacturing the multilayer wiring board I will be described with reference to FIG.

【0011】図2(a)に示すように、基板11,12
の両面に導電層13,14,15,16を形成する。同
図中、17はプリプレグ材である。
As shown in FIG. 2A, the substrates 11 and 12 are
Conductive layers 13, 14, 15 and 16 are formed on both surfaces of. In the figure, 17 is a prepreg material.

【0012】図2(b)に示すように、導電層13,1
4,15,16を所定のパターンにそれぞれエッチング
することにより表層パターン1,内層パターン2,内層
パターン3及び表層パターン4を形成する。
As shown in FIG. 2B, the conductive layers 13, 1
Surface layer pattern 1, inner layer pattern 2, inner layer pattern 3 and surface layer pattern 4 are formed by respectively etching 4, 15 and 16 into predetermined patterns.

【0013】図2(c)に示すように、表層パターン
1,基板11及び内層パターン2を貫通する貫通孔5
a,5bと、内層パターン3,基板12及び外層パター
ン4を貫通する貫通孔5c,5dとを形成する。
As shown in FIG. 2C, a through hole 5 penetrating the surface layer pattern 1, the substrate 11 and the inner layer pattern 2.
a, 5b and through holes 5c, 5d penetrating the inner layer pattern 3, the substrate 12 and the outer layer pattern 4 are formed.

【0014】図2(d)に示すように、貫通孔5a,5
b及び貫通孔5c,5dに印刷によりそれぞれ導電性ペ
ースト7a,7b及び導電性ペースト7c,7dを充填
する。このとき、本実施例では全ての貫通孔5a〜5d
に導電性ペースト7a〜7dを充填したが、この充填は
貫通孔5a〜5dを適宜選択して行なうこともできる。
As shown in FIG. 2D, the through holes 5a, 5
b and the through holes 5c and 5d are filled with the conductive pastes 7a and 7b and the conductive pastes 7c and 7d by printing. At this time, in this embodiment, all the through holes 5a to 5d are formed.
Although the conductive pastes 7a to 7d were filled in, the filling can be performed by appropriately selecting the through holes 5a to 5d.

【0015】図2(e)に示すように、プリプレグ材1
7を中央に挾んで基板11,12を積層して四層多層配
線基板を形成する。
As shown in FIG. 2 (e), the prepreg material 1
By sandwiching 7 in the center, the substrates 11 and 12 are laminated to form a four-layer multilayer wiring substrate.

【0016】図2(f)に示すように、表層パターン
1,基板11,内層パターン2,プリプレグ材17,内
層パターン3,基板12及び表層パターン4を貫通する
貫通孔6a,6bを形成する。
As shown in FIG. 2 (f), through holes 6a, 6b penetrating the surface layer pattern 1, the substrate 11, the inner layer pattern 2, the prepreg material 17, the inner layer pattern 3, the substrate 12 and the surface layer pattern 4 are formed.

【0017】図2(g)に示すように、貫通孔6aに印
刷により導電性ペースト8aを選択的に充填し、貫通孔
6bはそのままにしておく。
As shown in FIG. 2 (g), the through holes 6a are selectively filled with the conductive paste 8a by printing, and the through holes 6b are left as they are.

【0018】図2(h)に示すように、表層パターン
1,4から突出している導電性ペースト7a〜7d及び
8aを研摩して表層パターン1,4と面一になるように
加工する。すなわち、図3(a)に拡大して示すよう
に、図2(g)の工程では突出している導電性ペースト
7a〜7d及び8aを、図3(b)に拡大して示すよう
に、図2(h)の工程で面一に研摩する。これは、導電
性ペースト7a〜7d及び8a上に電子部品をハンダ付
けしたり、ランドを形成する場合の便宜に供するためで
ある。この場合、図3(c)に拡大して示すように、貫
通孔5a〜5d及び6aよりも大きめに印刷し、図2
(g)の工程では貫通孔5a〜5d及び6aの両端から
さらに表面に突出している導電ペースト7a〜7d及び
8aを図3(d)に拡大して示すように、図2(h)の
工程で面一に研磨しても良い。
As shown in FIG. 2 (h), the conductive pastes 7a to 7d and 8a protruding from the surface layer patterns 1 and 4 are polished and processed so as to be flush with the surface layer patterns 1 and 4. That is, as shown in the enlarged view of FIG. 3A, the conductive pastes 7a to 7d and 8a protruding in the step of FIG. 2G are shown in the enlarged view of FIG. 3B. Grind flush in the step 2 (h). This is for the convenience of soldering an electronic component or forming a land on the conductive pastes 7a to 7d and 8a. In this case, as shown in an enlarged view in FIG. 3 (c), printing is performed in a size larger than the through holes 5a to 5d and 6a.
In the step (g), the conductive pastes 7a to 7d and 8a further protruding from the both ends of the through holes 5a to 5d and 6a on the surface are enlarged as shown in FIG. It may be ground flush with.

【0019】最終的には導電性ペースト7a〜7d及び
8aを熱により硬化させる。かくして表層パターン1と
内層パターン2、表層パターン4と内層パターン3及び
表層パターン1,4同志は導電性ペースト7a〜7d及
び8aにより導通される。なお、図2(e)に示す積層
工程で黒化処理をした場合には表層パターン1,4の黒
化剥離を行なう。この黒化処理とはプリプレグ材17と
の接着性を良くするために表面を乱す処理である。
Finally, the conductive pastes 7a to 7d and 8a are hardened by heat. Thus, the surface layer pattern 1 and the inner layer pattern 2, the surface layer pattern 4, the inner layer pattern 3 and the surface layer patterns 1 and 4 are conducted by the conductive pastes 7a to 7d and 8a. When the blackening treatment is performed in the laminating step shown in FIG. 2E, the surface layer patterns 1 and 4 are blackened and peeled. The blackening treatment is a treatment for disturbing the surface in order to improve the adhesiveness with the prepreg material 17.

【0020】[0020]

【発明の効果】以上実施例とともに具体的に説明したよ
うに、本発明によればメッキ処理工程を除去することが
でき、印刷工程のみで各層間の導通をとることができる
ので、生産設備が簡単になり、コストの低廉化も達成し
得る。
As described above in detail with reference to the embodiments, according to the present invention, the plating process can be eliminated, and the conduction between layers can be established only by the printing process. It can be simplified and the cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】上記実施例の作製時の各工程の態様を示す断面
図である。
FIG. 2 is a cross-sectional view showing an aspect of each step in manufacturing the above-mentioned embodiment.

【図3】図2(g),(h)の一部を拡大して示す拡大
断面図である。
FIG. 3 is an enlarged sectional view showing an enlarged part of FIGS. 2 (g) and 2 (h).

【符号の説明】[Explanation of symbols]

1,4 表層パターン 2,3 内層パターン 5a,5b,5c,5d,6a,6b 貫通孔 7a,7b,7c,7d,8a 導電性ペースト 1,4 Surface layer pattern 2,3 Inner layer pattern 5a, 5b, 5c, 5d, 6a, 6b Through hole 7a, 7b, 7c, 7d, 8a Conductive paste

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 三層以上のパターンを形成した多層配線
基板において、表層パターンと内層パターン及び表層パ
ターン同志の導通を確保するための貫通孔に印刷により
導電性ペーストを充填したことを特徴とする多層配線基
板。
1. A multilayer wiring board having a pattern of three or more layers, wherein a through hole for ensuring continuity between the surface layer pattern, the inner layer pattern and the surface layer pattern is filled with a conductive paste by printing. Multilayer wiring board.
JP13037993A 1993-06-01 1993-06-01 Multilayer circuit board Pending JPH06342983A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13037993A JPH06342983A (en) 1993-06-01 1993-06-01 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13037993A JPH06342983A (en) 1993-06-01 1993-06-01 Multilayer circuit board

Publications (1)

Publication Number Publication Date
JPH06342983A true JPH06342983A (en) 1994-12-13

Family

ID=15032938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13037993A Pending JPH06342983A (en) 1993-06-01 1993-06-01 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPH06342983A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011228727A (en) * 2011-06-10 2011-11-10 Kyocera Corp Wiring board, electronic equipment with the wiring board, and probe card

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011228727A (en) * 2011-06-10 2011-11-10 Kyocera Corp Wiring board, electronic equipment with the wiring board, and probe card

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Effective date: 20000606