JPH02237142A - Manufacture of board for semiconductor mounting use - Google Patents
Manufacture of board for semiconductor mounting useInfo
- Publication number
- JPH02237142A JPH02237142A JP1056294A JP5629489A JPH02237142A JP H02237142 A JPH02237142 A JP H02237142A JP 1056294 A JP1056294 A JP 1056294A JP 5629489 A JP5629489 A JP 5629489A JP H02237142 A JPH02237142 A JP H02237142A
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- layer
- board
- conductor
- copper foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910000679 solder Inorganic materials 0.000 claims abstract description 7
- 239000000853 adhesive Substances 0.000 claims abstract description 5
- 230000001070 adhesive effect Effects 0.000 claims abstract description 5
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 239000011889 copper foil Substances 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は、半導体搭載用基板の製造方法に関し、より詳
し《は、より高密度化が可能なＰＰＧＡ（Ｐｌａｓｔｉ
ｃ Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）用基板の製造方法
に関するものである．
〔従来の技術〕
半導体搭載用基板の製造方法は、その構造によって種々
の方法が採用されているが、近年半導体技術の進展に伴
い、従来の構造に基づく座グリ部を有する両面回路基板
がその主流を占めている．一つは、通常の両面スルーホ
ール回路基板を作成した後、半導体搭載部分を座ぐる方
法であり、他の一つは、両面銅張積層板を用いてスルー
ホール穴をあけ、座ぐり加工をした後、パネルメッキを
経て半田メッキ等によって回路バクーンを形成し、さら
に、逆パターンのレジスト印刷をした後メッキを行なう
方法である．後者の方法は座ぐり部分にもメッキを形成
するものであり、前者の方法と比較して、半導体の特性
保持・信頬性のより優れた構造と考えられている．
しかし、２００ビン、３００ピンを超える多ピン化が進
むに伴って、半導体の構造の制約から従来の２層（両面
）構造では対応しきれず、回路を３層構造にして、ポン
ディングパッド部を２段構造とした基仮に対する要求が
高まってきており、しかも信顛性に対する要求も年々そ
の厳しさを増してきている．例えば、２Ｎ構造で２００
ピン程度のピングリッドアレーであれば、信号線パター
ンは半導体搭載面と同じ側に配線されており、ピン間に
５〜ＩＯ本の信号線パターンが通り、線巾／ｖＡ間は０
．１２／０．１２ｍｍ程廣であるが、同じ２層構造で３
００ビン以上になると、ビン間に７〜１４本以上の信号
線を通ずことが必要となり、線巾／線間は０．０８ ／
０．０８ｍｍ程度になるため、回路加工時における回路
パターンの断線・ショート等の不良が発生しやすく、ま
た、回路の細り等による配線抵抗の増加、信頼性の低下
等の問題があった．〔発明が解決しようとする課題〕
本発明は、多ビン化の進展に伴ない、高密度化さ高信顛
性が要求される半導体搭載用基板に関するものであり、
これらの要求に応えるため基板の配線を３層構造にし、
信号線を２Ｎにわたって配線することにより回路の細り
ゃ断線、ショート等信顧性に関係する諸問題を解決した
半導体搭載用基板を提供することを目的としたものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a substrate for mounting a semiconductor, and more particularly, to a method for manufacturing a substrate for mounting a semiconductor.
The present invention relates to a method for manufacturing a substrate for (c) Pin Grid Array. [Prior art] Various methods are used to manufacture semiconductor mounting boards depending on their structure, but in recent years, with the advancement of semiconductor technology, double-sided circuit boards with counterbore parts based on the conventional structure have become popular. It occupies the mainstream. One method is to create a normal double-sided through-hole circuit board and then counterbore the semiconductor mounting part.The other method is to use a double-sided copper-clad laminate to drill through-holes and perform counterbore processing. After that, a circuit board is formed by panel plating, solder plating, etc., and then a reverse pattern of resist is printed, followed by plating. The latter method also forms plating on the counterbore area, and is considered to have a structure that maintains the characteristics of the semiconductor and is more reliable than the former method. However, as the number of pins exceeds 200 bins and 300 pins, the conventional two-layer (double-sided) structure cannot be used due to the limitations of the semiconductor structure, so the circuit is changed to a three-layer structure, and the bonding pad part is There is an increasing demand for two-tiered bases, and the demands on reliability are also becoming stricter year by year. For example, in a 2N structure, 200
In the case of a pin-sized pin grid array, the signal line pattern is routed on the same side as the semiconductor mounting surface, 5 to IO signal line patterns pass between the pins, and the line width/vA is 0.
．． 12/It is about 0.12mm wider, but with the same two-layer structure, 3
00 bins or more, it is necessary to run 7 to 14 or more signal lines between the bins, and the line width/line spacing is 0.08/
Since the thickness is approximately 0.08 mm, defects such as disconnections and short circuits in circuit patterns are likely to occur during circuit processing, and there are also problems such as increased wiring resistance and decreased reliability due to thinning of the circuit. [Problems to be Solved by the Invention] The present invention relates to a semiconductor mounting board that is required to have high density and high reliability as the number of bins increases.
In order to meet these demands, the wiring of the board has a three-layer structure,
The object of the present invention is to provide a semiconductor mounting board that solves various reliability-related problems such as thinning, disconnection, and short circuits by wiring signal lines over 2N.
即ち、本発明は、両面銅張積層板の上側の面（第２の導
体層）にサブトラクト法により回路パターンを形成し、
該第２の導体層の上に接着シートおよび銅箔面を上側に
した片面銅張８Ｉ層仮、もしくはプリブレグおよび銅箔
をこの順に載！し積層一体化する工程、
得られた基板の上側銅箔層（第１の導体層）より前記第
２の導体層と下側銅箔層（第３の導体層）との中間の部
位まで座ぐり加工して、半導体搭載部となる凹部を形成
すると共に、各導体層間を接続するためのスルーホール
を形成する工程、基板の全面にパネルメッキを施すと共
に、半田レジスト法により第１および第３の導体層に回
路パターンを形成する工程、
前記半導体搭載用凹部の周辺部を基板の上側面よりルー
ター加工して、半導体のボンディングバッド部となる第
２の導体層を露出させる工程、および、
基板の上下両面にレジスト印刷をすると共に、露出して
いる導体層にニッケル・金メッキを施す工程
から成ることを特徴とする３層構造の半導体搭載用基板
の製造方法である．
以下、図面により本発明を詳細に説明する．第１図は、
本発明による半導体搭載用基板の−実施例を示す断面図
で、第２図は、本発明による半導体搭載用基板の製造工
程を示す図である．先ず、両面銅張積層板を用いて、第
２図（ａ）に示したように、その上側面の銅箔、即ち本
発明による半導体搭載用基板（１）の第２の導体層（１
６）となる銅箔を、フォトエッチング等のサブトラクト
法によってパターン加工し、回路パターンを形成させる
。That is, the present invention forms a circuit pattern on the upper surface (second conductor layer) of a double-sided copper-clad laminate by a subtract method,
On top of the second conductor layer, place an adhesive sheet and a single-sided copper-clad 8I layer with the copper foil side facing up, or pre-reg and copper foil in this order! In the step of laminating and integrating, the upper copper foil layer (first conductor layer) of the obtained board is seated up to an intermediate portion between the second conductor layer and the lower copper foil layer (third conductor layer). A process of drilling to form a recess that will become a semiconductor mounting area and a through hole for connecting between each conductor layer. Panel plating is applied to the entire surface of the board, and the first and third layers are formed using a solder resist method. a step of forming a circuit pattern on the conductor layer of the substrate; a step of routering the peripheral portion of the semiconductor mounting recess from the upper surface of the substrate to expose a second conductor layer that will become a bonding pad portion of the semiconductor; This is a method for manufacturing a semiconductor mounting board with a three-layer structure, which comprises the steps of printing a resist on both the top and bottom surfaces of the board, and plating the exposed conductor layer with nickel and gold. The present invention will be explained in detail below with reference to the drawings. Figure 1 shows
FIG. 2 is a sectional view showing an embodiment of the semiconductor mounting board according to the present invention, and FIG. 2 is a diagram showing the manufacturing process of the semiconductor mounting board according to the present invention. First, as shown in FIG. 2(a), a double-sided copper-clad laminate is used, and as shown in FIG.
6) The copper foil is patterned by a subtract method such as photoetching to form a circuit pattern.
次いで、第２図（ｂ）のように、第２の導体層（ｌ６）
である回路パターンの上に接着シート（１４）を載せ、
さらに、片面銅張積層板（１３）を第１の導体層（１５
）となる銅箔面を上側にして載せ、必要に応じて加熱加
圧し、積層一体化する．ここで、接着シー１− （１４
）および片面銅張積層仮（１３）の代りに、プリブレグ
および銅箔を使用して積層一体化しても、同様に本発明
の目的を達することが出来る。Next, as shown in FIG. 2(b), the second conductor layer (l6)
Place the adhesive sheet (14) on top of the circuit pattern,
Furthermore, the single-sided copper-clad laminate (13) is coated with the first conductor layer (15).
) with the copper foil side facing up, and heat and press as necessary to integrate the layers. Here, adhesive sheet 1- (14
) and single-sided copper-clad laminated temporary (13), the object of the present invention can be similarly achieved even if pre-reg and copper foil are used for lamination and integration.
次に、第２図（ｃ）に示したように、積層一体化して得
られた３層構造の基板の中央部に、上側第１の導体層（
１５）より、第２の導体ｊＷ （１６）と下側第３の導
体層（１７）の間に位置する絶８ｉ層（１２）の中半ま
で座ぐり加工を行ない、半導体搭載部となる凹部（１８
）を形成させる。併せて、ビン（３）を挿入し各導体層
間を電気的に接続するためのスルーホール（ｌ９）を形
成する孔あけ加工を行なう。Next, as shown in FIG. 2(c), an upper first conductor layer (
15), counterboring is performed to the middle of the 8i layer (12) located between the second conductor jW (16) and the lower third conductor layer (17) to create a recess that will become the semiconductor mounting area. (18
) to form. At the same time, drilling is performed to form a through hole (19) for inserting a bottle (3) and for electrically connecting each conductor layer.
次に、スルーホール（１９）内部および基板全体に銅メ
ッキ（パネルメッキ）を施す．＃ｒ４メッキは、数μの
厚さに無電解銅メッキを施した後、所望の厚み、好まし
くは約１５〜２０μの厚みの電気銅メッキを施すもので
ある．続いて、３履構造の基板の上下両面の銅箔面に、
それぞれ所定の回路パターンとは逆のパターンのレジス
トを施し、露出している（レジストが付いていない）銅
箔面に半田メッキをし、レジストを剥離した後、露出し
た銅箔をエッチングして除去し、さらに、先にメッキ付
けした半田を剥離させる、謂る半田レジスト法により、
第１および第３の導体Ｉ’！ （１５） ．（１７）に
銅の回路パターンを形成させる．（第２図（ｄ））次に
、第２図（ｄ）のように凹部（１８）の周辺部（ｅ）に
示したように、基板の上側面よりルーター加工を行なう
ことによって露出させる．最後に、基板の上下両面にレ
ジスト印刷を施し、凹部（１８） 、半導体ボンディン
グパッド（２０）、およびスルーホール（１９）の露出
している導体層にニッケル・金メッキを施す．
３層構造の形成は、片面銅張積層仮を第ＩＮにし両面銅
張積層板を第２Ｎと第３層にする他、両面銅張積層板を
第ＩＮと第２Ｎにし、片面銅張積層板を第３層にして積
層してもよい．また、プリプレグと銅箔を使用する場合
も同様である．〔発明の効果〕
本発明により、従来の２Ｎ構造の回路基板では困難であ
った３００ピン以上の多ピンの半導体搭載用基板の製造
が可能になり、回路パターンの断線・細り等の問題もな
く、高信鎖性のある半導体搭載用基板を提供するものと
してきわめて有用であNext, copper plating (panel plating) is applied to the inside of the through hole (19) and the entire board. #r4 plating is performed by applying electroless copper plating to a thickness of several microns, and then applying electrolytic copper plating to a desired thickness, preferably about 15 to 20 microns. Next, on the copper foil surfaces on both the top and bottom of the three-socket structure board,
Apply a resist with a pattern opposite to the predetermined circuit pattern, apply solder plating to the exposed (no resist) copper foil surface, peel off the resist, and then remove the exposed copper foil by etching. Furthermore, by using the so-called solder resist method, which peels off the previously plated solder,
The first and third conductors I'! (15). (17) Form a copper circuit pattern. (FIG. 2(d)) Next, as shown in FIG. 2(d), the peripheral area (e) of the recess (18) is exposed by router processing from the upper surface of the substrate. Finally, resist printing is applied to both the upper and lower surfaces of the board, and nickel and gold plating is applied to the exposed conductor layers of the recesses (18), semiconductor bonding pads (20), and through holes (19). The three-layer structure is formed by using a single-sided copper-clad laminate as the IN layer, a double-sided copper-clad laminate as the 2N and 3rd layers, and a double-sided copper-clad laminate as the IN and 2N layers. It may also be laminated as the third layer. The same applies when using prepreg and copper foil. [Effects of the Invention] The present invention makes it possible to manufacture semiconductor mounting boards with more than 300 pins, which was difficult with conventional 2N structure circuit boards, and eliminates problems such as disconnection and thinning of circuit patterns. It is extremely useful as a substrate for mounting semiconductors with high reliability.
第１図は、本発明による半導体搭載用基板の概念を示す
断面図で、第２図は、本発明の半導体搭載用基板の製造
工程の一実施例を示す図である．第１図FIG. 1 is a sectional view showing the concept of a semiconductor mounting substrate according to the present invention, and FIG. 2 is a diagram showing an embodiment of the manufacturing process of the semiconductor mounting substrate according to the present invention. Figure 1
Claims (1)
ブトラクト法により回路パターンを形成し、該第２の導
体層の上に接着シートおよび銅箔面を上側にした片面銅
張積層板、もしくはプリプレグおよび銅箔をこの順に載
置し積層一体化する工程、得られた基板の上側銅箔層（
第１の導体層）より前記第２の導体層と下側銅箔層（第
３の導体層）との中間の部位まで座ぐり加工して、半導
体搭載部となる凹部を形成すると共に、各導体層間を接
続するためのスルーホールを形成する工程、基板の全面
にパネルメッキを施すと共に、半田レジスト法により第
１および第３の導体層に回路パターンを形成する工程、 前記半導体搭載用凹部の周辺部を基板の上側面よりルー
ター加工して、半導体のボンディングパット部となる第
２の導体層を露出させる工程、および、 基板の上下両面にレジスト印刷をすると共に、露出して
いる導体層にニッケル・金メッキを施す工程 から成ることを特徴とする３層構造の半導体搭載用基板
の製造方法。(1) A circuit pattern is formed on the upper surface (second conductor layer) of a double-sided copper-clad laminate by the subtract method, and an adhesive sheet and a single-sided copper layer with the copper foil side facing upward are formed on the second conductor layer. The process of laminating and integrating a stretched laminate or prepreg and copper foil in this order, and the upper copper foil layer (
A counterbore is formed from the first conductor layer to an intermediate portion between the second conductor layer and the lower copper foil layer (third conductor layer) to form a concave portion that will become the semiconductor mounting portion. a step of forming a through hole for connecting conductor layers; a step of panel plating the entire surface of the board and forming a circuit pattern on the first and third conductor layers by a solder resist method; A process of routering the peripheral part from the upper side of the substrate to expose the second conductor layer that will become the bonding pad part of the semiconductor, and printing resist on both the top and bottom surfaces of the substrate, as well as coating the exposed conductor layer. A method for manufacturing a semiconductor mounting board having a three-layer structure, characterized by comprising a process of applying nickel and gold plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1056294A JPH02237142A (en) | 1989-03-10 | 1989-03-10 | Manufacture of board for semiconductor mounting use |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1056294A JPH02237142A (en) | 1989-03-10 | 1989-03-10 | Manufacture of board for semiconductor mounting use |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02237142A true JPH02237142A (en) | 1990-09-19 |
Family
ID=13023092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1056294A Pending JPH02237142A (en) | 1989-03-10 | 1989-03-10 | Manufacture of board for semiconductor mounting use |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02237142A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216539A (en) * | 1993-01-14 | 1994-08-05 | Matsushita Electric Works Ltd | Printed wiring board nad semiconductor device |
| US5542175A (en) * | 1994-12-20 | 1996-08-06 | International Business Machines Corporation | Method of laminating and circuitizing substrates having openings therein |
| US5566448A (en) * | 1995-06-06 | 1996-10-22 | International Business Machines Corporation | Method of construction for multi-tiered cavities used in laminate carriers |
| JP2006041521A (en) * | 2004-07-23 | 2006-02-09 | Samsung Electronics Co Ltd | Printed circuit board and display utilizing same |
| JP2010135742A (en) * | 2008-10-28 | 2010-06-17 | Hitachi Chem Co Ltd | Three-layered wiring substrate, and method of manufacturing the same |
-
1989
- 1989-03-10 JP JP1056294A patent/JPH02237142A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216539A (en) * | 1993-01-14 | 1994-08-05 | Matsushita Electric Works Ltd | Printed wiring board nad semiconductor device |
| US5542175A (en) * | 1994-12-20 | 1996-08-06 | International Business Machines Corporation | Method of laminating and circuitizing substrates having openings therein |
| US5578796A (en) * | 1994-12-20 | 1996-11-26 | International Business Machines Corporation | Apparatus for laminating and circuitizing substrates having openings therein |
| US5566448A (en) * | 1995-06-06 | 1996-10-22 | International Business Machines Corporation | Method of construction for multi-tiered cavities used in laminate carriers |
| JP2006041521A (en) * | 2004-07-23 | 2006-02-09 | Samsung Electronics Co Ltd | Printed circuit board and display utilizing same |
| US8144300B2 (en) | 2004-07-23 | 2012-03-27 | Samsung Electronics Co., Ltd. | Printed circuit board and display device using the same |
| JP2010135742A (en) * | 2008-10-28 | 2010-06-17 | Hitachi Chem Co Ltd | Three-layered wiring substrate, and method of manufacturing the same |
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