JPH02271653A - Manufacture of substrate for mounting semiconductor - Google Patents
Manufacture of substrate for mounting semiconductorInfo
- Publication number
- JPH02271653A JPH02271653A JP1091911A JP9191189A JPH02271653A JP H02271653 A JPH02271653 A JP H02271653A JP 1091911 A JP1091911 A JP 1091911A JP 9191189 A JP9191189 A JP 9191189A JP H02271653 A JPH02271653 A JP H02271653A
- Authority
- JP
- Japan
- Prior art keywords
- board
- substrate
- plating
- sided copper
- clad laminate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 title abstract description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000007747 plating Methods 0.000 claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052737 gold Inorganic materials 0.000 claims abstract description 13
- 239000010931 gold Substances 0.000 claims abstract description 13
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 14
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 239000011889 copper foil Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 11
- 239000010949 copper Substances 0.000 abstract description 11
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体搭載用基板の製造方法に関し、より詳し
くは、より高密度化が可能なＰＰＧＡ（Ｐｌａｓｔｉｃ
Ｐｉｎ Ｇｒｉｄ Ａｒｒｒａｙ）用基板の製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a substrate for mounting a semiconductor, and more specifically, the present invention relates to a method of manufacturing a substrate for mounting a semiconductor, and more particularly, it relates to a method of manufacturing a substrate for mounting a semiconductor, and more specifically, it relates to a method of manufacturing a substrate for mounting a semiconductor.
The present invention relates to a method of manufacturing a substrate for a pin grid array.
半導体搭載用基板の製造方法は、その構造によって種々
の方法が採用されているが、近年半導体技術の進展に伴
い、薄型高密度を十分満足させる構造である、座グリ部
を有する両面回路基板がその主流を占めている。一つは
、通常の両面スルーホール回路基板を作成した後、半導
体搭載部分を座ぐる方法であり、他の一つは、両面銅張
積層板を用いてスルーホール穴あけ・座ぐり加工をした
後、パネルメッキを経て半田メッキ等によって回路を形
成し、さらにレジストを印刷した後メッキを行なう方法
である。後者の方法は座ぐり部分にもメッキを形成する
ものであり、前者の方法と比較して、耐湿性、耐熱衝撃
性等、半導体の特性保持・信組性のより優れた構造と考
えられている。Various methods are used to manufacture semiconductor mounting boards depending on their structure, but in recent years, with the advancement of semiconductor technology, double-sided circuit boards with counterbore parts, which have a structure that fully satisfies thinness and high density, have been developed. It occupies the mainstream. One method is to create a normal double-sided through-hole circuit board and then spot-bore the semiconductor mounting part.The other method is to drill and counter-bore the through-holes using a double-sided copper-clad laminate. In this method, a circuit is formed by panel plating, solder plating, etc., and then plating is performed after printing a resist. The latter method also forms plating on the counterbore area, and is considered to have a structure that retains semiconductor properties such as moisture resistance and thermal shock resistance and is more reliable than the former method. .
の２層（両面）構造では対応しきれず、回路を３層構造
、さらにはそれ以上の多層構造にして、ポンディングパ
ッド部を２段構造さらには多段構造とした基板に対する
要求が高まってきており、しかも信組性に対する要求も
年々その厳しさを増してきている０例えば、２層構造で
２００ピン程度のピングリッドアレーであれば、信号線
パターンは半導体搭載面と同じ側に配線されており、ビ
ン間に５〜１０本の信号線パターンが通り、線巾／線間
は０．１２１０．１２ｍｍ程度であるが、同じ２層構造
で３００ピン以上になると、ピン間に７〜１４本以上の
信号線パターンを通すことが必要となり、線巾／線間は
０．０８１０．０８ｍ程度になるため、回路加工時にお
ける回路の断線、シッート等の不良が発生しやすく、ま
た、回路の細り等による配線抵抗の増加、耐湿耐衝撃の
信組性の低下等の問題があった。The two-layer (both-sided) structure cannot meet the requirements, and there is an increasing demand for circuit boards with three-layer or even more multi-layer structures, and with two-layer or even multi-layer bonding pad structures. Moreover, the requirements for reliability are becoming stricter year by year.For example, in a pin grid array with a two-layer structure and about 200 pins, the signal line pattern is routed on the same side as the semiconductor mounting surface. 5 to 10 signal line patterns pass between the bins, and the line width/line distance is about 0.1210.12 mm, but if the same two-layer structure has more than 300 pins, there will be 7 to 14 or more signal lines between the pins. It is necessary to pass the signal line pattern, and the line width/line spacing is approximately 0.0810.08 m, so defects such as circuit breakage and sheeting are likely to occur during circuit processing, and due to thinning of the circuit, etc. There were problems such as an increase in wiring resistance and a decrease in moisture and shock resistance.
本発明は、多ピン化の進展に伴い、高密度化と高信幀性
が要求される半導体耐搭載用基板に関するものであり、
これらの要求に応えるための基板の配線を多層構造にし
、信号線を２層以上にわたって配線することにより回路
の細りゃ断線、シジート等信鯨性に関係する諸問題を解
決した半導体搭載用基板を提供することを目的としたも
のである。The present invention relates to a semiconductor mounting board that is required to have high density and high reliability as the number of pins increases.
In order to meet these demands, we have developed a multi-layer wiring structure for the board, and by wiring signal lines over two or more layers, we have created a semiconductor mounting board that solves problems related to thin circuits, disconnections, wire breaks, etc. It is intended to provide.
即ち本発明は、所望の位置にデバイスホールを形成した
片面銅張積層板と、他の片面銅張積層板とを互いに銅箔
面が外側になるように接着シートにて積層一体化した基
板、もしくは両面銅張積層板の所望の位置に座ぐり加工
して半導体搭載部となる凹部を形成した基板に、全面パ
ネルメッキを施し、凹部が形成された側の面に通常のサ
ブトラクト法により所望の回路形成し、所定の部分にソ
ルダーレジストを形成した後、露出している導体部分に
ニッケル・金メッキを施す第１の工程、第１の工程で得
られた基板の回路形成面上に、前記基板の凹部より大き
いデバイスホールおよび所望の位置に所望の回路を形成
し、所定の部分にソルダーレジストを形成後、露出して
いる導体部分にニッケル・金メッキを施した１枚もしく
は複数枚の片面銅張積Ｎ板を、接着シートを介して順次
積層し、次いで、最外層にデバイスホールのみを形成し
た片面銅張積層板を積層一体化する第２の工程、第２の
工程で得られた基板の所望の位置に各導体層間を接続す
るためのスルーホールを形成し、基板全体にパネルメッ
キを施し、基板の最外層両面にサブトラクト法にて回路
を形成する第３の工程、および、該基板の最外層両面に
ソルダーレジストを印刷した後、露出している導体部分
にニッケル・金メッキを施す第４の工程からなることを
特徴とする多層構造の半導体搭載用基板の製造方法であ
る。That is, the present invention provides a substrate in which a single-sided copper-clad laminate with device holes formed at desired positions and another single-sided copper-clad laminate are laminated together with an adhesive sheet so that the copper foil side faces outward; Alternatively, a double-sided copper-clad laminate is counterboiled at the desired position to form a recess that will serve as a semiconductor mounting area, then full panel plating is applied to the board, and the surface on which the recess is formed is plated with the desired shape using a normal subtract method. After forming a circuit and forming a solder resist on a predetermined portion, the exposed conductor portion is plated with nickel and gold. After forming a device hole larger than the concave part and the desired circuit at the desired position, and forming a solder resist in the designated area, one or more single-sided copper-clad sheets with nickel and gold plating applied to the exposed conductor parts are formed. The second step is to sequentially laminate the N-laminated boards via adhesive sheets, and then to integrate the single-sided copper-clad laminate with only device holes formed in the outermost layer. A third step is to form through holes to connect the conductor layers at desired positions, apply panel plating to the entire board, and form circuits on both sides of the outermost layer of the board by the subtract method; This is a method for manufacturing a semiconductor mounting board having a multilayer structure, which comprises a fourth step of printing solder resist on both sides of the outermost layer and then plating exposed conductor parts with nickel and gold.
以下、図面により本発明の詳細な説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は本発明による半導体搭載用基板の一実施例を示
す断面図で、第２図は本発明による半導体搭載用基板の
製造工程を示す図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor mounting substrate according to the present invention, and FIG. 2 is a diagram showing a manufacturing process of the semiconductor mounting substrate according to the present invention.
先ず、第２図（ａ）に示したように、片面銅張積層板（
１１）の上に接着シー） （１２）を載せ、所望の位置
に所望の大きさでルータ−加工、金型打抜、パンチング
等でデバイスホール（１４）を形成した片面銅張積層板
（１３）を載せ、銅箔面が互いに外側になるようにし、
必要に応じて加熱、加圧し積層一体化して、第２図（ｂ
）のように半導体搭載用の凹部（１５）を形成する。こ
こで、両面銅積層層板を用いて、所望の位置に所望の大
きさの座ぐり加工を行なって、同様に半導体搭載用の凹
部（１５）を形成する方法も可能である。続いて、前記
により凹部（１５）を形成した基板全体に銅パネルメッ
キを施す、ｗ４パネルメッキは、無電解銅メッキを施し
た後、所望の厚さ、好ましくは約１５〜２０μｍの厚み
の電解銅メッキを施すものである。さらに、基板の凹部
（１５）を形成した側の面の導体層（１８）に所望の回
路パターンとは逆のパターンレジストを施し、露出して
いる（レジストの付いていない）銅箔部分に半田メッキ
を施し、レジストを剥離した後、露出した銅箔をエツチ
ング加工して除去し、さらに先にメッキした半田を剥離
させる、謂る半田レジスト法により回路加工を行ない導
体層（１８）に回路パターン（１６）を形成させる。続
いて、得られた基板の導体層（１日）側にソルダーレジ
スト（１７）を施して、半導体搭載用の凹部（１５）
、ポンディングパッド部（１９）のレジストの付いてい
ない露出している導体部分に、ニッケル・金メッキを施
す。First, as shown in Fig. 2(a), a single-sided copper-clad laminate (
Place adhesive sheet (12) on top of 11), and form a single-sided copper-clad laminate (13) with a device hole (14) in a desired size at a desired position by router processing, die cutting, punching, etc. ), and place the copper foil sides on the outside of each other.
If necessary, heat and pressurize to integrate the layers to form the structure shown in Figure 2 (b).
) A recess (15) for mounting the semiconductor is formed. Here, it is also possible to similarly form a recess (15) for mounting a semiconductor by using a double-sided copper laminate plate and performing counterbore processing of a desired size at a desired position. Next, copper panel plating is applied to the entire board in which the recesses (15) have been formed as described above.W4 panel plating is performed by applying electroless copper plating to a desired thickness, preferably about 15 to 20 μm. Copper plating is applied. Furthermore, a pattern resist opposite to the desired circuit pattern is applied to the conductor layer (18) on the side where the recess (15) is formed, and solder is applied to the exposed (no resist) copper foil portion. After plating is applied and the resist is peeled off, the exposed copper foil is etched and removed, and the plated solder is removed first. Circuit processing is performed using the so-called solder resist method to form a circuit pattern on the conductor layer (18). (16) is formed. Next, a solder resist (17) is applied to the conductor layer (1st) side of the obtained board to form a recess (15) for mounting a semiconductor.
, Nickel/gold plating is applied to the exposed conductor portion of the bonding pad portion (19) that is not coated with resist.
次に、第２図（ｃ）に示したように、前記第１の工程に
て得られた基板の導体層（１日）の上に、接着シート（
１２’）を介して片面銅張積層板（１１’）を積層する
０片面銅積層層板（１１’）は、直接積層される下側の
基板の凹部（１５）の周囲にあるボンディングパット部
（１９）が露出できる大きさのデバイスホール（１４’
）を持ち、かつ導体層（１８’）に所望の回路パターン
（１６’）をフォトエツチング等のサブトラクト法で回
路形成を行ない、前記第１の工程と同様にしてソルダー
レジスト（１７°）を施した後、露出している導体部分
であるポンディングパッド部（１９°）に、ニッケル・
金メッキを施したものである。このような接着シート（
１２′）と片面銅張積層板（１１′）の組合せを、必要
に応じて１組もしくは複数組積層するが、２組以上用い
る場合は、上側に積層する銅張積層板には、下側に積層
される銅張積層板のデバイスホールより大きいデバイス
ホールを設けて、下側の導体層のボンディングバット部
がそれぞれ露出できるようにする。Next, as shown in FIG. 2(c), an adhesive sheet (
The single-sided copper laminate laminate (11') is laminated with the single-sided copper clad laminate (11') via the bonding pad part around the recess (15) of the lower board to be directly laminated. (19) is large enough to expose the device hole (14'
), and a desired circuit pattern (16') is formed on the conductor layer (18') by a subtracting method such as photoetching, and a solder resist (17°) is applied in the same manner as in the first step. After that, apply nickel to the exposed conductor part (19°) of the bonding pad.
It is gold plated. Adhesive sheet like this (
12') and single-sided copper-clad laminates (11') are laminated as needed. However, when using two or more sets, the copper-clad laminates laminated on the upper side must be laminated on the lower side. A device hole larger than that of the copper-clad laminate to be laminated is provided so that the bonding butt portions of the lower conductor layer can be exposed.
さらに、片面Ｗ４張積層板（１１°）の導体層（１８°
）の上に、最外層となるデバイスホールのみを形成した
片面銅張積層板（１１”）を、接着シー） （１２”）
を介して載置し、必要に応じて加熱、加圧して全体を積
層一体化する。このようにして、４層以上の導体層を有
する基板が得られる。Furthermore, a conductor layer (18°) of a single-sided W4 clad laminate (11°)
) on which a single-sided copper-clad laminate (11") with only the device holes formed as the outermost layer is glued onto the adhesive sheet (12")
The whole is laminated and integrated by heating and pressurizing as necessary. In this way, a substrate having four or more conductor layers is obtained.
次に、第２図（ｄ）に示したように、前記第２の工程で
得られた基板の所望の箇所に、ピン（３）を挿入し各導
体層間を電気的に接続するためのスルーホール（２０）
を形成する孔あけ加工を行なう。Next, as shown in FIG. 2(d), pins (3) are inserted into desired locations on the substrate obtained in the second step to form through holes for electrically connecting each conductor layer. Hall (20)
Drilling is performed to form a hole.
続いて、スルーホール（２０）の内部および基板全体に
銅パネルメッキを施す。銅メッキは、無電解銅メッキを
施した後、所望の厚み、好ましくは約１５〜２０μｍの
厚みの電気銅メッキを施すものである。Subsequently, copper panel plating is applied to the inside of the through hole (20) and the entire board. Copper plating is performed by applying electroless copper plating and then applying electrolytic copper plating to a desired thickness, preferably about 15 to 20 μm.
続いて、得られた基板の最外層となる上下両面の導体層
（１８”、１８”’）にフォトエツチング等のサブトラ
クト法によって回路を加工し、所望の回路パターンを形
成させる。Subsequently, circuits are processed on the upper and lower conductive layers (18'', 18'''), which are the outermost layers of the obtained substrate, by a subtracting method such as photoetching to form a desired circuit pattern.
最後に、基板の上下両面の導体層（１８”、１８”’）
に、ソルダーレジスト（１７″）を施し、凹部（１５）
、半導体ポンディングパッド部（１９，１９’ 、１９
”）、およびスルーホール部分（２０）の露出している
導体部分にニッケル・金メッキを施す。このとき、各片
面銅張積層板のデバイスホールの内周面に相当する垂直
部分（２１）は、ニッケル・金メッキを施されることな
く露出状態で残される。Finally, conductor layers (18", 18"') on both the top and bottom of the board.
Apply solder resist (17″) to the recess (15).
, semiconductor bonding pad section (19, 19', 19
”) and the exposed conductor portions of the through-hole portions (20) are plated with nickel and gold.At this time, the vertical portions (21) corresponding to the inner peripheral surfaces of the device holes of each single-sided copper-clad laminate are plated with nickel and gold. It is left exposed without being plated with nickel or gold.
本発明により、従来の２層構造の回路基板では困難であ
った３００ピン以上の多ピン半導体搭載用基板の製造が
可能になり、回路パターンを２層以上にわたって引き廻
す事により生ずる断線・細り等の問題もなく、さらには
、半導体搭載部分のに優れた構造であり、また、各導体
層間の垂直部分（２１）で、半導体と基板のポンディン
グパッド部を接続しているボンディングワイヤーが凹部
のエツジに接触してショート等の不良を発生することの
ない構造である、高信頼性のある半導体搭載用基板を提
供するものとしてきわめて有用である。The present invention makes it possible to manufacture multi-pin semiconductor mounting boards with 300 pins or more, which was difficult with conventional two-layer circuit boards. There were no problems, and furthermore, the structure of the semiconductor mounting part was excellent, and the bonding wire connecting the semiconductor and the bonding pad part of the board in the vertical part (21) between each conductor layer was inserted into the recess. It is extremely useful for providing a highly reliable semiconductor mounting substrate that has a structure that does not cause defects such as short circuits due to contact with edges.
第１図は本発明による半導体搭載用基板の概念を示す断
面図で、第２図は本発明の半導体搭載用基板の製造工程
の一実施例を示す図である。FIG. 1 is a sectional view showing the concept of a semiconductor mounting substrate according to the present invention, and FIG. 2 is a diagram showing an embodiment of the manufacturing process of the semiconductor mounting substrate according to the present invention.
Claims (1)
の片面銅張積層板とを互いに銅箔面が外側になるように
接着シートにて積層一体化した基板、もしくは両面銅張
積層板に座ぐり加工して半導体搭載部となる凹部を形成
した基板に、全面パネルメッキを施し、凹部が形成され
た側の面にサブトラクト法により回路を形成し、ソルダ
ーレジストを形成した後、露出している導体部分にニッ
ケル・金メッキを施す第１の工程、 前記基板の凹部より大きいデバイスホールおよび回路を
形成し、ソルダーレジストを形成し、露出している導体
部分にニッケル・金メッキを施した１枚もしくは複数枚
の片面銅張積層板を、前記基板の回路形成面上に接着シ
ートを介して順次積層し、次いで、最外層にデバイスホ
ールのみを形成した片面銅張積層板を積層一体化する第
２の工程、 第２の工程で得られた基板の各導体層間を接続するため
のスルーホールを形成し、基板全体にパネルメッキを施
し、基板の最外層両面にサブトラクト法にて回路を形成
する第３の工程、および、基板の最外層両面にソルダー
レジストを印刷した後、露出している導体部分にニッケ
ル・金メッキを施す第４の工程 から成ることを特徴とする多層構造の半導体搭載用基板
の製造方法。(1) A board in which a single-sided copper-clad laminate with a device hole formed therein and another single-sided copper-clad laminate are laminated together using an adhesive sheet with the copper foil side facing outward, or a double-sided copper-clad laminate is used. A board on which a concave portion that will become the semiconductor mounting area is formed by counterbore processing is subjected to full panel plating, a circuit is formed on the side where the concave portion is formed by the subtract method, and a solder resist is formed. The first step is to apply nickel/gold plating to the exposed conductor parts, form device holes and circuits larger than the recesses of the board, form a solder resist, and apply nickel/gold plating to the exposed conductor parts. A second step in which a plurality of single-sided copper-clad laminates are sequentially laminated on the circuit forming surface of the board via an adhesive sheet, and then a single-sided copper-clad laminate having only device holes formed in the outermost layer is laminated and integrated. The second step is to form through holes to connect the conductor layers of the board obtained in the second step, apply panel plating to the entire board, and form circuits on both sides of the outermost layer of the board by the subtract method. 3, and a fourth step of printing solder resist on both sides of the outermost layer of the board, and then plating exposed conductor parts with nickel and gold. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1091911A JPH02271653A (en) | 1989-04-13 | 1989-04-13 | Manufacture of substrate for mounting semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1091911A JPH02271653A (en) | 1989-04-13 | 1989-04-13 | Manufacture of substrate for mounting semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02271653A true JPH02271653A (en) | 1990-11-06 |
Family
ID=14039765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1091911A Pending JPH02271653A (en) | 1989-04-13 | 1989-04-13 | Manufacture of substrate for mounting semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02271653A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216539A (en) * | 1993-01-14 | 1994-08-05 | Matsushita Electric Works Ltd | Printed wiring board nad semiconductor device |
| KR100285116B1 (en) * | 1997-02-12 | 2001-06-01 | 모기 쥰이찌 | Manufacturing method of semiconductor package |
-
1989
- 1989-04-13 JP JP1091911A patent/JPH02271653A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216539A (en) * | 1993-01-14 | 1994-08-05 | Matsushita Electric Works Ltd | Printed wiring board nad semiconductor device |
| KR100285116B1 (en) * | 1997-02-12 | 2001-06-01 | 모기 쥰이찌 | Manufacturing method of semiconductor package |
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