JPH06338911A - Data communication equipment - Google Patents

Abstract

PURPOSE:To provide a data communication equipment capable of efficiently distributing (copying) the same transmission data to plural channels. CONSTITUTION:The data communication equipment is provided with a data processing part 1, plural data transmission buffers 2 which are connected to the data processing part 1 in parallel and plural data communication means 3 which are respectively connected to the data transmission buffers 2. The equipment is provided with an interface means 4 interfacing the writing of transmission data into each data transmission buffer 2 from the data processing part 1 and the interface part 4 can write the same transmission data from the data processing part 1 into each data transmission buffer 2 at the same time. Preferably, the interface means 4 is constituted to be capable of switching a mode for writing the same transmission data from the data processing part 1 into each data transmission buffer 2 at the same time and a mode for individually writing individual transmission data from the data processing part 1 into each data transmission buffer 2 by the input of a mode signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device,
More specifically, the present invention relates to a data communication device including a data processing unit, a plurality of data transmission buffers connected in parallel to the data processing unit, and a plurality of data communication units respectively connected to the data transmission buffers. In recent years, with the increase in communication data, improvement in communication reliability is required. Therefore, there are systems that increase the reliability of communication by transmitting the same data using multiple channels, but for this purpose, it is necessary to efficiently distribute (copy) the data of a single information source to multiple channels. There is.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional data communication device.
In the figure, 1 is a CPU for processing communication data,
AB is the CPU address bus, CB is the control bus
DB, data bus, 2_A, 2_BTemporary communication data
Buffer memory (BUFM) that stores statically, 2_FiveIs FI
FO type write buffer (WB), 2₆Is also FIFO
Type read buffer (RB), 3_A, 3_BData communication
Knit (CU), 3₁Is a transmission buffer (T
B), 3₂Is a parallel-serial converter (PS), 3 ₃
Is a flag check that generates an error check signal for transmitted data
Sequence generator (FGC), 3_FourIs the driver (D),
Three_FiveIs the receiver (R), 3₆Is serial-parallel conversion
Bowl (SP), 3₇Is a receive buffer (RB) of several bytes,
Three₈Is a flag checker that checks the received data for errors.
Can inspection device (FCC), 3₉Is the data transmission / reception packet
Write / read buffer 2 while assembling / disassembling
_FiveTwo₆And a control unit (C
C), 3_TenIs its buffer interface (BIF),
5 is a RAM for the CPU 1 to process communication data, and 6 is a C
PU1 and buffer memory 2_A, 2_BMemory access between
Buffer interface (BI
F), 6_A, 6_BIs its buffer interface unit
(BIFU).

In this type of data communication apparatus, for example, the data communication units 3 _A and 3 _B are connected to another data communication apparatus (not shown), and a large number of channels CH-A and CH-B are provided. By transmitting the data, highly reliable data communication can be performed. Alternatively, the data communication units 3 _A and 3 _B are respectively connected to two different data communication devices (not shown), and the same large amount of data is transmitted to the channels CH-A and CH-B to perform broadcast communication. Is also possible.

In such a case, in the conventional case, first, BIFU6 _A
The transmission data TxD is written to the write buffer ₂₅ of the channel CH-A via the same, and then the same transmission data Tx is written to the write buffer ₂₅ of the channel CH-B via the BIFU 6 _B.
I was writing xD. That is, the CPU 1 first sets the address signal A = the address of the transmission data TxD of the RAM 5, the memory cycle signal MC = 1 (that is, the chip select signal CS = 1 of the RAM 5), and the read control signal RE = 1 to the transmission data of the RAM 5. TxD is temporarily stored in an internal register (not shown), then address signal A = device address of buffer memory 2 _A , memory cycle signal M
The transmission data TxD stored in the internal register when C = 0 (that is, the external buffer memory 2 is activated) and the write control signal WT = 1 is set to the write buffer 2 of the channel CH-A.
Write to ₅ . Thereafter, a series of transmission data Tx is similarly obtained.
D is written in the write buffer ₂₅ of the channel CH-A, while the written transmission data TxD is sequentially read by the data communication unit 3 _A , and the channel CH-
Sent via A.

Next, the CPU 1 causes the address signal A = RA.
RAM5 with the address of the transmission data TxD of M5, the memory cycle signal MC = 1, and the read control signal RE = 1
Of the transmission data TxD of the CPU 1 into the internal register of the CPU 1 again, and then the address signal A = the device address of the buffer memory 2 _B , the memory cycle signal MC = 0, and the write control signal WT = 1 are stored in the internal register. The data TxD is transferred to the write buffer 2 of the channel CH-B.
Write to ₅ . Thereafter, a series of transmission data Tx is similarly obtained
D is written to the write buffer 2 ₅ channels CH-B, whereas, the written transmitted data TxD is sequentially read out by the data communication unit 3 _B, the channel CH-
Sent via B.

[0006]

However, it is extremely inefficient to repeatedly transfer the same transmission data TxD to the buffer memories 2 _A and 2 _B for each channel as described above. Moreover, in recent years, this kind of transmission data TxD tends to become more and more huge, and the data transfer time from the CPU 1 to the buffer memories 2 _A and 2 _B cannot be ignored.

An object of the present invention is to provide a data communication device which can efficiently distribute (copy) the same transmission data to a plurality of channels.

[0008]

The above-mentioned problems can be solved by the structure shown in FIG. That is, the data communication device of the present invention is
A data processing unit comprising a data processing unit 1, a plurality of data transmission buffers 2 connected in parallel to the data processing unit 1, and a plurality of data communication means 3 respectively connected to the data transmission buffer 2. 1 is provided with interface means 4 for interfacing the writing of transmission data from each data transmission buffer 2, and the interface means 4 is capable of simultaneously writing the same transmission data from the data processing unit 1 into each data transmission buffer 2. It has been done.

[0009]

In FIG. 1, the transmission data output from the data processing unit 1 is simultaneously added to a plurality of data transmission buffers 2 _A and 2 _B connected in parallel to the data processing unit 1. Then, in synchronization with this, when the data processing unit 1 outputs a data write control signal to the interface means 4, the interface means 4 outputs a plurality of data write control signals WCS _A based on the data write control signal. , WCS _B is formed,
The same transmission data is transferred to each data transmission buffer 2 _A , 2
Write to _B simultaneously.

Therefore, the same transmission data can be transferred to the plurality of data transmission buffers 2 _A and 2 _B by one-time data writing control of the data processing unit 1, which is efficient. These transmission data are subsequently read out separately by each data communication means 3 _A, 3 _B, it is transmitted according to the communication timing of each channel CH-A, in CH-B. The data transmission buffer 2 and the data communication means 3 are not limited to two as shown in the drawing, but may be three or more.

Preferably, the interface means 4 writes the same transmission data from the data processing unit 1 into each data transmission buffer 2 simultaneously by the input of the mode signal, and the individual transmission data from the data processing unit 1 into each data transmission buffer 2. It is configured to be capable of switching between a mode for individually writing to the transmission buffer 2.

[0012]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 2 is a block diagram of the data communication apparatus of the first embodiment, and this first embodiment shows a case where a RAM is used as the buffer memory 2.

In the figure, 1 is a CPU, 2 _A and 2 _B are buffer memories (BUFM), 2 ₁ is a RAM, 2 ₂ is a data bus interface (DBIF), 2 ₃ is an address bus interface (ABIF), and 2 ₄ is a RAM 2 bus arbiter that arbitrates contention data access from the data access and the data communication unit 3 from CPU1 for _{1 (B-ABT), 3} a, 3 B is a data communication unit (C
U), 4 is a buffer interface (BIF) of the first embodiment for interfacing memory access between the CPU 1 and the buffer memories 2 _A and 2 _B , and 4 _1A and 4 _1B decode predetermined upper address signal UAD ₁ of the CPU ₁ . decoder (DEC), 4 ₃ the decoder latch for holding the other predetermined state of the upper address signal UAD ₂ 1 or mode signal SL of decoding outputs 0 of the CPU 1 (DEC
L), 4 ₂ denotes a selector, 5 is a RAM.

Seen from the CPU 1 side, the RAM 2 ₁ of the buffer memory 2 _A has a write area for the transmission data TxD-A (eg, hexadecimal 80000-9FFFF).
And a read area of received data RxD-A (A0000 to B
FFFF). Also RAM 2 ₁ of buffer memory 2 _B write area of the transmission data TxD-B (C0
000 to DFFFF) and a read area (E0000 to FFFFF) for receiving data RxD-B. On the other hand, the data communication unit 3 _A, 3 when viewed from the side of _B, the transmission data T each RAM 2 ₁ is the write area of the received data RxD (lower address LAD = 20000~3FFFF)
xD read area (lower address LDA = 00000-
1FFFF). Bus arbiter 2 ₄ is RA
Data access request RQ from CPU ₁ for M2 ₁
And data access request RQ from the data communication unit 3
As well as mediation of conflicts, to return the access permission signal AK to those who gain access RAM2 _1.

With such a configuration, the CPU 1 controls the predetermined upper address signal UAD ₂ = non-simultaneous transfer mode, and the control signal C.
And it outputs the P = 1, the output signal S of the decoder latch 4 ₃
L = becomes 1 (asynchronous transfer mode), the selector 4 ₂ selects the terminal b side as shown. In this state, CPU1
Can separately access the buffer memories 2 _A and 2 _B.

That is, the CPU 1 sends the address signal A = 800.
When 00 to 9FFFF is output, the memory energizing output E _W of the decoder 4 _1A is output by the memory cycle signal MC of the CPU 1 (that is, energizing the external buffer memory 2) and the predetermined upper address UAD ₁ = 8 or 9. = 1 and the write control signal W = 1 at that time causes the transmission data T of the CPU 1 to be transmitted.
xD-A is written into RAM 2 ₁ of the lower address LAD = 00000~1FFFF the buffer memory 2 _A.
Further, the CPU 1 sends the address signal A = A0000 to BFFF.
When F is output, MC = 0 and UAD ₁ = A or B, the read energizing signal E _R = 1 of the decoder 4 _1A is set, and the read control signal R = 1 at that time LAD of the RAM 2 ₁ of the buffer memory 2 _A = Received data RxD-A of 20000 to 3FFFF is fetched by the CPU 1.

Further, the CPU 1 causes the address signal A = C00.
When 00 to DFFFF is output, MC = 0 and UAD ₁
= Write energizing output E _W = 1 of the decoder 4 _1B depending on C or D
Then, the write control signal W = 1 at that time causes the CPU
The transmission data TxD-B of 1 is RA of the buffer memory 2 _B.
M2 is written to _one of the LAD = 00000~1FFFF. Further, the CPU 1 causes the address signal A = E0000 to FF
When FFF is output, MC = 0 and UAD ₁ = E or F
_Causes the read energizing signal E _R of the decoder 4 _1B to be 1 and the read control signal R = 1 at that time causes the buffer memory 2
Received data RxD-B of RAM 2 ₁ of LAD = 20000~3FFFF of _B is taken into CPU 1.

Next, when the CPU1 predetermined upper address signal UAD ₂ = simultaneous transfer mode, and outputs a control signal CP = 1, becomes an output signal SL = 0 of the decoder latch 4 ₃ (simultaneous transfer mode), the selector 4 ₂ selects the terminal a side. In this state, the CPU 1 to the buffer memory 2 _A ,
Writing of the transmission data TxD-A to 2 _B is performed at the same time,
The reading of the reception data RxD-A and RxD-B to the CPU 1 is performed separately.

That is, the CPU 1 sends the address signal A = 800.
When 00 to 9FFFF is output, MC = 0 and UAD ₁
= 8 or 9, write energizing output E _W = 1 of the decoder 4 _1A
Then, the write control signal W = 1 at that time causes the CPU
The transmission data TxD-A of 1 is RA of the buffer memory 2 _A.
M2 is written to _one of the LAD = 00000~1FFFF. Further, in this case, since the write energizing input E _{W of the} buffer memory 2 _B becomes 1 at the same time, the write control signal W = 1
Transmission data TxD-A of the can is also simultaneously written in the RAM 2 ₁ of LAD = 00000~1FFFF of the buffer memory 2 _B by.

Further, the CPU 1 sends the address signal A = A000.
When 0 to BFFFF is output, MC = 0 and UAD ₁ =
A or decoder 4 _1A read energizing signal E _R = 1 next to the B, RAM 2 ₁ of LAD in the buffer memory 2 _A by the read control signal R = 1 at that time = 20000～3FF
The reception data RxD-A of the FF is fetched by the CPU 1. Further, the CPU 1 causes the address signal A = E0000 to FF
When FFF is output, MC = 0 and UAD ₁ = E or F
_Causes the read energizing signal E _R of the decoder 4 _1B to be 1 and the read control signal R = 1 at that time causes the buffer memory 2
Received data RxD-B of RAM 2 ₁ of LAD = 20000~3FFFF of _B is taken into CPU 1.

FIG. 3 is a block diagram of a data communication apparatus according to the second embodiment. In the second embodiment, the buffer memory 2 has a FIF.
The case where O-type memories 2 ₅ and 2 ₆ are used is shown.
In the figure, 4 is a buffer interface (BIF) of the second embodiment, and 4 _4A and 4 _4B are the buffer interface units (BIFU). FIFO type memory 2 ₅
Is a dual port memory and a C
A write counter that manages the data write address on the PU1 side, a read counter that manages the data read address on the data communication unit 3 _A side, and a buffer full FL or buffer empty EP based on the count phase of both counters. And the output circuit. The same applies to the memory 2 ₆ of the FIFO type, in this case the read side of the CPU1 received data RxD-A, a data communication unit 3 _A is writing side of the received data RxD-A. The CPU 1 temporarily stops the data writing by the interrupt input of the buffer full FL, and temporarily stops the data reading by the interrupt input of the buffer empty EP.

With such a configuration, the CPU 1 can execute a predetermined high-order add.
Response signal UAD₂= Non-simultaneous transfer mode and control signal C
When P = 1 is output, BIFU4_4BOutput signal SL = 1
(Non-simultaneous transfer mode) and selector 4₂Is as shown
Select terminal b side. In this state, CPU1 is a buffer
Memory 2_A, 2_BEach access can be done separately. Immediately
Then, the CPU 1 uses the address signal A = buffer memory 2_Aof
Device address, MC = 0 and write control signal WT = 1
If set to, BIFU4_4AWrite pulse signal WP = 1
As a result, the transmission data TxD-A of the CPU 1 is
Far memory 2 _AWrite buffer 2_FiveWritten in. Well
CPU 1 has address signal A = buffer memory 2_ADe
Vise address, MC = 0 and read control signal RE = 1
Then BIFU4_4ARead pulse signal RE = 1
Therefore, the buffer memory 2 _ARead buffer 2₆
The received data RxD-A of is received in the CPU 1.

Similarly, the CPU 1 causes the address signal A =
When the device address of the buffer memory 2 _B , MC = 0 and the write control signal WT = 1 are set, the write pulse signal WP = 1 of the BIFU _{4 4B} is set, whereby the CPU at that time point is
1 of the transmission data TxD-B is written to the write buffer 2 ₅ of the buffer memory 2 _B. Further, the CPU 1 sends the address signal A = device address of the buffer memory 2 _B , MC
= 0 and read control signal RE = 1, BIFU4 _4B
Read pulse signal RE = 1 next, thereby the reception data RxD-B of the read buffer 2 ₆ of the buffer memory 2 _B
Are taken into the CPU 1.

Next, when the CPU 1 outputs a predetermined upper address signal UAD ₂ = simultaneous transfer mode and the control signal CP = 1, the output signal SL of BIFU4 _4B becomes SL = 0 (simultaneous transfer mode) and the selector 4 ₂ Select the terminal a side.
In this state, the transmission data TxD-A is written from the CPU 1 to the buffer memories 2 _A and 2 _B at the same time.
The reception data RxD-A and RxD-B for 1 are read separately.

That is, the CPU 1 sends the address signal A = buffer
Memory 2_ADevice address, MC = 0 and write control
Control signal WT = 1, BIFU4_4AWrite pulse signal
No. WP = 1, so that the transmission data T of the CPU 1
xD-A is buffer memory 2 _AWrite buffer 2_FiveWritten on
Be impressed. Also, in this case, the buffer memory 2 _B
Since the write pulse signal WP of 1 becomes 1, the same
Transmission data TxD-A of the buffer memory 2_BWrite
Tiffa 2_FiveAlso written at the same time.

Further, the CPU 1 uses the address signal A = buffer
Memory 2_ADevice address, MC = 0 and read control
When signal RE = 1, BIFU4_4AReadout pulse signal
RE = 1, so that the buffer memory 2_AReading
Buffer 2₆Received data RxD-A is stored in the CPU1.
Get stuck. Further, the CPU 1 has the address signal A = buffer
Memory 2_BDevice address, MC = 0 and read control
When signal RE = 1, BIFU4_4BReadout pulse signal
RE = 1, so that the buffer memory 2 _BReading
Buffer 2₆Received data RxD-B of
Get stuck.

In the above embodiment, the write energizing output E _W or the write pulse signal WP as the decoding result is switched by the selector 4 _2. However, the present invention is not limited to this. For example, in the first embodiment, the selector 4 ₂ is omitted and the mode signal S
Switching the decoding method of the decoder 4 _1B by L = 0, CPU 1 address signal A = 80000~9FFF
When F is output, the write energizing output E _W = 1 may be simultaneously output from the decoder 4 _1A and the decoder 4 _1B depending on MC = 0 and UAD ₁ = 8 or 9. Similarly, in the second embodiment, the selector 4 ₂ is omitted, the decoding method in the BIFU _{4 4B} is switched by the mode signal SL = 0, and the CPU 1 causes the address signal A = the device address of the buffer memory 2 _A , MC = 0, and the write operation. When the input control signal WT = 1, the write pulse signal WP = 1 may be simultaneously output from the BIFU4 _4A and BIFU4 _4B .

Further, the simultaneous / non-simultaneous transfer mode signal SL
May be configured to be changed by a manual switch. Further, although the wire type data communication apparatus has been described in the above embodiments, the present invention is applicable to data communication apparatuses of all communication methods such as a wireless method, an optical communication method and other sound waves.

Although the buffer memories 2 _A and 2 _B are provided in the above embodiment, for example, the transmission buffer 3 ₁ and the reception buffer 3 _{7 in the} data communication units 3 _A and 3 _B are provided.
Buffer memory 2 _A ,
Instead of 2 _B , the control of the present invention may be applied to the transmission buffer 3 ₁ and the reception buffer 3 ₇ .

[0030]

As described above, according to the present invention, the interface means 4 is constructed so that the same transmission data from the data processing unit 1 can be simultaneously written in the respective data transmission buffers 2, so that it can be used in a plurality of channels. On the other hand, the same transmission data can be efficiently distributed (copied), the control load of the data processing unit 1 is reduced, and the transmission data of a plurality of channels can be the same without error.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a data communication device according to a first embodiment.

FIG. 3 is a block diagram of a data communication device according to a second embodiment.

FIG. 4 is a block diagram of a conventional data communication device.

[Explanation of symbols]

 1 data processing unit 2 data transmission buffer 3 data communication means 4 interface means

Claims (2)

[Claims] 1. A data processing unit (1), a plurality of data transmission buffers (2) connected in parallel to the data processing unit (1), and a plurality of data communications connected to the data transmission buffer (2), respectively. A data communication device comprising means (3), comprising interface means (4) for interfacing writing of transmission data from the data processing section (1) to each data transmission buffer (2), the interface means (4) comprising A data communication device, characterized in that the same transmission data from the data processing unit (1) can be simultaneously written into each data transmission buffer (2). 2. A mode in which the interface means (4) simultaneously writes the same transmission data from the data processing unit (1) to each data transmission buffer (2) by inputting a mode signal, and a mode in which the data processing unit (1) outputs the same transmission data. 2. The data communication device according to claim 1, wherein a mode for individually writing individual transmission data to each data transmission buffer (2) is switchable.