JPH06338602A - Semiconductor memory and manufacture thereof - Google Patents
Semiconductor memory and manufacture thereofInfo
- Publication number
- JPH06338602A JPH06338602A JP5126958A JP12695893A JPH06338602A JP H06338602 A JPH06338602 A JP H06338602A JP 5126958 A JP5126958 A JP 5126958A JP 12695893 A JP12695893 A JP 12695893A JP H06338602 A JPH06338602 A JP H06338602A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- semiconductor
- forming
- film
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、特にＮＡＮＤ型ＥＥＰ
ＲＯＭのセル構造の改良に関する。BACKGROUND OF THE INVENTION The present invention is particularly applicable to NAND type EEP.
The present invention relates to improvement of a cell structure of a ROM.
【０００２】[0002]
【従来の技術】従来のＮＡＮＤ型ＥＥＰＲＯＭのセル構
造について説明する。図２１（ａ）〜（ｃ）は、従来の
ＮＡＮＤ型ＥＥＰＲＯＭのセル構造を示している。な
お、同図（ａ）は、当該セル構造の平面図、同図（ｂ）
は、同図（ａ）のＩ−Ｉ´線に沿う断面図、同図（ｃ）
は、同図（ａ）のII−II´線に沿う断面図である。2. Description of the Related Art A cell structure of a conventional NAND type EEPROM will be described. 21A to 21C show the cell structure of a conventional NAND type EEPROM. Note that FIG. 7A is a plan view of the cell structure, and FIG.
Is a cross-sectional view taken along the line II ′ of FIG.
FIG. 4B is a sectional view taken along line II-II ′ of FIG.
【０００３】図２１（ａ）〜（ｃ）において、第一導電
型の半導体基板１１上には、第二導電型のウエル１２が
形成されている。ウエル１２上には、素子分離絶縁膜１
３が形成されている。素子領域の一部には、トンネル酸
化膜１４が形成されている。トンネル酸化膜１４上に
は、フロ−ティングゲ−トとして機能する第一のポリシ
リコン電極１５が形成されている。第一のポリシリコン
電極１５上には、絶縁膜１６が形成されている。絶縁膜
１６上には、ワ−ド線及びコントロ−ルゲ−トとして機
能する第二のポリシリコン電極１７が形成されている。
さらに、素子領域において各々の第一のポリシリコン電
極１５の間には、ソ−ス・ドレイン拡散層１８が形成さ
れている。In FIGS. 21A to 21C, a well 12 of the second conductivity type is formed on a semiconductor substrate 11 of the first conductivity type. An element isolation insulating film 1 is formed on the well 12.
3 is formed. A tunnel oxide film 14 is formed in a part of the element region. A first polysilicon electrode 15 which functions as a floating gate is formed on the tunnel oxide film 14. An insulating film 16 is formed on the first polysilicon electrode 15. A second polysilicon electrode 17 which functions as a word line and a control gate is formed on the insulating film 16.
Further, a source / drain diffusion layer 18 is formed between the first polysilicon electrodes 15 in the element region.
【０００４】一個のセルは、一点破線Ａで囲んだ部分か
ら構成され、複数個（例えば１０個）のセルが直列接続
されている。両端にあるセル２０は、選択ゲ−トとして
の機能を果たすものである。従って、当該セル２０の第
一のポリシリコン電極１５と第二のポリシリコン電極１
７は、図示しない配線によって短絡されている。One cell is composed of a portion surrounded by a dashed line A, and a plurality of cells (for example, 10 cells) are connected in series. The cells 20 at both ends serve as a selection gate. Therefore, the first polysilicon electrode 15 and the second polysilicon electrode 1 of the cell 20 are
7 is short-circuited by a wiring not shown.
【０００５】選択ゲ−ト（セル２０）の間にある複数個
（例えば８個）のセル２１は、各々が１ビット分の記憶
を蓄えることができる実際のセルである。ビット線１９
は、一端側にある選択ゲ−ト（セル２０）の拡散層１８
に接続されている。このようなセル構造において、一般
に、ビット線１９に接続するセル２０側は、ドレイン側
と呼ばれる。A plurality of cells (for example, eight cells) 21 between the selection gates (cells 20) are actual cells each capable of storing one bit of memory. Bit line 19
Is the diffusion layer 18 of the selective gate (cell 20) on one end side.
It is connected to the. In such a cell structure, the cell 20 side connected to the bit line 19 is generally called the drain side.
【０００６】[0006]
【発明が解決しようとする課題】上記ＮＡＮＤ型ＥＥＰ
ＲＯＭのセル構造は、半導体基板上における単位面積当
りのセル数（ビット数）を向上させるものとして期待さ
れるものである。しかし、半導体記憶装置における集積
度の向上は止まるところを知らず、次世代における集積
度を達成するためのセル構造が要望されている。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The cell structure of a ROM is expected to improve the number of cells (bit number) per unit area on a semiconductor substrate. However, there is no end to the improvement in the degree of integration in semiconductor memory devices, and there is a demand for a cell structure for achieving the degree of integration in the next generation.
【０００７】本発明は、上記要望に鑑みてなされたもの
で、その目的は、写真蝕刻技術の改善にたよることな
く、次世代における集積度を達成することが可能な半導
体記憶装置及びその製造方法を提供することである。The present invention has been made in view of the above demands, and an object thereof is a semiconductor memory device capable of achieving the next-generation degree of integration without depending on the improvement of the photo-etching technique and its manufacture. Is to provide a method.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明の半導体記憶装置は、半導体基板と、前記半
導体基板上に形成される半導体柱と、前記半導体柱に複
数段を形成する素子分離絶縁膜と、前記素子分離絶縁膜
の間であって、前記複数段のうち最上段と最下段にそれ
ぞれ形成される選択ゲ−トと、前記最上段と最下段の間
の各段にそれぞれ形成されるメモリセルとを備える。In order to achieve the above object, a semiconductor memory device of the present invention is a semiconductor substrate, a semiconductor pillar formed on the semiconductor substrate, and an element for forming a plurality of steps on the semiconductor pillar. Between the isolation insulating film and the element isolation insulating film, selection gates formed in the uppermost stage and the lowermost stage of the plurality of stages, and in each stage between the uppermost stage and the lowermost stage, respectively. Formed memory cells.
【０００９】前記選択ゲ−トは、前記半導体柱の側壁に
第一の絶縁膜を介して形成される第一の導電膜を有す
る。前記メモリセルは、前記半導体柱の側壁にトンネル
絶縁膜を介して形成され、フロ−ティングゲ−トとして
機能する第二の導電膜、及び前記第二の導電膜上に第二
の絶縁膜を介して形成され、コントロ−ルゲ−トとして
機能する第三の導電膜を有する。そして、前記第一の絶
縁膜と前記第二の絶縁膜、及び前記第一の導電膜と前記
第三の導電膜は、それぞれ同一の材料から構成されてい
る。The selection gate has a first conductive film formed on the sidewall of the semiconductor pillar with a first insulating film interposed therebetween. The memory cell is formed on a sidewall of the semiconductor pillar via a tunnel insulating film, and has a second conductive film functioning as a floating gate, and a second insulating film on the second conductive film. And a third conductive film functioning as a control gate. The first insulating film and the second insulating film, and the first conductive film and the third conductive film are made of the same material.
【００１０】前記フロ−ティングゲ−トとして機能する
第二の導電膜は、各段において、前記半導体柱を取り巻
くリング状に形成されている。前記素子分離絶縁膜の間
であって、前記複数段のうち最上段と最下段の高さは、
その最上段と最下段の間の各段の高さよりも高くなるよ
うに構成されている。その結果、前記選択ゲ−トのゲ−
ト長は、前記メモリセルのゲ−ト長よりも長くなってい
る。The second conductive film functioning as the floating gate is formed in a ring shape surrounding the semiconductor pillar in each stage. Between the element isolation insulating films, the height of the uppermost stage and the lowermost stage among the plurality of stages is
It is configured to be higher than the height of each stage between the uppermost stage and the lowermost stage. As a result, the gate of the selected gate is
The gate length is longer than the gate length of the memory cell.
【００１１】前記半導体柱の側壁であって、前記複数段
を構成する前記素子分離絶縁膜の各段に隣接してリング
状に形成されるソ−ス・ドレイン拡散層と、前記半導体
基板中に形成され、前記最下段の選択ゲ−トのソ−ス・
ドレイン拡散層に接続されるソ−ス拡散層と、前記半導
体柱の最上部に形成され、前記最上段の選択ゲ−トのソ
−ス・ドレイン拡散層に接続されるドレイン拡散層とを
有する。A source / drain diffusion layer formed in a ring shape on the side wall of the semiconductor pillar, adjacent to each step of the element isolation insulating film forming the plurality of steps, and in the semiconductor substrate. The source of the selection gate at the bottom is formed.
A source diffusion layer connected to the drain diffusion layer and a drain diffusion layer formed on the uppermost part of the semiconductor pillar and connected to the source / drain diffusion layer of the uppermost selection gate. .
【００１２】前記半導体柱は、前記半導体基板上に行列
状に複数形成され、行方向の半導体柱における当該ドレ
イン拡散層に共通に接続するビット線を有する。前記半
導体柱は、前記半導体基板上に行列状に複数形成され、
前記複数段を構成する素子分離絶縁膜の各段は、列方向
の半導体柱に共通して棚状に形成される。前記選択ゲ−
トの第一の導電膜及び前記コントロ−ルゲ−トとして機
能する第三の導電膜は、それぞれ列方向の半導体柱に共
通し、かつ、各段において、それぞれ列方向に帯状に形
成されている。A plurality of the semiconductor pillars are formed in a matrix on the semiconductor substrate and have bit lines commonly connected to the drain diffusion layers of the semiconductor pillars in the row direction. A plurality of the semiconductor pillars are formed in a matrix on the semiconductor substrate,
Each step of the element isolation insulating film forming the plurality of steps is formed in a shelf shape commonly to the semiconductor pillars in the column direction. The selection gate
The first conductive film of the gate and the third conductive film functioning as the control gate are common to the semiconductor pillars in the column direction, and are formed in strips in the column direction in each stage. .
【００１３】前記選択ゲ−トの第一の導電膜及び前記コ
ントロ−ルゲ−トとして機能する第三の導電膜は、それ
ぞれ列方向の端部において階段状に形成され、その階段
状の部分にコンタクト部が設けられている。The first conductive film of the selective gate and the third conductive film functioning as the control gate are formed stepwise at the ends in the column direction, and the stepwise portions are formed at the stepwise portions. A contact portion is provided.
【００１４】本発明の半導体記憶装置の製造方法は、ま
ず、第一の工程として、半導体基板上に第一の絶縁膜を
形成し、前記第一の絶縁膜上に第二の絶縁膜を形成す
る。次に、第二の工程として、前記第二の絶縁膜上に、
少なくとも１回以上、次の (i),(ii)の工程、即ち (i)
第三の絶縁膜を形成する工程、及び(ii) 前記第三の
絶縁膜上に第四の絶縁膜を形成する工程を繰り返し実行
することにより得られる積層膜を形成する。次に、第三
の工程として、前記積層膜上に第五の絶縁膜を形成し、
前記第五の絶縁膜上に第六の絶縁膜を形成する。次に、
第四の工程として、前記第六の絶縁膜上に第七の絶縁膜
をを形成し、前記第七の絶縁膜上に第八の絶縁膜を形成
する。次に、第五の工程として、前記第八の絶縁膜の表
面から前記半導体基板まで達する行列状の複数の穴を形
成する。次に、第六の工程として、選択エピタキシャル
成長法により、各々の穴内に、半導体を成長させ、行列
状の半導体柱を形成する。次に、第七の工程として、前
記第一乃至第八の絶縁膜からなる多層膜をエッチング
し、半導体柱の各列の間であって、列方向に伸びるスト
ライプ状の溝を形成する。次に、第八の工程として、前
記第二、第四、第六及び第八の絶縁膜を選択的にエッチ
ングすることにより、残存した前記第一、第三、第五及
び第七の絶縁膜であって、列方向の半導体柱に支えられ
た複数段の棚状のものを形成する。次に、第九の工程と
して、前記複数段のうち、前記第一の絶縁膜と前記第三
の絶縁膜の間の最下段及び前記第五の絶縁膜と前記第七
の絶縁膜の間の最上段に選択ゲ−トを形成し、前記最下
段と最上段の間の各段にメモリセルを形成するものであ
る。In the method of manufacturing a semiconductor memory device of the present invention, first, as a first step, a first insulating film is formed on a semiconductor substrate, and a second insulating film is formed on the first insulating film. To do. Next, as a second step, on the second insulating film,
At least once, the following steps (i) and (ii), that is, (i)
A laminated film obtained by repeatedly performing the step of forming the third insulating film, and (ii) the step of forming the fourth insulating film on the third insulating film is formed. Next, as a third step, a fifth insulating film is formed on the laminated film,
A sixth insulating film is formed on the fifth insulating film. next,
As a fourth step, a seventh insulating film is formed on the sixth insulating film, and an eighth insulating film is formed on the seventh insulating film. Next, as a fifth step, a plurality of holes in a matrix form from the surface of the eighth insulating film to the semiconductor substrate are formed. Next, as a sixth step, a semiconductor is grown in each hole by a selective epitaxial growth method to form a matrix of semiconductor columns. Next, as a seventh step, the multilayer film formed of the first to eighth insulating films is etched to form stripe-shaped grooves extending in the column direction between the columns of the semiconductor pillar. Next, in an eighth step, the remaining first, third, fifth and seventh insulating films are formed by selectively etching the second, fourth, sixth and eighth insulating films. In this case, a plurality of stages of shelves supported by semiconductor columns in the column direction are formed. Next, as a ninth step, among the plurality of steps, a bottom step between the first insulating film and the third insulating film and a step between the fifth insulating film and the seventh insulating film are performed. A select gate is formed on the uppermost stage, and a memory cell is formed on each stage between the lowermost stage and the uppermost stage.
【００１５】前記第一の工程は、前記第二の絶縁膜の列
方向の端部を部分的にエッチングする工程を有し、前記
第二の工程は、少なくとも１回以上、前記 (i)，(ii)の
工程及び (iii) 前記第四の絶縁膜の列方向の端部を部
分的にエッチングする工程を繰り返し実行するものであ
り、前記第三の工程は、前記第六の絶縁膜の列方向の端
部を部分的にエッチングする工程を有し、前記第四の工
程は、前記第八の絶縁膜の列方向の端部を部分的にエッ
チングする工程を有ている。そして、前記列方向の端部
では、前記第二、第四、第六及び第八の絶縁膜は、階段
状に形成されるものである。The first step includes a step of partially etching an end portion of the second insulating film in the column direction, and the second step is performed at least once or more, in (i), The step (ii) and (iii) the step of partially etching the end portion in the column direction of the fourth insulating film is repeatedly performed, and the third step is to form the sixth insulating film. The method has a step of partially etching the end portion in the column direction, and the fourth step has a step of partially etching the end portion in the column direction of the eighth insulating film. Then, at the end portion in the column direction, the second, fourth, sixth and eighth insulating films are formed stepwise.
【００１６】前記第五の工程と前記第六の工程の間に、
以下の工程を含んでいる。まず、等方性エッチングによ
り、各穴内の前記第一、第三、第五及び第七の絶縁膜を
所定量だけエッチングし、後退部を形成する。次に、等
方性エッチングにより、各穴内の前記第二、第四、第六
及び第八の絶縁膜を所定量だけエッチングし、前記後退
部を拡張する。次に、前記後退部を含む前記各穴の側壁
に第九の絶縁膜を形成する。次に、前記第九の絶縁膜上
に、前記後退部を埋め込み、不純物を含む第十の絶縁膜
を形成する。次に、等方性エッチングにより、前記第九
及び第十の絶縁膜を前記各穴内の後退部にのみ残存させ
る。Between the fifth step and the sixth step,
It includes the following steps. First, the first, third, fifth and seventh insulating films in each hole are etched by a predetermined amount by isotropic etching to form a recessed portion. Next, the second, fourth, sixth and eighth insulating films in each hole are etched by a predetermined amount by isotropic etching to expand the recessed portion. Next, a ninth insulating film is formed on the sidewall of each hole including the recessed portion. Next, the recessed portion is embedded on the ninth insulating film to form a tenth insulating film containing impurities. Next, the ninth and tenth insulating films are left only in the recessed portions in the holes by isotropic etching.
【００１７】また、前記第六の工程と前記第七の工程の
間に、熱処理を行い、前記第十の絶縁膜中の不純物を当
該半導体柱の側壁に拡散させ、各半導体柱の側壁にリン
グ状のソ−ス・ドレイン領域を形成する工程を含んでい
る。In addition, heat treatment is performed between the sixth step and the seventh step to diffuse the impurities in the tenth insulating film to the sidewalls of the semiconductor pillar, and ring the sidewalls of each semiconductor pillar. Forming a source-drain region in the shape of a circle.
【００１８】前記第二及び第六の絶縁膜の膜厚は、前記
第四の絶縁膜の膜厚よりも大きく設定されている。そし
て、前記第九の工程は、以下の工程を含んでいる。ま
ず、各半導体柱の側壁に第十一の絶縁膜を形成する。次
に、全面に、第一の導電膜を形成する。次に、等方性エ
ッチングにより、前記第十一の絶縁膜及び前記第一の導
電膜を所定量だけエッチングし、前記第十一の絶縁膜及
び前記第一の導電膜を前記最下段と最上段を除く各段に
のみ残存させ、前記最下段と最上段を除く各段にのみ当
該半導体柱を取り巻くリング状のフロ−ティングゲ−ト
を形成する。次に、全面に、第十二の絶縁膜を形成す
る。次に、全面に、第二の導電膜を形成する。次に、等
方性エッチングにより、前記第二の導電膜を所定量だけ
エッチングし、当該第二の導電膜を、前記複数段を構成
する素子分離絶縁膜の各段に残存させ、前記最下段と最
上段に列方向に伸びる帯状の選択ゲ−ト線を形成し、前
記最下段と最上段の間の各段に列方向に伸びる帯状のワ
−ド線を形成する。The film thicknesses of the second and sixth insulating films are set to be larger than the film thickness of the fourth insulating film. Then, the ninth step includes the following steps. First, an eleventh insulating film is formed on the side wall of each semiconductor pillar. Next, a first conductive film is formed on the entire surface. Next, the eleventh insulating film and the first conductive film are etched by a predetermined amount by isotropic etching to remove the eleventh insulating film and the first conductive film from the lowermost layer and the uppermost conductive film. The ring-shaped floating gate surrounding the semiconductor pillar is formed only in each of the stages except the uppermost stage and the lowermost stage and the uppermost stage. Next, a twelfth insulating film is formed on the entire surface. Next, a second conductive film is formed on the entire surface. Next, the second conductive film is etched by a predetermined amount by isotropic etching, and the second conductive film is left in each stage of the element isolation insulating film forming the plurality of stages. A strip-shaped selection gate line extending in the column direction is formed on the uppermost stage, and a strip-shaped word line extending in the column direction is formed on each stage between the lowermost stage and the uppermost stage.
【００１９】前記第一の工程の前に、前記半導体基板中
にソ−ス領域を形成する工程を有している。また，前記
第九の工程の後に、各半導体柱の最上部にドレイン領域
を形成する工程と、行方向の半導体柱のドレイン拡散層
に接続するビット線を形成する工程と有している。Before the first step, there is a step of forming a source region in the semiconductor substrate. Further, after the ninth step, there are steps of forming a drain region on the top of each semiconductor pillar and forming a bit line connected to the drain diffusion layer of the semiconductor pillar in the row direction.
【００２０】[0020]
【作用】上記構成によれば、半導体基板上には半導体柱
が形成されている。従って、従来、平面的に形成されて
いたメモリセルを、当該半導体柱の側壁に立体的に形成
することができる。これにより、従来に比べ、格段に、
集積度の向上（単位面積当りのセル数の増大）を図るこ
とができ、写真蝕刻技術の改善にたよることなく、次世
代におけるＬＳＩに貢献することができる。According to the above structure, the semiconductor pillar is formed on the semiconductor substrate. Therefore, it is possible to three-dimensionally form the memory cell, which is conventionally formed in a plane, on the side wall of the semiconductor pillar. As a result, compared to the past,
It is possible to improve the degree of integration (increase the number of cells per unit area) and contribute to the next-generation LSI without relying on the improvement of the photo-etching technique.
【００２１】また、当該セル構造を提供するにあたって
は、半導体柱を利用することにより、自己整合的な工程
を達成することができるため、簡単に、上記構造を提供
できる。しかも、製造工程中、等方性エッチングが主と
して用いられるため、加工も行い易い。In providing the cell structure, a semiconductor pillar can be used to achieve a self-aligned process, so that the above structure can be easily provided. Moreover, since isotropic etching is mainly used during the manufacturing process, processing is easy to perform.
【００２２】[0022]
【実施例】以下、図面を参照しながら、本発明の半導体
記憶装置及びその製造方法について詳細に説明する。ま
ず、本発明の半導体記憶装置について説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail below with reference to the drawings. First, the semiconductor memory device of the present invention will be described.
【００２３】図１〜図３は、本発明の一実施例に係わる
ＮＡＮＤ型ＥＥＰＲＯＭのセル構造を示すものである。
なお、図１は、当該セル構造の平面図、図２は、図１の
III−III ´線に沿う断面図、図３は、図１のIV−IV´
線に沿う断面図である。1 to 3 show a cell structure of a NAND type EEPROM according to an embodiment of the present invention.
1 is a plan view of the cell structure, and FIG. 2 is a plan view of FIG.
A cross-sectional view taken along the line III-III ', and FIG. 3 shows IV-IV' of FIG.
It is sectional drawing which follows the line.
【００２４】第一導電型の半導体基板３１上には、第一
導電型の半導体柱３２が形成されている。この半導体柱
３２は、例えば半導体基板３１上に行列状に形成され
る。また、半導体柱３２の形状は、図示するように角柱
であってもよいし、又は円柱であってもよい。First-conductivity-type semiconductor columns 32 are formed on a first-conductivity-type semiconductor substrate 31. The semiconductor pillars 32 are formed in a matrix on the semiconductor substrate 31, for example. The shape of the semiconductor pillar 32 may be a prism as shown in the figure, or may be a cylinder.
【００２５】半導体柱３２には、この半導体柱３２を複
数段に分ける素子分離絶縁膜２５が形成されている。こ
の複数段を構成する素子分離絶縁膜２５の各段は、列方
向の半導体柱３２に共通して棚状に形成されている。The semiconductor pillar 32 is provided with an element isolation insulating film 25 which divides the semiconductor pillar 32 into a plurality of stages. Each step of the element isolation insulating film 25 forming the plurality of steps is formed in a shelf shape commonly to the semiconductor pillars 32 in the column direction.
【００２６】半導体柱３２の側壁であって、素子分離絶
縁膜２５の各段には、それぞれ１個のセルが形成されて
いる。なお、一つの半導体柱３２には、複数個（例えば
１１個）のセルが直列接続される。A cell is formed on each side of the semiconductor pillar 32 and on each step of the element isolation insulating film 25. In addition, a plurality of (for example, 11) cells are connected in series to one semiconductor pillar 32.
【００２７】素子分離絶縁膜２５の各段のうち、最上段
と最下段に形成されるセルは、選択ゲ−ト３３−１，３
３−２である。選択ゲ−ト３３−１，３３−２は、それ
ぞれ半導体柱３２の側壁に絶縁膜３４を介して形成され
るポリシリコン電極３５を有している。このポリシリコ
ン電極３５は、例えばワ−ド線が延在する方向にある半
導体柱３２の最下段又は最上段の選択ゲ−トに共通して
おり、かつ、各段において、それぞれ列方向に帯状に形
成されている。Among the respective stages of the element isolation insulating film 25, the cells formed in the uppermost stage and the lowermost stage are selected gates 33-1 and 3-3.
3-2. Each of the selection gates 33-1 and 33-2 has a polysilicon electrode 35 formed on the side wall of the semiconductor pillar 32 with an insulating film 34 interposed therebetween. This polysilicon electrode 35 is common to, for example, the lowermost or uppermost selection gate of the semiconductor pillar 32 in the direction in which the word line extends, and in each stage, it has a strip shape in the column direction. Is formed in.
【００２８】ポリシリコン電極３５の列方向の端部の所
定の箇所には、コンタクト部３６が形成されている。な
お、図４（ａ）は、選択ゲ−トのポリシリコン電極３５
のみを取り出して示すものである。A contact portion 36 is formed at a predetermined position on the end portion of the polysilicon electrode 35 in the column direction. Incidentally, FIG. 4A shows a polysilicon electrode 35 of the selective gate.
Only the one is taken out and shown.
【００２９】半導体柱３２の側壁において、選択ゲ−ト
３３−１，３３−２が形成される最下段及び最上段の間
の各段にあるセルは、各々が１ビット分の記憶を蓄える
ことができるメモリセル３７−１〜３７−９である。本
実施例では、メモリセル３７−１〜３７−９は、半導体
柱３２の側壁に９個形成されているが、この個数は任意
に決めることができるものである。On the side wall of the semiconductor pillar 32, the cells in each stage between the lowermost stage and the uppermost stage where the selective gates 33-1 and 33-2 are formed each store 1 bit of memory. Memory cells 37-1 to 37-9 capable of performing the above. In this embodiment, nine memory cells 37-1 to 37-9 are formed on the side wall of the semiconductor pillar 32, but this number can be arbitrarily determined.
【００３０】メモリセル３７−１〜３７−９は、各々が
半導体柱３２の側壁に絶縁膜（トンネル酸化膜）３８を
介して形成されるポリシリコン電極３９を有している。
このポリシリコン電極３９の形状は、半導体柱３２を取
り囲むリング状である。ポリシリコン電極３９は、フロ
−ティングゲ−トとしての機能を果たすものである。Each of the memory cells 37-1 to 37-9 has a polysilicon electrode 39 formed on the sidewall of the semiconductor pillar 32 with an insulating film (tunnel oxide film) 38 interposed therebetween.
The polysilicon electrode 39 has a ring shape surrounding the semiconductor pillar 32. The polysilicon electrode 39 functions as a floating gate.
【００３１】各々のメモリセル３７−１〜３７−９のポ
リシリコン電極３９上には、絶縁膜４０を介してポリシ
リコン電極４１が形成されている。このポリシリコン電
極４１は、ワ−ド線及びコントロ−ルゲ−トとして機能
するものである。ポリシリコン電極４１は、最下段及び
最上段の間の各段において、それが延在する方向にある
半導体柱３２の各段のメモリセルに共通しており、か
つ、列方向に帯状に形成されている。A polysilicon electrode 41 is formed on the polysilicon electrode 39 of each of the memory cells 37-1 to 37-9 with an insulating film 40 interposed therebetween. The polysilicon electrode 41 functions as a word line and a control gate. The polysilicon electrode 41 is common to the memory cells of each stage of the semiconductor pillar 32 in the extending direction in each stage between the lowermost stage and the uppermost stage, and is formed in a strip shape in the column direction. ing.
【００３２】ポリシリコン電極４１の列方向の端部は、
階段状に形成されており、その階段状の部分における所
定の箇所には、コンタクト部４２が形成されている。な
お、図４（ｂ）は、一つのポリシリコン電極（ワ−ド
線）４１のみを取り出して示すものである。The ends of the polysilicon electrodes 41 in the column direction are
The contact portion 42 is formed in a stepped shape, and the contact portion 42 is formed at a predetermined position in the stepped portion. Note that FIG. 4B shows only one polysilicon electrode (word line) 41 taken out.
【００３３】各々のポリシリコン電極３５，３９の間に
は、第二導電型のソ−ス・ドレイン拡散層４３が形成さ
れている。最下段の選択ゲ−ト３３−２の拡散層４３
は、半導体基板３１中に形成された第二導電型のソ−ス
拡散層４４に接続されている。半導体柱３２の最上部に
は、第二導電型のドレイン拡散層４５が形成されてい
る。このドレイン拡散層４５は、最上段の選択ゲ−ト３
３−１の拡散層となっている。A second conductivity type source / drain diffusion layer 43 is formed between the polysilicon electrodes 35 and 39. Diffusion layer 43 of selection gate 33-2 at the bottom
Are connected to a second conductivity type source diffusion layer 44 formed in the semiconductor substrate 31. A second conductivity type drain diffusion layer 45 is formed on the uppermost part of the semiconductor pillar 32. The drain diffusion layer 45 is the uppermost selection gate 3
It is a diffusion layer 3-1.
【００３４】半導体柱３２は、絶縁膜４６によって完全
に覆われており、絶縁膜４６の表面は平坦になってい
る。絶縁膜４６には、半導体柱３２の最上部にあるドレ
イン拡散層４５に達するコンタクトホ−ル４７が形成さ
れている。ビット線４８は、絶縁膜４６上に形成され、
コンタクトホ−ル４７を介してドレイン拡散層４５に接
続されている。また、ビット線４８は、ワ−ド線である
ポリシリコン電極４１に直交して配線され、かつ、行方
向の半導体柱３２のドレイン拡散層４５に共通して接続
されている。The semiconductor pillar 32 is completely covered with the insulating film 46, and the surface of the insulating film 46 is flat. A contact hole 47 reaching the drain diffusion layer 45 at the uppermost part of the semiconductor pillar 32 is formed in the insulating film 46. The bit line 48 is formed on the insulating film 46,
It is connected to the drain diffusion layer 45 via a contact hole 47. The bit line 48 is wired orthogonally to the polysilicon electrode 41, which is a word line, and is commonly connected to the drain diffusion layer 45 of the semiconductor pillar 32 in the row direction.
【００３５】選択ゲ−トのポリシリコン電極３５及びメ
モリセルのポリシリコン電極４１は、半導体基板３１上
に絶縁膜４９を介して積層されている。そこで、図１及
び図３に示すように、これらポリシリコン電極３５，４
１は、その端部において階段状となるように構成されて
いる。従って、絶縁膜４６に、各々のポリシリコン電極
３５，４１に達するコンタクトホ−ル５０を設けること
ができ、配線材料５１を各々のポリシリコン電極３５，
４１に接続することができる。なお、５２は、フィ−ル
ド絶縁膜である。The polysilicon electrode 35 of the selection gate and the polysilicon electrode 41 of the memory cell are laminated on the semiconductor substrate 31 with an insulating film 49 interposed therebetween. Therefore, as shown in FIGS. 1 and 3, these polysilicon electrodes 35, 4
1 is configured to have a stepped shape at its end. Therefore, the insulating film 46 can be provided with the contact holes 50 reaching the respective polysilicon electrodes 35 and 41, and the wiring material 51 can be provided to the polysilicon electrodes 35 and 41.
41 can be connected. Reference numeral 52 is a field insulating film.
【００３６】上記構成によれば、ＮＡＮＤ型ＥＥＰＲＯ
Ｍの各々のメモリセルは、半導体基板に対して垂直方向
に伸びた半導体柱に形成されている。従って、従来の半
導体基板に平面的にメモリセルが形成されていた場合に
比べ、格段に高集積化（単位面積当りのセル数の向上）
を図ることができる。According to the above configuration, the NAND type EEPROM
Each memory cell of M is formed in a semiconductor pillar extending in a direction perpendicular to the semiconductor substrate. Therefore, as compared with the case where memory cells are formed in a plane on a conventional semiconductor substrate, the degree of integration is remarkably high (the number of cells per unit area is improved).
Can be achieved.
【００３７】次に、上記ＮＡＮＤ型ＥＥＰＲＯＭの動作
について説明する。デ−タの消去時には、例えば選択ゲ
−トのポリシリコン電極３５及びメモリセルのポリシリ
コン電極４１にそれぞれ接地電位（０Ｖ）を印加する。
また、半導体基板３１及び半導体柱３２に正の高電位を
印加する。これにより、リング状のポリシリコン電極３
９の電子が絶縁膜（トンネル酸化膜）３８を介して半導
体柱３２へ抜け（Ｆ−Ｎトンネリング現象）、メモリセ
ルの閾値Ｖｔｈが負になる。Next, the operation of the NAND type EEPROM will be described. At the time of erasing data, for example, the ground potential (0 V) is applied to the polysilicon electrode 35 of the select gate and the polysilicon electrode 41 of the memory cell.
Further, a positive high potential is applied to the semiconductor substrate 31 and the semiconductor pillar 32. As a result, the ring-shaped polysilicon electrode 3
The electrons of 9 escape to the semiconductor pillar 32 through the insulating film (tunnel oxide film) 38 (F-N tunneling phenomenon), and the threshold Vth of the memory cell becomes negative.
【００３８】デ−タ“１”の書込み時には、ビット線４
８には１０Ｖを印加する。また、選択した（デ−タを書
き込む）メモリセルのポリシリコン電極４１には２０Ｖ
を印加し、非選択の（デ−タを書き込まない）メモリセ
ルのポリシリコン電極４１には１０Ｖを印加する。ま
た、最下端（ソ−ス側）の選択ゲ−ト３３−２のポリシ
リコン電極３５には接地電位（０Ｖ）を印加し、最上端
（ドレイン側）の選択ゲ−ト３３−１のポリシリコン電
極３５には１２Ｖを印加する。When writing the data "1", the bit line 4
10V is applied to 8. Further, 20V is applied to the polysilicon electrode 41 of the selected memory cell (writing data).
Is applied, and 10 V is applied to the polysilicon electrode 41 of the non-selected memory cell (where no data is written). Further, a ground potential (0 V) is applied to the polysilicon electrode 35 of the selection gate 33-2 at the bottom end (source side), and the polysilicon of the selection gate 33-1 at the top end (drain side) is applied. 12V is applied to the silicon electrode 35.
【００３９】これにより、選択したメモリセルのチャネ
ルとポリシリコン電極（コントロ−ルゲ−ト）４１の間
の電圧は、約１３Ｖとなる。従って、電子は、半導体柱
３２から選択したメモリセルのポリシリコン電極（フロ
−ティングゲ−ト）３９へ注入され難く、メモリセルの
閾値Ｖｔｈは、負のままに保たれる。As a result, the voltage between the channel of the selected memory cell and the polysilicon electrode (control gate) 41 becomes about 13V. Therefore, it is difficult for electrons to be injected from the semiconductor pillar 32 into the polysilicon electrode (floating gate) 39 of the selected memory cell, and the threshold Vth of the memory cell is kept negative.
【００４０】デ−タ“０”の書込み時には、ビット線４
８に接地電位（０Ｖ）を印加する。また、選択した（デ
−タを書き込む）メモリセルのポリシリコン電極４１に
は２０Ｖを印加し、非選択の（デ−タを書き込まない）
メモリセルのポリシリコン電極４１には１０Ｖを印加す
る。また、最下端（ソ−ス側）の選択ゲ−ト３３−２の
ポリシリコン電極３５には接地電位（０Ｖ）を印加し、
最上端（ドレイン側）の選択ゲ−ト３３−１のポリシリ
コン電極３５には１２Ｖを印加する。When writing data "0", the bit line 4
A ground potential (0 V) is applied to 8. In addition, 20V is applied to the polysilicon electrode 41 of the selected memory cell (writing data) and it is not selected (data is not written).
10V is applied to the polysilicon electrode 41 of the memory cell. Further, a ground potential (0 V) is applied to the polysilicon electrode 35 of the selection gate 33-2 at the bottom end (source side),
12V is applied to the polysilicon electrode 35 of the selection gate 33-1 at the uppermost end (drain side).
【００４１】これにより、選択したメモリセルのチャネ
ルとポリシリコン電極（コントロ−ルゲ−ト）４１の間
の電圧は、約２０Ｖとなる。従って、電子は、半導体柱
３２から選択したメモリセルのポリシリコン電極（フロ
−ティングゲ−ト）３９へ注入され、メモリセルの閾値
Ｖｔｈは、正（但し、５Ｖ以下）となる。As a result, the voltage between the channel of the selected memory cell and the polysilicon electrode (control gate) 41 becomes about 20V. Therefore, the electrons are injected from the semiconductor pillar 32 into the polysilicon electrode (floating gate) 39 of the selected memory cell, and the threshold Vth of the memory cell becomes positive (however, 5 V or less).
【００４２】デ−タの読出し時には、ビット線４８に２
０Ｖ、ソ−ス拡散層４４には接地電位（０Ｖ）、選択し
た（デ−タを読み出す）メモリセルのポリシリコン電極
（ワ−ド線）４１には０Ｖを印加する。また、非選択の
（デ−タを読み出さない）メモリセルのポリシリコン電
極（ワ−ド線）４１、並びに最下端（ソ−ス側）及び最
上端（ドレイン側）の選択ゲ−トのポリシリコン電極３
５には、それぞれ５Ｖを印加する。At the time of reading data, 2 is applied to the bit line 48.
0V, ground potential (0V) is applied to the source diffusion layer 44, and 0V is applied to the polysilicon electrode (word line) 41 of the selected (reading data) memory cell. Further, the polysilicon electrode (word line) 41 of the non-selected (data is not read) memory cell, and the polysilicon of the selection gate at the lowermost end (source side) and the uppermost end (drain side). Silicon electrode 3
5V is applied to 5 respectively.
【００４３】これにより、選択したメモリセルのデ−タ
が“１”の場合、その閾値は負のため、当該メモリセル
は導通状態（オン状態）となる。一方、選択したメモリ
セルのデ−タが“０”の場合、その閾値は正であるた
め、当該メモリセルは非導通状態（オフ状態）となる。
なお、選択されていないメモリセルでは、ポリシリコン
電極（ワ−ド線）４１の電位は５Ｖであるため、メモリ
セルに記憶されているデ−タが如何なる値（“１”又は
“０”）であっても、導通状態（オン状態）となる。As a result, when the data of the selected memory cell is "1", the threshold value of the memory cell is negative, so that the memory cell becomes conductive (ON state). On the other hand, when the data of the selected memory cell is "0", the threshold value is positive, and the memory cell is in the non-conducting state (off state).
In the unselected memory cell, the potential of the polysilicon electrode (word line) 41 is 5 V, so that the data stored in the memory cell has any value ("1" or "0"). Even in this case, it is in a conductive state (on state).
【００４４】次に、本発明の半導体記憶装置の製造方法
について説明する。図５〜図２０は、本発明の一実施例
に係わるＮＡＮＤ型ＥＥＰＲＯＭのセル構造の製造方法
を示すものである。Next, a method of manufacturing the semiconductor memory device of the present invention will be described. 5 to 20 show a method of manufacturing a cell structure of a NAND type EEPROM according to an embodiment of the present invention.
【００４５】まず、図５及び図６に示すように、第一導
電型の半導体基板５１の表面領域に、フィ−ルド絶縁膜
７１を形成する。なお、図６は、図５のＡの部分をＢの
方向から見た図である。半導体基板５１の素子領域に、
ＮＡＮＤ型ＥＥＰＲＯＭのメモリセルのソ−ス拡散層５
０を形成する。First, as shown in FIGS. 5 and 6, a field insulating film 71 is formed in the surface region of the first conductivity type semiconductor substrate 51. Note that FIG. 6 is a view of the portion A in FIG. 5 viewed from the direction B. In the element region of the semiconductor substrate 51,
Source diffusion layer 5 of NAND type EEPROM memory cell
Form 0.
【００４６】次に、第一導電型の半導体基板５１上に、
膜厚が約５０ｎｍの第一の絶縁膜（例えばシリコン窒化
膜）５２を形成する。第一の絶縁膜５２上に、膜厚が約
６００ｎｍの第二の絶縁膜（例えばシリコン酸化膜）５
３を形成する。この後、写真蝕刻技術とエッチング技術
を用いて、例えば半導体基板５１の列方向の端部（素子
分離絶縁膜７１上）において第二の絶縁膜５３を部分的
にエッチングする。Next, on the semiconductor substrate 51 of the first conductivity type,
A first insulating film (for example, a silicon nitride film) 52 having a film thickness of about 50 nm is formed. A second insulating film (for example, a silicon oxide film) 5 having a thickness of about 600 nm is formed on the first insulating film 52.
3 is formed. After that, the second insulating film 53 is partially etched, for example, at the end of the semiconductor substrate 51 in the column direction (on the element isolation insulating film 71) by using the photo-etching technique and the etching technique.
【００４７】次に、第二の絶縁膜５３上に、次の (ｉ)
及び (ii) 及び (iii)の工程を１回以上（本実施例では
８回）繰り返し実行することによって得られる積層膜を
形成する。Next, the following (i) is formed on the second insulating film 53.
And the laminated film obtained by repeating the steps (ii) and (iii) once or more (eight times in this embodiment) is formed.
【００４８】(ｉ) 膜厚が約５０ｎｍの第三の絶縁膜
（例えばシリコン窒化膜）５４を形成する。 (ii) 膜厚が約４００ｎｍの第四の絶縁膜（例えばシ
リコン酸化膜）５５を形成する。 (iii) 第四の絶縁膜５５を半導体基板の列方向の端部
（素子分離絶縁膜７１上）において部分的にエッチング
する。(I) A third insulating film (for example, a silicon nitride film) 54 having a film thickness of about 50 nm is formed. (ii) A fourth insulating film (for example, a silicon oxide film) 55 having a film thickness of about 400 nm is formed. (iii) The fourth insulating film 55 is partially etched at the column-direction end (on the element isolation insulating film 71) of the semiconductor substrate.
【００４９】なお、上記 (ｉ) 及び (ii) 及び (iii)の
工程を繰り返す回数は、ＮＡＮＤ型ＥＥＰＲＯＭのメモ
リセルの数に相当する。また、図６に示すように、第二
及び第四の絶縁膜５２，５４は、半導体基板の列方向の
端部において階段状となるようにエッチングされる。The number of times the steps (i), (ii) and (iii) are repeated corresponds to the number of memory cells of the NAND type EEPROM. Further, as shown in FIG. 6, the second and fourth insulating films 52 and 54 are etched so as to have a step shape at the end portion in the column direction of the semiconductor substrate.
【００５０】また、この積層膜上に、膜厚が約５０ｎｍ
の第五の絶縁膜（例えばシリコン窒化膜）５６を形成す
る。第五の絶縁膜５６上に、膜厚が約６００ｎｍの第六
の絶縁膜（例えばシリコン酸化膜）５７を形成する。第
六の絶縁膜５７を半導体基板の列方向の端部において部
分的にエッチングする。A film thickness of about 50 nm is formed on this laminated film.
A fifth insulating film (for example, a silicon nitride film) 56 is formed. A sixth insulating film (for example, a silicon oxide film) 57 having a thickness of about 600 nm is formed on the fifth insulating film 56. The sixth insulating film 57 is partially etched at the end of the semiconductor substrate in the column direction.
【００５１】また、第六の絶縁膜５７上に、膜厚が約５
０ｎｍの第七の絶縁膜（例えばシリコン窒化膜）５８を
形成する。第七の絶縁膜５８上に、膜厚が約２００ｎｍ
の第八の絶縁膜（例えばシリコン酸化膜）５９を形成す
る。Further, a film thickness of about 5 is formed on the sixth insulating film 57.
A 0 nm seventh insulating film (for example, a silicon nitride film) 58 is formed. A film thickness of about 200 nm is formed on the seventh insulating film 58.
An eighth insulating film (for example, a silicon oxide film) 59 is formed.
【００５２】このような多層膜において、将来、膜厚が
約６００ｎｍの第二及び第六の絶縁膜５３，５６の部分
に選択ゲ−トが形成され、膜厚が約４００ｎｍの第四の
絶縁膜５５の部分にメモリセルが形成されることにな
る。なお、絶縁膜５３，５６の膜厚ｄ１と絶縁膜５５の
膜厚ｄ２の関係は、ｄ１＞ｄ２となるように設定する。
この理由は、後の工程において説明する。In such a multilayer film, selective gates will be formed in the portions of the second and sixth insulating films 53 and 56 having a film thickness of about 600 nm in the future, and the fourth insulating film having a film thickness of about 400 nm will be formed. A memory cell will be formed in the portion of the film 55. The relationship between the film thickness d1 of the insulating films 53 and 56 and the film thickness d2 of the insulating film 55 is set so that d1> d2.
The reason for this will be described in a later step.
【００５３】次に、図７に示すように、上述の多層膜
に、その表面から半導体基板５１まで達する穴６０を形
成する。この穴６０内には、将来、半導体柱が形成され
るため、当該半導体柱を角柱状にしたい場合には図示す
るような四角形状の穴を形成し、また、当該半導体柱を
円柱状にしたい場合には円形状の穴を形成すればよい。Next, as shown in FIG. 7, a hole 60 reaching the semiconductor substrate 51 from the surface thereof is formed in the above-mentioned multilayer film. Since semiconductor pillars will be formed in the holes 60 in the future, if the semiconductor pillars should be prismatic, a square hole as shown in the figure should be formed, and the semiconductor pillars should be cylindrical. In that case, a circular hole may be formed.
【００５４】次に、図８に示すように、例えば加熱した
リン酸を用いて、第一、第三、第五及び第七の絶縁膜
（シリコン窒化膜）５２，５４，５６，５８を選択的に
エッチングし、当該絶縁膜の部分に後退部６１を形成す
る。この後退部６１の長さＬ１は、エッチング時間等を
適宜調節することにより、例えば約３００ｎｍに設定す
る。Next, as shown in FIG. 8, the first, third, fifth and seventh insulating films (silicon nitride films) 52, 54, 56 and 58 are selected by using, for example, heated phosphoric acid. Of the insulating film to form a recessed portion 61 in the insulating film. The length L1 of the recessed portion 61 is set to, for example, about 300 nm by appropriately adjusting the etching time and the like.
【００５５】次に、図９に示すように、例えば弗化アン
モニウムを用いて、第二、第四、第六及び第八の絶縁膜
（シリコン酸化膜）５３，５５，５７，５９を選択的に
５０ｎｍ程度エッチングし、後退部６１の幅Ｈ１を広げ
る。この後退部６１の幅Ｈ１は、エッチング時間等を適
宜調節することにより、例えば約１５０ｎｍ（絶縁膜５
２、５４、５６又は５８の膜厚（５０ｎｍ）＋エッチン
グ量（５０ｎｍ）×２）に設定する。Next, as shown in FIG. 9, the second, fourth, sixth and eighth insulating films (silicon oxide films) 53, 55, 57 and 59 are selectively formed by using, for example, ammonium fluoride. Then, the width H1 of the recessed portion 61 is widened by etching about 50 nm. The width H1 of the receding portion 61 is, for example, about 150 nm (insulating film 5) by appropriately adjusting the etching time and the like.
The film thickness (50 nm) + etching amount (50 nm) × 2) of 2, 54, 56 or 58 is set.
【００５６】次に、図１０に示すように、全面に、膜厚
が約５０ｎｍの第九の絶縁膜（シリコン窒化膜）６２を
形成する。この第九の絶縁膜６２は、穴６０の内面（後
退部６１を含む）に被着する。また、第九の絶縁膜６２
上に、第二導電型の不純物を含む膜厚が約１５０ｎｍの
第十の絶縁膜（例えばＡｓＳＧ、ＰＳＧなど）６３を形
成する。この第十の絶縁膜６３は、穴６０の内面の第九
の絶縁膜６２上に被着し、後退部６１を完全に埋め込
む。Next, as shown in FIG. 10, a ninth insulating film (silicon nitride film) 62 having a film thickness of about 50 nm is formed on the entire surface. The ninth insulating film 62 is attached to the inner surface of the hole 60 (including the receding portion 61). In addition, the ninth insulating film 62
A tenth insulating film (for example, AsSG, PSG, etc.) 63 having a film thickness of about 150 nm containing an impurity of the second conductivity type is formed thereon. The tenth insulating film 63 is deposited on the ninth insulating film 62 on the inner surface of the hole 60 to completely fill the recessed portion 61.
【００５７】次に、図１１に示すように、等方性エッチ
ングにより、第九及び第十の絶縁膜６２，６３を比較的
に短い時間でエッチングする。その結果、第九及び第十
の絶縁膜６２，６３は、穴６０内の後退部６１のみに残
存する。Next, as shown in FIG. 11, the ninth and tenth insulating films 62 and 63 are etched in a relatively short time by isotropic etching. As a result, the ninth and tenth insulating films 62 and 63 remain only in the recessed portion 61 in the hole 60.
【００５８】なお、この時点において、穴６０の内面近
辺における絶縁膜５３，５６の膜厚（選択ゲ−トの形成
予定部）ｄ３は、約５００ｎｍであり、当該近辺におけ
る絶縁膜５５の膜厚（メモリセルの形成予定部）ｄ４
は、約３００ｎｍである。At this point, the film thickness of the insulating films 53 and 56 near the inner surface of the hole 60 (the portion where the selective gate is to be formed) d3 is about 500 nm, and the film thickness of the insulating film 55 near that region. (Memory cell formation planned portion) d4
Is about 300 nm.
【００５９】次に、図１２に示すように、エピタキシャ
ル成長により、穴６０内に、半導体基板５１から当該穴
６０の上端部まで伸びた第一導電型の半導体柱６４を形
成する。また、熱処理を行い、第十の絶縁膜６３内に含
まれる不純物（例えばＡｓ、Ｐなど）を半導体柱６４へ
拡散させ、当該半導体柱６４の側壁にリング状の複数の
ソ−ス・ドレイン拡散層６５を形成する。Next, as shown in FIG. 12, a semiconductor column 64 of the first conductivity type extending from the semiconductor substrate 51 to the upper end of the hole 60 is formed in the hole 60 by epitaxial growth. Further, heat treatment is performed to diffuse impurities (eg, As, P, etc.) contained in the tenth insulating film 63 into the semiconductor pillar 64, and a plurality of ring-shaped source / drain diffusion layers are formed on the sidewalls of the semiconductor pillar 64. Form the layer 65.
【００６０】次に、図１３に示すように、異方性エッチ
ングにより、多層膜を、列方向にストライプ状となるよ
うにエッチングする。つまり、当該多層膜は、列方向に
存在する半導体柱６４を含むように、当該列方向に延在
するようにして残存させる。Next, as shown in FIG. 13, the multilayer film is etched by anisotropic etching so as to form stripes in the column direction. That is, the multilayer film is left so as to extend in the column direction so as to include the semiconductor pillars 64 existing in the column direction.
【００６１】次に、図１４及び図１５に示すように、弗
化アンモニウムを用いて、当該積層膜のうち第二、第
四、第六及び第八の絶縁膜（シリコン酸化膜）５３，５
５，５７，５９の部分を選択的にエッチング除去する。
その結果、当該積層膜のうち第一、第三、第五及び第七
の絶縁膜（シリコン窒化膜）５２，５４，５６，５８の
部分のみが残存し、これら絶縁膜は、帯状、かつ、列方
向の半導体柱６４に支えられた棚状となる。Next, as shown in FIGS. 14 and 15, using ammonium fluoride, the second, fourth, sixth and eighth insulating films (silicon oxide films) 53, 5 of the laminated film are formed.
The portions 5, 57 and 59 are selectively removed by etching.
As a result, only the first, third, fifth, and seventh insulating films (silicon nitride films) 52, 54, 56, and 58 of the laminated film remain, and these insulating films are strip-shaped and It becomes a shelf shape supported by the semiconductor columns 64 in the column direction.
【００６２】なお、図１５は、図１４においてＢ方向か
ら、半導体基板５１の列方向の端部、即ち積層膜の階段
部分を見た図である。次に、図１６に示すように、熱酸
化法を用いて、半導体柱６４の表面（側壁部を含む）で
あって露出している部分に、メモリセルのトンネル絶縁
膜としての機能を果たす第十一の絶縁膜６６を約１０ｎ
ｍ形成する。FIG. 15 is a view of the end portion of the semiconductor substrate 51 in the column direction, that is, the stepped portion of the laminated film, viewed from the direction B in FIG. Next, as shown in FIG. 16, the exposed portion of the surface (including the side wall portion) of the semiconductor pillar 64 that functions as a tunnel insulating film of the memory cell is formed by using a thermal oxidation method. The eleventh insulating film 66 is set to about 10n.
m.
【００６３】また、第一の導電膜（例えば、導電性のポ
リシリコン膜）６７を約１５０ｎｍ形成する。その結
果、図１６に示すように、半導体柱６４の部分におい
て、第一の導電膜６７は、第三の絶縁膜５４の間（メモ
リセルの形成予定部ＭＣ）の隙間を完全に埋め込むこと
ができるが、第一及び第三の絶縁膜５２，５４の間、並
びに第五及び第七の絶縁膜５６，５８の間（選択ゲ−ト
の形成予定部ＳＧ）の隙間を完全に埋め込むことができ
ない。A first conductive film (for example, a conductive polysilicon film) 67 is formed to a thickness of about 150 nm. As a result, as shown in FIG. 16, in the semiconductor pillar 64 portion, the first conductive film 67 can completely fill the gap between the third insulating films 54 (memory cell formation planned portion MC). However, it is possible to completely fill the gaps between the first and third insulating films 52 and 54 and between the fifth and seventh insulating films 56 and 58 (selective gate formation planned portion SG). Can not.
【００６４】その理由は、選択ゲ−トの形成予定部ＳＧ
の幅ｄ３は、約５００ｎｍであるのに対し、メモリセル
の形成予定部ＭＣの幅ｄ４は、約３００ｎｍであるから
である（図１１参照）。但し、メモリセルの形成予定部
ＭＣでは、半導体柱６４から少し離れると、第三の絶縁
膜５４の間の幅ｄ１が約４００ｎｍとなるため（図５参
照）、第一の導電膜６７は、この部分を完全に埋め込む
ことはできない。The reason for this is that the formation portion SG of the selected gate is to be formed.
The width d3 of the memory cell is about 500 nm, while the width d4 of the portion MC of the memory cell to be formed is about 300 nm (see FIG. 11). However, in the portion MC where the memory cell is to be formed, the width d1 between the third insulating films 54 becomes about 400 nm when it is slightly separated from the semiconductor pillar 64 (see FIG. 5), so that the first conductive film 67 is This part cannot be completely embedded.
【００６５】次に、図１７及び図１８に示すように、等
方性エッチングにより、第一の導電膜６７及び第十一の
絶縁膜６６をエッチングし、当該第一の導電膜６７及び
第十一の絶縁膜６６をメモリセルに形成予定部ＭＣのみ
に残存させる。この残存した第一の導電膜６７は、半導
体柱６４をリング状に取り巻く形となり、フロ−ティン
グゲ−トとしての機能を果たすものとなる。Next, as shown in FIGS. 17 and 18, the first conductive film 67 and the eleventh insulating film 66 are etched by isotropic etching, and the first conductive film 67 and the eleventh conductive film are etched. The one insulating film 66 is left only in the memory cell MC to be formed. The remaining first conductive film 67 surrounds the semiconductor pillar 64 in a ring shape, and functions as a floating gate.
【００６６】また、全面に、ＯＮＯ（ＳｉＯ2 ／Ｓｉ3
Ｎ4 ／ＳｉＯ2 ）絶縁膜６８を約２０ｎｍ形成する。こ
のＯＮＯ絶縁膜６８は、半導体柱６４の側壁（第一の導
電膜６７上を含む）に被着する。さらに、全面に、第二
の導電膜（例えば、導電性のポリシリコン膜）６９を約
４００ｎｍ形成する。On the entire surface, ONO (SiO 2 / Si 3
An N 4 / SiO 2 ) insulating film 68 is formed to a thickness of about 20 nm. The ONO insulating film 68 is deposited on the sidewalls of the semiconductor pillar 64 (including on the first conductive film 67). Further, a second conductive film (for example, a conductive polysilicon film) 69 is formed on the entire surface to a thickness of about 400 nm.
【００６７】その結果、図１７に示すように、半導体柱
６４の部分において、第二の導電膜６９は、第三の絶縁
膜５４の間（第一の導電膜６７上の広い部分）の隙間、
第一及び第三の絶縁膜５２，５４の間、並びに第五及び
第七の絶縁膜５６，５８の間（選択ゲ−トの形成予定部
ＳＧ）の隙間を完全に埋め込む。As a result, as shown in FIG. 17, in the portion of the semiconductor pillar 64, the second conductive film 69 has a gap between the third insulating films 54 (a wide portion on the first conductive film 67). ,
The gaps between the first and third insulating films 52 and 54 and between the fifth and seventh insulating films 56 and 58 (selection gate formation planned portion SG) are completely filled.
【００６８】また、図１８に示すように、半導体柱６４
以外の部分において、第二の導電膜６９は、第三の絶縁
膜５４の間の隙間、第一及び第三の絶縁膜５２，５４の
間の隙間、並びに第五及び第七の絶縁膜５６，５８の間
の隙間をそれぞれ完全に埋め込む。Further, as shown in FIG.
In the portions other than the above, the second conductive film 69 has a gap between the third insulating films 54, a gap between the first and third insulating films 52, 54, and the fifth and seventh insulating films 56. , 58 are completely filled in.
【００６９】次に、図１９及び図２０に示すように、等
方性エッチングにより、第二の導電膜６９を所定量だけ
エッチングする。その結果、第二の導電膜６９は、メモ
リセルの形成予定部ＭＣ及び選択ゲ−トの形成予定部Ｓ
Ｇの双方、並びに半導体柱６４以外の部分（半導体基板
の列方向の端部の階段部分（図２０参照）を含む）にお
ける絶縁膜５２，５４，５６，５８の隙間に残存する。Next, as shown in FIGS. 19 and 20, the second conductive film 69 is etched by a predetermined amount by isotropic etching. As a result, the second conductive film 69 has a planned formation portion MC of the memory cell and a planned formation portion S of the selective gate.
It remains in the gaps between the insulating films 52, 54, 56, and 58 in both of G and the portion other than the semiconductor pillar 64 (including the stepped portion at the end of the semiconductor substrate in the column direction (see FIG. 20)).
【００７０】この残存した第二の導電膜６９は、半導体
基板５１上において列方向に長い帯状となる。素子分離
絶縁膜２５の最上段及び最下段に残存する第二の導電膜
６９は、選択ゲ−トの選択ゲ−ト線としての機能を果た
すものとなる。最上段及び最下段の間の各段に残存する
第二の導電膜６９は、メモリセルのワ−ド線及びコント
ロ−ルゲ−トとしての機能を果たすものとなる。The remaining second conductive film 69 has a strip shape which is long in the column direction on the semiconductor substrate 51. The second conductive film 69 remaining on the uppermost stage and the lowermost stage of the element isolation insulating film 25 functions as a selection gate line of the selection gate. The second conductive film 69 remaining in each stage between the uppermost stage and the lowermost stage serves as a word line and a control gate of the memory cell.
【００７１】また、半導体柱６４の最上部に、最上部の
選択ゲ−トの第二の導電膜（ゲ−ト電極）６９の部分ま
で達する第二導電型のドレイン拡散層７０を形成する。
全面に、半導体柱６４を完全に埋め込む第十二の絶縁膜
７２を形成する。第十二の絶縁膜７２は、その表面が平
坦になるように、十分な膜厚で形成する。In addition, a drain diffusion layer 70 of the second conductivity type is formed on the uppermost part of the semiconductor pillar 64 so as to reach the second conductive film (gate electrode) 69 of the uppermost selection gate.
A twelfth insulating film 72 that completely fills the semiconductor pillar 64 is formed on the entire surface. The twelfth insulating film 72 is formed with a sufficient film thickness so that its surface becomes flat.
【００７２】また、第十二の絶縁膜７２に、ドレイン拡
散層７０に達するコンタクトホ−ルを開け、ビット線を
配線し、かつ、ワ−ド線及び選択ゲ−ト線の端部（階段
部）において当該ワ−ド線及び選択ゲ−ト線に達するコ
ンタクトホ−ルを開け、配線材料７３を形成すれば、図
１〜図４に示すＮＡＮＤ型ＥＥＰＲＯＭのセル構造を得
ることができる。Further, a contact hole reaching the drain diffusion layer 70 is opened in the twelfth insulating film 72, a bit line is wired, and ends of the word line and the select gate line (steps) are formed. 1), the cell structure of the NAND type EEPROM shown in FIGS. 1 to 4 can be obtained by opening a contact hole reaching the word line and the select gate line and forming the wiring material 73.
【００７３】[0073]
【発明の効果】以上、説明したように、本発明の半導体
記憶装置及びその製造方法によれば、次のような効果を
奏する。従来、平面的にメモリセルが形成されていたの
に対し、半導体基板上に半導体柱を形成し、この半導体
柱の側壁に、即ち立体的にメモリセルを形成している。
従って、従来に比べ、格段に、集積度の向上（単位面積
当りのセル数の増大）を図ることができ、写真蝕刻技術
の改善にたよることなく、次世代におけるＬＳＩに貢献
することができる。As described above, according to the semiconductor memory device and the method of manufacturing the same of the present invention, the following effects can be obtained. Conventionally, memory cells are formed in a plane, whereas semiconductor pillars are formed on a semiconductor substrate, and the memory cells are formed on the side walls of the semiconductor pillars, that is, three-dimensionally.
Therefore, it is possible to significantly improve the degree of integration (increase in the number of cells per unit area) as compared with the related art, and to contribute to the next-generation LSI without relying on the improvement of the photo-etching technique. .
【００７４】また、当該セル構造を提供するにあたって
は、半導体柱を利用することにより、自己整合的な工程
を達成することができるため、簡単に、上記構造を提供
できる。しかも、製造工程中、等方性エッチングが主と
して用いられるため、加工も行い易くなる。In providing the cell structure, the semiconductor pillar can be used to achieve a self-aligned process, so that the above structure can be easily provided. Moreover, since isotropic etching is mainly used during the manufacturing process, processing is easy.
【図１】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲＯ
Ｍのセル構造を示す平面図、FIG. 1 is a NAND-type EEPROM according to an embodiment of the present invention.
A plan view showing the cell structure of M,
【図２】図１のIII −III ´線に沿う断面図、2 is a cross-sectional view taken along the line III-III ′ of FIG.
【図３】図１のIV−IV´線に沿う断面図、FIG. 3 is a sectional view taken along line IV-IV ′ in FIG.
【図４】図１のワ−ド線部分のみを取り出して示す図、FIG. 4 is a diagram showing only the word line portion of FIG.
【図５】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲＯ
Ｍのセル構造の製造方法を示す斜視図、FIG. 5 is a NAND-type EEPROM which is an embodiment of the present invention.
A perspective view showing a manufacturing method of the cell structure of M,
【図６】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲＯ
Ｍのセル構造の製造方法を示す断面図、FIG. 6 is a NAND-type EEPRO which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of M,
【図７】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲＯ
Ｍのセル構造の製造方法を示す斜視図、FIG. 7 is a NAND-type EEPROM which is an embodiment of the present invention.
A perspective view showing a manufacturing method of the cell structure of M,
【図８】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲＯ
Ｍのセル構造の製造方法を示す断面図、FIG. 8 is a NAND-type EEPROM that is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of M,
【図９】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲＯ
Ｍのセル構造の製造方法を示す断面図、FIG. 9 is a NAND-type EEPRO which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of M,
【図１０】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 10 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１１】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 11 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１２】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 12 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１３】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す斜視図、FIG. 13 is a NAND-type EEPR which is an embodiment of the present invention.
A perspective view showing a method for manufacturing an OM cell structure;
【図１４】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す斜視図、FIG. 14 is a NAND-type EEPR which is an embodiment of the present invention.
A perspective view showing a method for manufacturing an OM cell structure;
【図１５】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 15 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１６】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 16 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１７】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 17 is a NAND-type EEPR that is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１８】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 18 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図１９】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 19 is a NAND-type EEPR which is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図２０】本発明の一実施例であるＮＡＮＤ型ＥＥＰＲ
ＯＭのセル構造の製造方法を示す断面図、FIG. 20 is a NAND-type EEPR that is an embodiment of the present invention.
Sectional drawing which shows the manufacturing method of the cell structure of OM,
【図２１】従来のＮＡＮＤ型ＥＥＰＲＯＭのセル構造を
示す図。FIG. 21 is a diagram showing a cell structure of a conventional NAND type EEPROM.
１１，３１，５１ …半導体基板、 １２ …ウエル、 １３，５２，７１ …フィ−ルド絶縁膜、 １４．３８ …トンネル絶縁膜、 １５，３９ …ポリシリコン電極（フロ−
ティングゲ−ト）、 １６，３４，４０，４６，４９，５２〜５９，６２，６
３，６６，７２…絶縁膜、 １７，４１ …ポリシリコン電極（コント
ロ−ルゲ−ト）、 １８，４３，６５ …ソ−ス・ドレイン拡散層、 １９ …ビット線、 ２５ …素子分離絶縁膜、 ３２，６４ …半導体柱、 ３３−１，３３−２ …選択ゲ−ト、 ３５ …ポリシリコン電極（選択ゲ
−ト）、 ３６，４２ …コンタクト部、 ３７−１〜３７−９ …メモリセル、 ４４，５０ …ソ−ス拡散層、 ４５，７０ …ドレイン拡散層、 ４７，５０ …コンタクトホ−ル、 ４８ …ビット線、 ５１，７３ …配線材料、 ６０ …穴、 ６１ …後退部、 ６７，６９ …導電膜 ６８ …ＯＮＯ絶縁膜。11, 31, 51 ... Semiconductor substrate, 12 ... Well, 13, 52, 71 ... Field insulating film, 14.38 ... Tunnel insulating film, 15, 39 ... Polysilicon electrode (flow)
Ting gate), 16, 34, 40, 46, 49, 52 to 59, 62, 6
3, 66, 72 ... Insulating film, 17, 41 ... Polysilicon electrode (control gate), 18, 43, 65 ... Source / drain diffusion layer, 19 ... Bit line, 25 ... Element isolation insulating film, 32, 64 ... Semiconductor pillar, 33-1, 33-2 ... Selection gate, 35 ... Polysilicon electrode (selection gate), 36, 42 ... Contact part, 37-1 to 37-9 ... Memory cell, 44, 50 ... Source diffusion layer, 45, 70 ... Drain diffusion layer, 47, 50 ... Contact hole, 48 ... Bit line, 51, 73 ... Wiring material, 60 ... Hole, 61 ... Recessed portion, 67, 69 ... Conductive film 68 ... ONO insulating film.
Claims (13)
される半導体柱と、前記半導体柱に複数段を形成する素
子分離絶縁膜と、前記素子分離絶縁膜の間であって、前
記複数段のうち最上段と最下段にそれぞれ形成される選
択ゲ−トと、前記最上段と最下段の間の各段にそれぞれ
形成されるメモリセルとを具備することを特徴とする半
導体記憶装置。1. A semiconductor substrate, a semiconductor pillar formed on the semiconductor substrate, an element isolation insulating film forming a plurality of steps on the semiconductor pillar, and between the element isolation insulating film, wherein the plurality of steps are provided. A semiconductor memory device, comprising: a selection gate formed in each of an uppermost stage and a lowermost stage, and a memory cell formed in each stage between the uppermost stage and the lowermost stage.
て、前記選択ゲ−トは、前記半導体柱の側壁に第一の絶
縁膜を介して形成される第一の導電膜を有し、前記メモ
リセルは、前記半導体柱の側壁にトンネル絶縁膜を介し
て形成され、フロ−ティングゲ−トとして機能する第二
の導電膜、及び前記第二の導電膜上に第二の絶縁膜を介
して形成され、コントロ−ルゲ−トとして機能する第三
の導電膜を有することを特徴とする半導体記憶装置。2. The semiconductor memory device according to claim 1, wherein the selection gate has a first conductive film formed on a sidewall of the semiconductor pillar through a first insulating film, The memory cell is formed on the sidewall of the semiconductor pillar via a tunnel insulating film, and functions as a floating gate, and a second insulating film is formed on the second conductive film via a second insulating film. A semiconductor memory device having a third conductive film formed and functioning as a control gate.
て、前記フロ−ティングゲ−トとして機能する第二の導
電膜は、各段において、前記半導体柱を取り巻くリング
状に形成されていることを特徴とする半導体記憶装置。3. The semiconductor memory device according to claim 2, wherein the second conductive film functioning as the floating gate is formed in a ring shape surrounding the semiconductor pillar in each stage. A characteristic semiconductor memory device.
て、前記素子分離絶縁膜の間であって、前記複数段のう
ち最上段と最下段の高さは、その最上段と最下段の間の
各段の高さよりも高くなるように構成され、その結果、
前記選択ゲ−トのゲ−ト長は、前記メモリセルのゲ−ト
長よりも長くなっていることを特徴とする半導体記憶装
置。4. The semiconductor memory device according to claim 1, wherein the height between the element isolation insulating film and the uppermost stage and the lowermost stage among the plurality of stages is between the uppermost stage and the lowermost stage. Is configured to be higher than the height of each step of the
A semiconductor memory device characterized in that the gate length of the select gate is longer than the gate length of the memory cell.
て、前記半導体柱の側壁であって、前記複数段を構成す
る前記素子分離絶縁膜の各段に隣接してリング状に形成
されるソ−ス・ドレイン拡散層と、前記半導体基板中に
形成され、前記最下段の選択ゲ−トのソ−ス・ドレイン
拡散層に接続されるソ−ス拡散層と、前記半導体柱の最
上部に形成され、前記最上段の選択ゲ−トのソ−ス・ド
レイン拡散層に接続されるドレイン拡散層とを有するこ
とを特徴とする半導体記憶装置。5. The semiconductor memory device according to claim 1, wherein a sidewall of the semiconductor pillar is formed in a ring shape adjacent to each step of the element isolation insulating film forming the plurality of steps. -A source / drain diffusion layer, a source diffusion layer formed in the semiconductor substrate and connected to the source / drain diffusion layer of the lowermost selection gate, and on the top of the semiconductor pillar. And a drain diffusion layer formed and connected to the source / drain diffusion layer of the uppermost selection gate.
て、前記半導体柱は、前記半導体基板上に行列状に複数
形成され、行方向の半導体柱における当該ドレイン拡散
層に共通に接続するビット線を有することを特徴とする
半導体記憶装置。6. The semiconductor memory device according to claim 5, wherein a plurality of the semiconductor pillars are formed in a matrix on the semiconductor substrate and are commonly connected to the drain diffusion layers of the semiconductor pillars in the row direction. A semiconductor memory device comprising:
て、前記半導体柱は、前記半導体基板上に行列状に複数
形成され、前記複数段を構成する素子分離絶縁膜の各段
は、列方向の半導体柱に共通して棚状に形成され、前記
選択ゲ−トの第一の導電膜及び前記コントロ−ルゲ−ト
として機能する第三の導電膜は、それぞれ列方向の半導
体柱に共通し、かつ、各段において、それぞれ列方向に
帯状に形成されていることを特徴とする半導体記憶装
置。7. The semiconductor memory device according to claim 1, wherein a plurality of the semiconductor pillars are formed in a matrix on the semiconductor substrate, and each step of the element isolation insulating films forming the plurality of steps is in a column direction. The first conductive film of the select gate and the third conductive film functioning as the control gate, which are formed in a shelf shape in common with the semiconductor pillars, are common to the semiconductor pillars in the column direction. The semiconductor memory device is characterized in that each stage is formed in a strip shape in the column direction.
て、前記選択ゲ−トの第一の導電膜及び前記コントロ−
ルゲ−トとして機能する第三の導電膜は、それぞれ列方
向の端部において階段状に形成され、その階段状の部分
にコンタクト部が設けられていることを特徴とする半導
体記憶装置。8. The semiconductor memory device according to claim 7, wherein the first conductive film of the selection gate and the control gate are provided.
A semiconductor memory device characterized in that the third conductive film functioning as a rugate is formed stepwise at each end in the column direction, and a contact portion is provided at the stepwise portion.
前記第一の絶縁膜上に第二の絶縁膜を形成する第一の工
程と、 前記第二の絶縁膜上に、少なくとも１回以上、以下の
(i)，(ii)の工程、即ち(i) 第三の絶縁膜を形成する工
程、及び(ii) 前記第三の絶縁膜上に第四の絶縁膜を形
成する工程を繰り返し実行することにより得られる積層
膜を形成する第二の工程と、 前記積層膜上に第五の絶縁膜を形成し、前記第五の絶縁
膜上に第六の絶縁膜を形成する第三の工程と、 前記第六の絶縁膜上に第七の絶縁膜をを形成し、前記第
七の絶縁膜上に第八の絶縁膜を形成する第四の工程と、 前記第八の絶縁膜の表面から前記半導体基板まで達する
行列状の複数の穴を形成する第五の工程と、 選択エピタキシャル成長法により、各々の穴内に、半導
体を成長させ、行列状の半導体柱を形成する第六の工程
と、 前記第一乃至第八の絶縁膜からなる多層膜をエッチング
し、半導体柱の各列の間であって、列方向に伸びるスト
ライプ状の溝を形成する第七の工程と、 前記第二、第四、第六及び第八の絶縁膜を選択的にエッ
チングすることにより、残存した前記第一、第三、第五
及び第七の絶縁膜であって、列方向の半導体柱に支えら
れた複数段の棚状のものを形成する第八の工程と、 前記複数段のうち、前記第一の絶縁膜と前記第三の絶縁
膜の間の最下段及び前記第五の絶縁膜と前記第七の絶縁
膜の間の最上段に選択ゲ−トを形成し、前記最下段と最
上段の間の各段にメモリセルを形成する第九の工程とを
具備することを特徴とする半導体記憶装置の製造方法。9. A first insulating film is formed on a semiconductor substrate,
A first step of forming a second insulating film on the first insulating film, and at least once or more on the second insulating film,
Repeating steps (i) and (ii), that is, (i) forming a third insulating film, and (ii) forming a fourth insulating film on the third insulating film. A second step of forming a laminated film obtained by, forming a fifth insulating film on the laminated film, a third step of forming a sixth insulating film on the fifth insulating film, Forming a seventh insulating film on the sixth insulating film, a fourth step of forming an eighth insulating film on the seventh insulating film, and from the surface of the eighth insulating film A fifth step of forming a plurality of matrix-shaped holes reaching the semiconductor substrate, and a sixth step of growing a semiconductor in each of the holes by a selective epitaxial growth method to form a matrix-shaped semiconductor pillar, A multilayer film consisting of the first to eighth insulating films is etched to form stripes between columns of semiconductor pillars and extending in the column direction. A seventh step of forming a groove, and the remaining first, third, fifth and seventh insulations by selectively etching the second, fourth, sixth and eighth insulation films. An eighth step of forming a film, which is a shelf-shaped product of a plurality of stages supported by semiconductor columns in a column direction, and, of the plurality of stages, of the first insulating film and the third insulating film. A select gate is formed in the lowermost stage between and the uppermost stage between the fifth insulating film and the seventh insulating film, and memory cells are formed in each stage between the lowermost stage and the uppermost stage. 9. A method of manufacturing a semiconductor memory device, comprising the steps of:
造方法において、 前記第一の工程は、前記第二の絶縁膜の列方向の端部を
部分的にエッチングする工程を有し、 前記第二の工程は、少なくとも１回以上、前記 (i)，(i
i)の工程及び (iii)前記第四の絶縁膜の列方向の端部を
部分的にエッチングする工程を繰り返し実行するもので
あり、 前記第三の工程は、前記第六の絶縁膜の列方向の端部を
部分的にエッチングする工程を有し、 前記第四の工程は、前記第八の絶縁膜の列方向の端部を
部分的にエッチングする工程を有ており、 その結果、前記列方向の端部では、前記第二、第四、第
六及び第八の絶縁膜は、階段状に形成されることを特徴
とする半導体記憶装置の製造方法。10. The method of manufacturing a semiconductor memory device according to claim 9, wherein the first step includes a step of partially etching an end portion of the second insulating film in a column direction, In the second step, at least once, the above (i), (i
The step i) and (iii) the step of partially etching the end portion of the fourth insulating film in the column direction are repeatedly performed, and the third step is the row of the sixth insulating film. Direction partly etching the end part, the fourth step has a step of partially etching the column direction end part of the eighth insulating film, as a result, The method of manufacturing a semiconductor memory device, wherein the second, fourth, sixth and eighth insulating films are formed in a step shape at the ends in the column direction.
造方法において、 前記第五の工程と前記第六の工程の間に、以下のａ〜ｅ
の工程、即ち ａ． 等方性エッチングにより、各穴内の前記第一、第
三、第五及び第七の絶縁膜を所定量だけエッチングし、
後退部を形成する工程と、 ｂ． 等方性エッチングにより、各穴内の前記第二、第
四、第六及び第八の絶縁膜を所定量だけエッチングし、
前記後退部を拡張する工程と、 ｃ． 前記後退部を含む前記各穴の側壁に第九の絶縁膜
を形成する工程と、 ｄ． 前記第九の絶縁膜上に、前記後退部を埋め込み、
不純物を含む第十の絶縁膜を形成する工程と、 ｅ． 等方性エッチングにより、前記第九及び第十の絶
縁膜を前記各穴内の後退部にのみ残存させる工程を具備
し、 前記第六の工程と前記第七の工程の間に、熱処理を行
い、前記第十の絶縁膜中の不純物を当該半導体柱の側壁
に拡散させ、各半導体柱の側壁にリング状のソ−ス・ド
レイン領域を形成する工程を具備することを特徴とする
半導体記憶装置の製造方法。11. The method of manufacturing a semiconductor memory device according to claim 9, wherein the following a to e are provided between the fifth step and the sixth step.
Process of step a. By isotropic etching, the first, third, fifth and seventh insulating film in each hole is etched by a predetermined amount,
Forming a retreat, b. By isotropic etching, the second, fourth, sixth and eighth insulating film in each hole is etched by a predetermined amount,
Expanding said recess, c. Forming a ninth insulating film on the side wall of each hole including the recessed portion, and d. Embedding the recessed portion on the ninth insulating film,
Forming a tenth insulating film containing impurities; e. Comprises a step of leaving the ninth and tenth insulating films only in the recessed portion in each hole by isotropic etching, and performing heat treatment between the sixth step and the seventh step, A semiconductor memory device comprising: a step of diffusing impurities in the tenth insulating film to a sidewall of the semiconductor pillar to form a ring-shaped source / drain region on the sidewall of each semiconductor pillar. Production method.
造方法において、 前記第二及び第六の絶縁膜の膜厚は、前記第四の絶縁膜
の膜厚よりも大きく設定されており、 前記第九の工程は、 各半導体柱の側壁に第十一の絶縁膜を形成する工程と、 全面に、第一の導電膜を形成する工程と、 等方性エッチングにより、前記第十一の絶縁膜及び前記
第一の導電膜を所定量だけエッチングし、前記第十一の
絶縁膜及び前記第一の導電膜を前記最下段と最上段を除
く各段にのみ残存させ、前記最下段と最上段を除く各段
にのみ当該半導体柱を取り巻くリング状のフロ−ティン
グゲ−トを形成する工程と、 全面に、第十二の絶縁膜を形成する工程と、 全面に、第二の導電膜を形成する工程と、 等方性エッチングにより、前記第二の導電膜を所定量だ
けエッチングし、当該第二の導電膜を、前記複数段を構
成する素子分離絶縁膜の各段に残存させ、前記最下段と
最上段に列方向に伸びる帯状の選択ゲ−ト線を形成し、
前記最下段と最上段の間の各段に列方向に伸びる帯状の
ワ−ド線を形成する工程とを具備することを特徴とする
半導体記憶装置の製造方法。12. The method of manufacturing a semiconductor memory device according to claim 9, wherein the film thicknesses of the second and sixth insulating films are set to be larger than the film thickness of the fourth insulating film, The ninth step is a step of forming an eleventh insulating film on a sidewall of each semiconductor pillar, a step of forming a first conductive film on the entire surface, and a step of forming the eleventh insulating film by isotropic etching. The insulating film and the first conductive film are etched by a predetermined amount, and the eleventh insulating film and the first conductive film are left only in each stage except the lowermost stage and the uppermost stage. A step of forming a ring-shaped floating gate surrounding the semiconductor pillar only in each step except the uppermost step, a step of forming a twelfth insulating film on the entire surface, and a second conductive film on the entire surface. And a isotropic etching process to form a predetermined amount of the second conductive film. And etching, the second conductive film, wherein the plurality of stages is left to each stage of the device isolation insulating film constituting said strip-like select gates extending in the column direction in the bottom and top - to form the door line,
And a step of forming strip-shaped word lines extending in the column direction on each stage between the lowermost stage and the uppermost stage.
造方法において、 前記第一の工程の前に、前記半導体基板中にソ−ス領域
を形成する工程を具備し、 前記第九の工程の後に、各半導体柱の最上部にドレイン
領域を形成する工程と、行方向の半導体柱のドレイン拡
散層に接続するビット線を形成する工程とを具備するこ
とを特徴とする半導体記憶装置の製造方法。13. The method of manufacturing a semiconductor memory device according to claim 9, further comprising a step of forming a source region in the semiconductor substrate before the first step, and the ninth step. After that, a step of forming a drain region on the top of each semiconductor pillar, and a step of forming a bit line connected to the drain diffusion layer of the semiconductor pillar in the row direction are manufactured. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12695893A JP3651689B2 (en) | 1993-05-28 | 1993-05-28 | NAND type nonvolatile semiconductor memory device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12695893A JP3651689B2 (en) | 1993-05-28 | 1993-05-28 | NAND type nonvolatile semiconductor memory device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06338602A true JPH06338602A (en) | 1994-12-06 |
| JP3651689B2 JP3651689B2 (en) | 2005-05-25 |
Family
ID=14948112
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12695893A Expired - Lifetime JP3651689B2 (en) | 1993-05-28 | 1993-05-28 | NAND type nonvolatile semiconductor memory device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3651689B2 (en) |
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