JPH06334628A - Spread spectrum communication method - Google Patents

Abstract

PURPOSE:To simplify a circuit, and to attain a low cost by unnecessitating a differential conversion circuit on the transmitter side, and the delay circuit of a PN code in a carrier frequency band on the receiver side in a conventional delay detection modulation system. CONSTITUTION:At the transmission side, the PN signal from a PN code generator 11 is selectively multiplied by a carrier frequency signal according to the polarity of source binary data to be transmitted, and outputted. At the reception side, when the PN code is present in a spread spectrum signal, a matched pulse is generated in each one cycle of the PN code by a correlator 24. A flip flop circuit 29 which takes a set signal priority over a reset signal uses the matched pulse as the set signal, and uses the matched pulse delayed only in one cycle of the PN code as the reset signal. The output of the flip flop circuit 29 is used as modulated data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication method using direct sequence modulation.

[0002]

2. Description of the Related Art Conventionally, in spread spectrum communication by direct sequence modulation, a differential detection system has been used as a system that does not require a PN code (pseudo noise sequence) synchronizer on the receiving side. In this method, the transmission side differentially converts the transmission data and then multiplies it with the PN code to obtain a spread spectrum signal. The reception side spreads the received spread spectrum signal and the received spread spectrum signal in one cycle of the PN code. The data signal is demodulated by performing the multiplication with the signal delayed by the amount and utilizing the low-frequency component of the multiplied signal.

FIG. 4 is a block diagram of a conventional differential detection system.
5 shows the signal waveform of each part. FIG. 4A shows a block diagram on the transmission side. In the figure, source binary data input from the signal line 500 is input to the exclusive OR gate 50. The other input of the exclusive OR gate 50 is input from the signal line 501, and the exclusive OR gate 50
An exclusive OR operation is performed at, and a so-called precoded signal is output to the signal line 502. Signal line 5
The signal 02 is input to the delay circuit 51 and the source binary data 1
The signal is delayed by a bit and is output to the signal line 501.

The clock generation circuit 54 outputs a clock signal for generating a modulation PN code to the signal line 504. P
The N code generator 53 generates a PN code for modulation by the clock signal from the signal line 504 and outputs it to the signal line 503. The multiplier 52 multiplies the signal from the signal line 502 and the signal from the signal line 503 and outputs the product to the signal line 505.

FIG. 4B shows a block diagram on the receiving side.
In the figure, the received spread spectrum signal from the signal line 507 is input to the delay circuit 55 and the multiplier 56. In the delay circuit 55, the received spread spectrum signal is delayed by one period of the PN code, that is, one bit of the source binary data and output to the signal line 508. The spread spectrum signal received from the signal line 507 and the delayed signal on the signal line 508 are
The multiplication operation is performed by the multiplier 56, and the result is output to the signal line 509. The signal on the signal line 509 is a low-pass filter 57.
Thus, the low frequency component is extracted and output to the signal line 510 as demodulated data.

FIG. 5 shows the signal waveform of each part. Figure 5 (a)
Shows the waveform of the source binary data of the signal line 500, and FIG. 5B shows the precoded signal waveform of the signal line 502.
FIG. 5C shows a modulation waveform of the signal line 505 obtained by performing spread spectrum modulation on the signal of the signal line 502 with a PN code. The received spread spectrum signal on the signal line 507 has the signal waveform of FIG. FIG. 5D shows a signal waveform of the signal line 508 in which the received spread spectrum signal is delayed by one period of the PN code. The signal of the signal line 507 and the signal of the delayed signal line 508 are multiplied by the multiplier 56. Multiply and signal line 509
To the low pass filter 57. Figure 5
(E) shows demodulated data of the signal line 510.

[0007]

In the above-mentioned conventional differential detection system, the receiving side has P in the carrier frequency band.
A delay time of one N code cycle is required. A system that uses a SAW delay line to obtain this delay time and a carrier frequency signal are synchronized and converted into a baseband signal,
There is a method of digitally performing the baseband signal using a clock signal, but in both methods, the circuit configuration becomes complicated and the cost becomes high.

[0008]

Therefore, in the spread spectrum communication method of the present invention, in the spread spectrum communication by the direct spread modulation, the PN code is selectively selected on the transmitting side according to the polarity of the source binary data to be transmitted. The carrier-frequency signal is multiplied by the selectively output PN code to output a spread spectrum signal. At the receiving side, the spread spectrum signal is selectively output in the received spread spectrum signal. While the PN code is present, a pulse is generated for each cycle of the PN code, and the pulse and the pulse obtained by delaying the pulse by one cycle of the PN code are each used to output demodulated data. 1 and a second signal, the first signal has a state in which data to be demodulated is activated in priority to the second signal, and the second signal is
The demodulated data is obtained by dropping the data to be demodulated in the activated state.

[0009]

According to the above method, the transmitting side turns on / off the PN code from the PN code generator according to the positive / negative polarities of the source binary data, and turns on / off the PN code and the carrier frequency. The signal is multiplied and output. On the receiving side, while the PN code exists from the intermediate frequency spread spectrum signal obtained from the received spread spectrum signal,
A pulse is generated for each cycle of the PN code. Then, this pulse is used as the first signal, and the pulse obtained by delaying the pulse by one cycle of the PN code is used as the second signal to create demodulated data.

For example, when the first signal is generated, the second signal
Irrespective of the generation of the signal, the demodulated data to be output is turned on with priority over the second signal. When only the second signal is generated, the demodulated data to be output which was turned on by the first signal is turned off.

[0011]

EXAMPLES Specific examples will be described in detail below. Figure 1
FIG. 3 is a block diagram showing an example of a transmitting side that implements a spectrum method that implements the present invention. In FIG. 1A, the source binary data input from the signal line 100 is input to the selection circuit 10. The other input of the selection circuit 10 is a PN code for modulation. Clock generation circuit 12
Then, the clock signal for generating the modulation PN code is supplied to the signal line 1.
Output to 02. The PN code generator 11 has a signal line 102.
The PN code for modulation is generated by the clock signal from and output to the signal line 101. The selection circuit 10 creates a spread spectrum signal in which the PN code from the signal line 101 is turned on and off according to the polarity of the source binary data signal from the signal line 100.

The spread spectrum signal from the signal line 103 is a PN code that is turned on and off according to the polarity of the source binary data signal, and is the carrier frequency signal from the carrier frequency signal generation circuit 14 in the multiplication circuit 13. It is multiplied. The product signal on the signal line 105 is band-limited by the bandpass filter 15, and a transmission spread spectrum signal is output to the signal line 106.

FIG. 1B shows a circuit example of the selection circuit 10 shown in FIG. In FIG. 1B, when the source binary data signal from the signal line 100 is at H (high) level, the signal line 10
The modulation PN code from 1 is output to the signal line 109, and when the source binary data signal is at L (low) level, the modulation PN code is not output to the signal line 109 and is fixed at L level. The PN code turned on / off by the source binary data signal from the signal line 109 is latched by the D flip-flop 19 by the clock signal from the signal line 102 and output to the signal line 103 as a spread spectrum signal.

FIG. 2 is a block diagram showing an embodiment of the receiving side for implementing the present invention. In FIG. 2A, the received spread spectrum signal input from the signal line 200 is input to the multiplier 20. The other input of the multiplier 20 is input from the signal line 201, the local signal from the local oscillation frequency signal generator 21 and the received spread spectrum signal from the signal line 200 are multiplied, and the signal line 202 is fed with the intermediate frequency spectrum. It is output as a spread signal.

The intermediate frequency spread spectrum signal from the signal line 202 is band-limited by the band pass filter 22,
It is output to the signal line 203. The intermediate frequency spread spectrum signal from the signal line 203 is sent to the next SAW in the amplifier circuit 23.
It is amplified to the optimum input level of the correlator 24. The SAW correlator 24 outputs a matched pulse signal to the signal line 205 every PN code period while the PN code is present.

Since the matched pulse signal includes an intermediate frequency component, the square wave detection is performed by the double balanced modulator 25, the low frequency component is extracted by the low pass filter 26, and the low frequency component is output to the signal line 207. The square-law detection operation and band limitation of the low-pass filter can improve the signal-to-noise ratio of the matched pulse signal.
Further, the receiving circuit can be realized by using a digital correlator instead of the SAW correlator which is an analog correlator.

The matched pulse signal from the signal line 207 is pulse shaped by the matched pulse shaping circuit 27,
The signal is output to the signal line 208 as a set signal of the flip-flop circuit 29. The pulse signal on the signal line 208 is also input to the delay circuit 28, delayed by one cycle of the PN code in the delay circuit 28, and output to the signal line 209 as a reset signal for the flip-flop circuit 29.

The flip-flop circuit 29 is a set-reset flip-flop circuit with set priority.
Information data is demodulated by the set signal from the signal line 208 and the reset signal from the signal line 209 to obtain the signal line 211.
The demodulated data is output to.

FIG. 2B shows a circuit example of the set priority flip-flop circuit 29. Although a set signal is input from the signal line 208 and a reset signal is input from the signal line 209, the reset signal is valid only when the set signal is at the L level, and only when the reset pulse is input at that time. , Effective reset to the signal line 213 as a negative pulse
It is output as a pulse. The set pulse signal is effective when the reset pulse signal is at H level or L level, and when the set pulse signal is input, the signal line 212 is input.
Output as a negative pulse.

The set pulse signal on the signal line 212 and the reset pulse signal on the signal line 213 are input to the D flip-flops 35 and 36 and synchronized with the clock signal from the clock signal generator 30. The set pulse signal from the signal line 214 and the reset pulse signal from the signal line 215 are input to the set / reset flip-flop circuit including the logic gate elements 37 and 38, and the demodulated data signal is output to the signal line 216. And is output to the signal line 211 through the D flip-flop 39. Figure 3
The signal waveforms of the respective parts in FIGS. 1 and 2 are shown in FIG. FIG. 3A shows a signal form of the spread spectrum signal in which the PN code of the signal line 103 in the block diagram on the transmitting side of FIG. 1 is turned on and off by the source binary data signal. FIG. 3B shows FIG.
3 shows a signal waveform of the signal line 205 in the block diagram on the receiving side of FIG. The matched pulse signal on the signal line 205, which is the output of the SAW correlator, has phase information at the intermediate frequency. FIG. 3C shows a signal line 20 which is a square detection output.
6 shows a signal waveform of a signal line 208 obtained by waveform-shaping the signal of No. 6 and this pulse signal becomes a set signal of the set priority flip-flop circuit. FIG. 3D shows a signal waveform of the signal line 209, which serves as a reset signal of the set priority flip-flop circuit. FIG. 3E shows a signal waveform of the signal line 211, that is, a demodulated data signal.

[0021]

As described above, according to the spread spectrum communication method of the present invention, in the conventional differential detection demodulation system, the transmission side does not need the differential conversion circuit by using a simple selection circuit, and the reception side. However, by using the delay circuit for one cycle of the PN code of the matched pulse, the delay circuit for one cycle of the PN code in the carrier frequency band becomes unnecessary, the circuit configuration can be simplified, and the cost reduction effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitting side in an embodiment of a spread spectrum communication method of the present invention.

FIG. 2 is a block diagram of a receiving side in the embodiment.

FIG. 3 is a signal waveform diagram of each part on the transmission / reception side in the embodiment.

FIG. 4 is a block diagram of a conventional spread spectrum communication method.

FIG. 5 is a signal waveform diagram of each part of the same method.

[Explanation of symbols]

10 selection circuit 11,53 PN code generator 12, 30, 54 clock signal generation circuit 13, 20, 52, 56 multiplier 14 carrier frequency signal generator 15, 22 bandpass filter 16, 17, 31, 32, 34, 37, 38 and
Gate element 18, 33 OR gate element 19, 35, 36, 39 D type flip-flop 21 Local oscillation frequency signal generator 23 Amplifier circuit 24 SAW correlator 25 Double balanced modulator 26, 57 Low-pass filter 27 Matched・ Pulse shaping circuit 28 Matched pulse delay circuit 29 Set priority flip-flop circuit 50 Exclusive OR gate element 51, 55 Delay circuit

Claims (1)

[Claims] 1. In spread spectrum communication by direct sequence modulation, a PN code is selectively output on the transmitting side according to the polarity of source binary data to be transmitted, and the PN code is selectively output. , Multiplying the carrier frequency signal,
Send a spread spectrum signal, and on the receiving side, in the received spread spectrum signal,
While the selectively output PN code is present, PN
A first pulse for generating demodulated data by generating a pulse for each cycle of a code and delaying the pulse by one cycle of the PN code
And a second signal, the first signal is prioritized over the second signal, and the data to be demodulated is in a raised state, and the second signal is the demodulated signal in the raised state. Spread spectrum communication method in which the power data is dropped and demodulated data is obtained.