JPH0633450Y2 - Driving circuit for ECD anti-glare mirror - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a drive circuit for an anti-glare mirror, and in particular, it detects the terminal voltage of the electrochromic device (ECD) on the color fading / erasing side
ECD that controls the color density according to the terminal voltage on the color side
The present invention relates to a drive circuit for an antiglare mirror.

[Prior Art] While driving a night car, when illuminated by the headlight of the following vehicle from behind, the rearview mirror reflects the light of the following vehicle's headlight,
Since it causes the driver to be dazzled and hinders complete driving, the image of high incident light that causes dazzling is changed to an image of low reflected light. For that purpose, the lever attached to the rearview mirror is manually operated to mechanically switch the reflection angle, or a circuit for automatically switching the reflection angle when light dazzlingly enters is operated. In such a method of changing the reflection angle of the room mirror, the mirror must be movably supported and the reflection angle must be switched by a lever or a solenoid, so that the structure is complicated and switching from high reflection light to low reflection light is required. Cause a delay. Therefore, recently, by using a liquid crystal panel in which liquid crystal is sealed between glass substrates provided with transparent electrodes, the voltage applied to the electrodes of the liquid crystal panel is changed to change the light transmittance of the panel. Those that obtain an antiglare effect have been proposed.

[Problems to be Solved by the Invention] However, the mirror using the above liquid crystal panel has a variation in the transmittance of the liquid crystal panel and changes variously due to the influence of ambient temperature, aging, etc. It is difficult to maintain the transmittance at the set value even when applied. The color of the mirror of the liquid crystal panel varies depending on the viewing angle, resulting in a double image with poor visibility and insufficient weather resistance.
Therefore, it has been attempted to use the ECD panel as an antiglare mirror. Unlike LCDs, ECDs have good visibility, excellent contrast and light resistance, and also have a memory function, but when ECD panels are used as mirrors, no drive circuit has been developed that matches the usage conditions. It was

An object of the present invention is to provide an ECD antiglare mirror drive circuit that allows a driver to switch the reflectance of the antiglare mirror by a switch operation without tilting the antiglare mirror.

[Means for Solving the Problems] In order to achieve the above object, the present invention has a circuit for detecting the terminal voltage on the colored side of the ECD and a predetermined coloring density by stopping the voltage application when the ECD terminal voltage exceeds the reference voltage. The drive circuit of the ECD mirror is composed of the control circuit and the control circuit. That is, the sample and hold circuit in the control circuit detects the terminal voltage on the ECD coloring side and controls the coloring density by comparing with the reference voltage set by the volume or switch.

[Embodiment] Next, an embodiment of a driving circuit of the ECD anti-glare mirror of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a driving circuit of an ECD anti-glare mirror of the present invention, and FIG. 2 is a sectional view of an ECD panel.

In the figure, reference numeral 1 is an ECD (electro chromic
Device). This ECD 1 has an electrode layer 3 made of a transparent conductive film on a glass 2 as shown in the enlarged cross section of FIG.
It is a thin panel that is made by laminating glass 7 after applying EC layer 4 which is a coloring layer, electrode layer 5 which is an Al layer, sealing resin layer 6 which is an insulating layer, and glass 7 side is a mirror support. It is fixed to (not shown) by adhesion or caulking.
When a coloring voltage is applied between the electrode layers 3 and 5, the mirror reflectance decreases, and when a depolarizing voltage is applied between the electrode layers 3 and 5, the mirror reflectance increases. Note that the coloring voltage and the erasing voltage are voltages of opposite polarities, as can be seen from FIG.

The drive circuit of the ECD anti-glare mirror of this embodiment is the control circuit 50, E
CD drive power supply 25, first and second sample and hold circuits
10, 20 (hereinafter appropriately referred to as sample and hold circuit) and EC
D1 and third on the terminal 8 of the electrode layer 3 (coloring side) of ECD1
The transistor 13 and the fourth transistor 14 are connected, and the fifth transistor 15 and the sixth transistor 16 are connected to the terminal 9 of the electrode layer 5 (decoloring side).
The first to sixth transistors are MOS type FETs.
The ECD drive voltage source 25 is connected to an ACC or an ignition switch (not shown), and the ECD drive voltage source 25 is connected to the third transistor 13 and the fifth transistor 15.
The diodes D1 and D2 are ECD protection diodes that prevent an overvoltage from being applied to the ECD1.

A terminal 8 of the electrode layer 3 of the ECD 1 is connected via a line 33 to a first sample and hold circuit 10 for detecting a coloring side voltage and a second sample and hold circuit 20 for detecting an erasing side voltage. The terminal 9 of the electrode layer 5 is a fifth or sixth transistor
15, 16 and the alternate switch 31 or 32 described later.

The first sample and hold circuit 10 is composed of a transistor 11, a capacitor C ₁ and a high input impedance buffer 10a, and the second sample and hold circuit 20 is a transistor 12, a capacitor C ₂ and a high input impedance buffer 20.
It consists of a. First and second transistors 11, 1
The gates of 2 are each connected to the clock circuit 24. Further, the output sides of the sample and hold circuits 10 and 20 are connected to a comparator 17 or 27, an inverter 18 or 28, and a NOR circuit 19 or 29 to a contact 31 or a contact 32 of the alternate switch. Connect from contact 31 through lines 34 and 35 to the gates of transistors 13 and 16, and also contact
It is connected from 32 to the gates of transistors 14 and 15 through lines 37 and 38. One contact of the alternate switch 31
Is a switch for applying a coloring voltage to the electrode layer 3 of the ECD1, which raises the coloring density of the ECD1 (reduces the reflectance) to a so-called NIGHT state. The other contact 32, which is linked to the contact 31 of the alternate switch, is a switch for applying an erasing voltage to the power supply layer 5 of the ECD 1, and lowers the coloring density of the substrate 2 (to increase the reflectance) in the so-called DAY state. Let That is, when the contact 31 is closed in the NIGHT state (coloring) and the NOR circuit 19 is "high level", the transistors 13 and 16 are "ON" and the power supply voltage is applied to the terminal 8. The terminal 9 is grounded.

On the other hand, in the DAY state (when the color is erased), the contact 32 is closed and N
If the OR circuit 29 is at "high level", the transistor 14,
When 15 turns “ON”, the terminal 8 is grounded and the terminal 9 becomes the power supply voltage. Therefore, the terminal 8 at the time of coloring and erasing,
The polarities of the coloring voltage and the erasing voltage applied between 9 are reversed. The comparators 17 and 27 on the output side of the sample-hold circuit 10 or 20 compare with the output of the sample-hold circuit by using the voltage set by the adjustment of the volume VR ₁ or VR ₂ as a threshold (reference voltage) to color or erase. Turns the color drive signal on and off. When the headlight of the following vehicle is bright, the driver selectively operates the contact 31 of the alternate switch to reduce the reflectance.

Next, the operation of this embodiment will be described.

FIG. 3 is a timing chart showing the operation of the drive device for the drive mirror of the antiglare mirror of this embodiment when the alternate switch is selected. In FIG. 3, the uppermost row shows the case where the first contact 31 of the alternate switch is turned on (a),
The case (b) in which the second contact 32 is turned on is shown. The second stage of FIG. 3 is the clock signal input to the clock circuit 24 or the NOR circuits 19 and 29, and the third stage and below are diagrams showing the output voltage of the sample and hold circuit and the outputs of the inverters 18 and 28, and
3 is a diagram showing the outputs of NOR circuits 19 and 29. FIG.

To color the ECD1 (anti-glare state), the driver selects the contact 31 of the alternate switch. Capacitor C ₁ and
C ₂ is charged by sampling the colored terminal voltage of ECD 1. When the charging voltage of the capacitor C ₁ exceeds the voltage V _TH1 set by the volume VR1, the output of the comparator 17 becomes (L), one input of the NOR gate 19 becomes (H) by the inverter 18, and its output becomes (L). That is, ECD1
When the voltage of the colored side terminal 8 reaches the reference voltage preset by the volume VR1, the driving of the ECD is turned off, and the coloring density of the ECD does not become higher than the set value.

As described above, at the time of coloring, sampling of the ECD coloring / decoloring side terminal voltage and the ECD drive voltage are alternately repeated at the cycle generated by the clock circuit 24, and driving is performed when the output of the coloring side sample hold exceeds the set voltage. Stop energizing. Further, at the time of erasing, the terminal voltage on the coloring side is sample-held on the erasing side, and when the output voltage becomes lower than the set voltage on the erasing side, the energization is stopped. Volumes VR ₁ and V ₂ on the coloring side and the erasing side are linked, and the coloring side is the first
As shown in the figure, the voltage is high at CW and high at CCW on the bleaching side.

FIG. 4 is a diagram showing the relationship between the colored terminal voltage and the reflectance for each predetermined time. As is clear from this figure, the reflectance increases as the colored terminal voltage decreases.

Next, when erasing the ECD 1, the other switch 32 of the alternate switches is turned on (conducted). At that time, the first contact 31 is opened. At this time, the fourth transistor 15 and the fifth transistor 15 are rendered conductive, and an erasing voltage is applied to the electrode layer of ECD1 from the ECD drive voltage source. Therefore, the ECD has a low coloring density (high reflectance).

That is, the capacitors C ₁ and C ₂ for coloring terminal voltage becomes lower in ECD1 starts discharging. Voltage of the capacitor C ₂ is the output of the comparator 27 and falls below the set voltage of the volume VR2 and (L), inverted by inverter 28, NOR
One input of gate 29 is (H) and its output is (L)
And Therefore, ECD1 does not have a high reflectance above the preset value.

In the drive circuit for the anti-glare mirror of this embodiment, when the driver is dazzled by the headlight of the following vehicle and the like, the reflectance of the anti-glare mirror can be switched by a switch operation, and the driver can set the volume beforehand. You can adjust the density to your liking.

[Advantage of the Invention] According to the present invention, since the anti-glare mirror is configured by the ECD panel, the reflectance of the anti-glare mirror can be easily switched by the switch operation when the driver receives the headlight of the following vehicle and is dazzling. Moreover, the desired reflectance can be set by adjusting the volume.

[Brief description of drawings]

FIG. 1 is a drive circuit diagram of the ECD anti-glare mirror of the present invention, and FIG. 2 is E
FIG. 4 is a sectional view showing an example of the structure of the CD, FIG. 3 is a timing chart showing the operation of the drive circuit of the antiglare mirror of this embodiment when the alternate switch is selected, and FIG. 4 is a coloring terminal voltage and reflection at predetermined time intervals. It is a figure which shows the relationship with a rate. 1 ... ECD, 8, 9 ... Terminals, 10 ... 1st sample hold circuit (detection circuit), 20 ... 2nd sample hold circuit (detection circuit), 10a, 20a ... High input impedance buffer, 11-16 ... Transistor , 17, 27 ... Comparator, 18, 28 ...
Inverter, 19, 29 ... NOR circuit, 25 ... ECD drive voltage source, 24
… Clock circuit, 31, 32… Alternate switch, 50…
Control circuit, C _1, C ₂ ... capacitor, VR _1, VR ₂ ... volume.

Claims (1)

[Scope of utility model registration request] 1. A drive circuit for an anti-glare mirror using an electrochromic device (ECD) panel, wherein the drive circuit detects a terminal voltage of the ECD, and the terminal voltage of the ECD is a reference voltage. A control circuit for stopping the voltage application when the voltage exceeds and controlling the density to a predetermined coloring / discoloring density; and the detection circuit for sampling and holding the terminal voltage at the time of coloring; A second sample-and-hold circuit for sampling and holding the terminal voltage, and the control circuit having a clock circuit for issuing a clock of a predetermined cycle, and a sum-hold of the terminal voltage and a voltage application to the terminal. And are alternately repeated in the cycle of the clock circuit, and at the time of coloring, when the output of the first sample and hold circuit exceeds a set voltage, the voltage application is stopped and the color is erased. The voltage of the coloring during the opposite polarity is applied there, the output of the second sample-and-hold circuit is by stopping the voltage application to be lower than the voltage set, the drive circuit of the ECD dimming mirror.