JPH06326725A - Transmission cell slot designation device - Google Patents

Abstract

PURPOSE:To save the amount of the hardware and to correspond to high speed processing at the same time by using a counter, a register and comparator or the like so as to realize position designation of a cell slot. CONSTITUTION:A cell slot signal from a cell transmission section 52 is fed to A and B use counter count instruction circuits 1, 2 or an m-use count instruction circuit 3. Counters 4, 5, 6 to count A, B, m are provided as the counters and comparators 7, 8, 9 compare values A, B, m of registers 10, 11, 13 with counts and sends a cell generating enable signal and a reset signal or the like when they are respectively match with each other. The registers 10, 11, 12 store the values A, B, m calculated by a control section 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an ATM (Asynchronous
Transfer Mode) In a switching system, a test cell is sent from a test cell sending circuit or an ATM terminal when conducting a continuity characteristic test of a transmission line and a communication line. At that time, it is necessary to specify a sending cell slot. However, the present invention relates to a transmission cell slot designating device therefor.

The continuity characteristic test of the transmission path and the speech path is conducted by AT
It is an important test in the world of M, and is a test that is often performed when a new line is set up or in daily life. Even if the transmission line has a transmission rate (band) of 150 Mbps (150 megabits per second), a user who actually uses the transmission line may use a low transmission rate (band) of, for example, 64 kbps (150 kilobits per second). . At that time, 64 out of a large number of transmission cell slots generated according to the transmission rate of 150 Mbps
Transmission is performed using a small number of transmission cell slots corresponding to a low speed of kbps.

Therefore, when transmitting a test cell, if the channel to be tested has a transmission rate of 64 kbps, the transmission cell slot is correspondingly set to that.
From a large number of transmission cell slots that are generated according to the transmission rate of 150 Mbps, specify cells precisely and transmit the cells, and specify the transmission cell slots so that the cell intervals of the cells to be transmitted are almost constant. You need to do that. In this sense, the present invention relates to a transmission cell slot designation device required when transmitting a test cell.

[0004]

2. Description of the Related Art Conventionally, when an ATM cell is transmitted to a speech channel or transmission channel having a fixed bit rate at an arbitrary bit rate lower than the fixed rate in a form close to a constant interval, the cell is transmitted. In order to specify the cell slot to be sent out, it was necessary to schedule the cell slot in advance and store the result in the memory.

FIG. 5 is a conceptual diagram showing a configuration example of a conventional transmission cell slot designation device. In the figure, 51 is a cell buffer, 52 is a cell transmission unit, 53 is a transmission permission / inhibition determination circuit, 54 is a cell transmission instruction holding memory, 55 is a control unit,
Is.

A fixed bit rate of the transmission line,
One cycle (n cell slot) is determined by an arbitrary bit rate below the fixed rate to be tested, and which cell slot among the n cell slots is controlled in advance is a cell transmittable slot. The data is determined by the unit 55, and the data is written in the cell transmission instruction holding memory 54 for one cycle (for example, a logical 1 is written for a slot that can be transmitted and a logical 0 is written for a slot that cannot be transmitted).

The cell transmitter 52 generates cell slot signals at regular intervals. When receiving the cell slot signal from the cell transmission unit 52, the transmission permission / inhibition decision circuit 53 refers to the cell transmission instruction holding memory 54 at that timing, and the logic 1 is held in the memory position corresponding to the received cell slot signal. If so, it determines that transmission is possible and sends a cell generation permission signal to the cell transmission unit 52, and the cell transmission unit 52 takes in one cell from the cell buffer 51 and performs cell transmission.

If a logical 0 is held in the memory location corresponding to the received cell slot signal when referring to the cell sending instruction holding memory 54, it is determined that sending is impossible and a cell is generated in the cell sending unit 52. A non-permission signal is transmitted, and the cell transmission unit 52 transmits an empty cell or the like in that cell slot.

As described above, the transmission permission / inhibition determination circuit 53 accesses the holding memory 54 every time the cell slot signal is received from the cell transmitting unit 52, and the control unit 55 performs scheduling to store the data in the holding memory 53 for one cycle. The cell transmission instruction information is read out periodically. The cell transmission instruction information is a logical 0 indicating whether or not the cell is transmitted.
As described above, it is expressed by the bit of / logic 1 and indicates only the number of cell slots in one cycle.

For example, when a cell is transmitted at an arbitrary bit rate of an integer multiple of 64 kbps and 155.52 Mbps or less for a speech path having a fixed bit rate of 155.52 Mbps, 155.52 M / 64 k = 2430
The control unit 55 designates the cell slot position to which a cell is to be sent in 2430 cell slots, which is calculated as one cycle, and the result is stored in the holding memory 54.

When transmitting cells at 64 kbps, 2
Designate the first cell of the 430-cell slot, 128 kb
If ps (twice as large as 64), the first cell and the 1216th cell (almost in the middle of the 2430 cell slot) are designated for transmission, this information is stored in the holding memory 54, and this information is stored in the holding memory 54. By periodically reading out, cell transmission at a desired bit rate was realized.

[0012]

However, in this method, control for deciding which cell slot in 2430 cell slots which is one cycle is designated,
A memory for accumulating information on the cell slot position determined by the control unit is required.

Further, when the cell transmission rate to be designated is in units of a very small value (bit rate) as compared with the bit rate of the speech path or transmission path, 1
There is a problem that the number of cell slots in a cycle becomes enormous and the amount of memory for accumulating this information increases.
Further, when attempting to increase the transmission cell speed, there is a limit to the increase in speed due to the limit of the memory access speed because the memory is used.

On the other hand (although it is a completely different matter from the above problem), on the transmission path, the frame overhead and the path are terminated at both ends of the transmission path to perform error correction and alarm transmission / reception, and therefore section overhead and path overhead are required. There is a case in which the band that can be occupied by the ATM cell is limited by that insertion (the transmission speed must be reduced accordingly), and in this case, the AT in the speech path of the ATM switch is
Band (transmission speed) that M cells can occupy and AT in the transmission path
There will be a difference with the band (transmission rate) that can be occupied by M cells.

Therefore, when the ATM exchange is realized, it is necessary to add a new cell slot designating technique in consideration of the difference in the band (transmission rate) to the conventional cell slot designating apparatus. If the cells are not added yet, even if a square slot is designated, cells corresponding to the difference cannot be transmitted and are discarded, resulting in inconvenience.

The object of the present invention is to overcome the above-mentioned problems of the prior art and to provide a defect (increase in memory amount, memory access speed) which is caused by providing a memory for storing information on a cell slot position. Even if the bandwidth (transmission speed) that the transmitted cell can occupy differs between the speech path and the transmission path of the exchange, it is possible to solve the It is to provide a cell slot designation device that does not need to be discarded.

[0017]

In order to achieve the above object, according to the present invention, for a transmission line having a maximum cell transmission rate of T cells per unit time, a rate of T × (m / n) ( However, when m and n are integers and n ≧ m ≧ 1) and a test cell is to be transmitted, which cell slot among the cell slots continuously generated at a rate of T per unit time is selected. In the transmission cell slot designation device that specifies whether to specify as a slot that can be transmitted,

When the quotient of (n / m) is A and the remainder is B, means for calculating A and B in a relationship of n = Am + B, and values of A, B and m are set and held. Each of the holding means for the A value, the B value, and the m value, and the count value is A,
Each counter for A, B, and m that resets and repeats counting when it reaches B and m respectively,

At the rate of T per unit time, cell slot signals that are continuously generated in synchronization with the cell slots are taken in. If the cell slot signal is in the permitted state, the cell slot signal is sent to the A counter for counting and If it is in a permitting state, A counter counting instruction means for ignoring and not sending to the A counter,

If the cell slot signal is taken in and is in the permitted state, the cell slot signal is sent to the B counter for counting, and if it is in the unpermitted state, it is ignored.
Counter counting instruction means for not sending to the counter for B,

The count value of the A counter and the value of the A value holding means are compared, and if they match, the slot matching the timing among the cell slots is designated as a transmittable slot and a designated output is made. First comparing means which is generated, and a counter counting instruction means for m which takes in the designated output from the first comparing means and sends it to the counter for m for counting.

The count value of the m counter and the value of the m value holding means are compared, and if they match, a disable signal for causing the A counter count instruction means to take a disabling state is output. Second comparing means for outputting an enable signal for allowing the B counter counting instructing means to take an enabling state;

The count value of the B counter is compared with the value of the B value holding means, and if they match, an enable signal for causing the A counter count instruction means to take an enable state is output, and the B value is held. And a third comparing means for outputting a disable signal that causes the counter counting instruction means to take a disabling state.

In the present invention, the maximum transmission rate of cells is theoretically T × (m / n) for a transmission path having T cells per unit time (where m and n are integers, respectively). Therefore, the test cell is not transmitted when n ≧ m ≧ 1). However, since the maximum transmission rate of the cell actually allowed is T ′ (where T ′ ≦ T), as a result, T ′ × When a test cell is to be transmitted at a speed of (m / n), which cell slot is designated as the transmittable slot among the cell slots that are continuously generated at a rate of T per unit time. In the transmission cell slot designating device called

Means for calculating C and D satisfying the relation (T-T ') / T = D / C (where C and D are integers) and C value holding for holding the value of C Means and T cell slot signals continuously generated at a rate of T per unit time, and outputs the cell slot signal when in the permit state, but does not output when in the non-permit state. Counter counting instruction means,

If the cell slot signal output from the A, B counter counting instruction means is taken in and is in the permitted state, the cell slot signal is sent to the A counter for counting, and in the non-permitted state. A counter counting instruction means for ignoring and not sending to the A counter, and B counter counting instruction means that functions similarly.

A cell slot signal continuously generated at a rate of T per unit time is taken in, counted, and reset when the count value reaches C, and the count is repeated C
For comparing the count value of the counter for C and the value of the counter for C and the value of the C value holding means, and if they match, outputting a disable signal for causing the A and B counter counting instruction means to be in the disallowed state. 4 comparison means,

The value of D is set as the delay amount, the disable signal output from the fourth comparing means is taken in, delayed by the value D, and then the values of A and B are set.
And a delay means for outputting as an enable signal for allowing the counter counting instruction means to take the enable state.

[0029]

According to the present invention, a counter and a register (each value holding means) are used to specify the position of a cell slot when transmitting a test cell.
And by using a comparator, etc., the hardware is reduced compared to the conventional technology using a memory,
At the same time, it has realized the cell slot designation that can correspond to the high speed.

Further, in the present invention, assuming that the band (transmission rate) that the test cell can occupy due to the transmission overhead signal on the transmission line is reduced, the cell slot at the time of transmitting the test cell, By securing a band corresponding to the transmission overhead in advance and reducing the band of the test cell, it is possible to avoid cell discard when transferring the test cell from the communication path to the transmission path.

[0031]

FIG. 2 is an explanatory view showing an example of specifying a cell slot position when transmitting a cell in the first embodiment of the present invention, and a cell which can be transmitted from a test cell generation (transmission) circuit. When the maximum speed of is set to Tbps, T × (m / n)
An example of designation of a cell slot position for transmitting a test cell at a speed of bps (however, there is a relation of 1 ≦ m ≦ n, m and n are integers and represented as n = Am + B) is shown. ing.

In FIG. 2, the maximum speed (physical speed) Tbp
Among the series of cell slots corresponding to s, the black cell slot is the designated cell slot position when the test cell is transmitted at the speed of T × (m / n) bps. Maximum speed (physical speed) Tbps and test cell transmission speed T × (m /
It can be seen that the relationship of n = m × A + B is established in one cycle (n cell slots) determined by (n) bps.

To execute this cell slot position designating method, n / m is given when T × (m / n) bps is given.
Is calculated, and the quotient is A and the remainder is B, and the test cell is transmitted in one cell slot among the A cell slots, repeated m times, and finally for B cell slots. It suffices to periodically perform the operation for spacing.

For example, for a speech path having a bit rate of 155.52 Mbps, 34.56 Mbps (= 155.
To send a test cell at a speed equivalent to 52 Mbps x 2/9), n / m = 9/2 = 4 remainder 1 (A, B) =
Since it is (4, 1), sending the test cell once every four cells is repeated twice, and then the interval for one cell is inserted periodically.

The interval may be a non-signal state or an empty cell may be inserted according to the interface condition. With such an operation, the transmission cell slot position of the test cell can be specified by the counter for counting A cells and B cells and the counter for counting m times of repetition. , And m is n
In the case of a divisor of B, since B = 0, it is not necessary to insert an interval of B cells, and it is not necessary to count m repetitions. Therefore, only a counter for counting A cells is required. It will be possible.

FIG. 1 is a block diagram showing the configuration of a transmission cell slot designation device (device for executing the cell slot position designation method shown in FIG. 2) as the first embodiment of the present invention. In FIG. 1, 51 is a cell buffer, 52 is a cell sending unit, 1 is a B counter counting instruction circuit, 2 is an A counter counting instruction circuit, 3 is an m counter counting instruction circuit, 4
Is an A counter, 5 is a B counter, 6 is an m counter, 7 to 9 are comparators, 10 is an A value holding register, 11 is a B value holding register, 12 is an m value holding register, and 13 is a control unit. ,.

Referring to FIG. The cell transmission unit 52 generates a cell slot signal at regular intervals, and based on the cell generation permission signal input from the comparator 7 in synchronization with this signal,
Whether to transmit cells in the cell slot is determined.
At this time, the cell slot signal is not necessarily the cell transmission unit 5
It is not necessary to be supplied from the second circuit, but may be supplied from another circuit such as a clock supply unit (not shown).

If cell transmission is possible, cell transmission unit 52
Takes in one cell from the cell buffer 51 and performs cell transmission. If transmission is not permitted, an empty cell is transmitted or a no-signal state is created. The cell slot signal from the cell transmission unit 52 is input to the counter counting instruction circuits 1 and 2 which hold a determination state as to whether to count up the counters 5 and 4, and the counter counting instruction circuits are enabled for counting (enable). In the case of the state (1), it passes through the counter counting instruction circuits 1 and 2 and is input to the counters 5 and 4.

In the count disabled state (disabled state), the cell slot signal cannot pass through the counter counting instruction circuits 1 and 2. There are two types of counter counting instruction circuits, A and B counter counting instruction circuits 1 and 2 which are in a count enable state when an enable signal is input from the outside and a count disabled state when an disable signal is input from the outside. , B ≠ 0, the counter is in the count enable state, and if B = 0, there is the m counter count instruction circuit 3 in which the count is disabled. Therefore, the latter has a function of a 0 determination circuit (when it is determined to be 0, it stops functioning thereafter).

The counter has counters 4, 5 and 6 for counting A, B and m, and comparators 7, 8 and 9
Is a register 1 holding the values of A, B and m
0, 11 and 12 are compared with the values of the respective counters, and if the two values match, a cell generation enable signal or enable / disabl
Send the e signal and reset signal. Register 10, 11
The values of A, B, and m calculated by the control unit 13 are stored in and 12, respectively.

The above-mentioned designation of the sending cell slot can be realized as shown in FIG. 3 using these counters, registers, comparators and the like. From the beginning, B
When it is clear that = 0, it is possible to delete the B counter, the m counter, and the like.

The circuit operation will be described below in more detail with reference to FIG. For a transmission path in which the maximum transmission speed of cells is T cells per unit time, a speed of T × (m / n) (where m and n are integers and n ≧ m ≧
When the test cell is to be transmitted in 1), the transmission cell slot designation is made as to which cell slot is designated as the transmittable slot among the cell slots continuously generated at a rate of T per unit time. That is why.

Therefore, first, in the controller 13, (n /
When the quotient of m) is A and the remainder is B, A and B having a relationship of n = Am + B are calculated, and the values of A, B, and m are the A value holding register 10 and the B value holding register 1, respectively.
1. The value is held in the m-value holding register 12. The A counter 4, the B counter 5, and the m counter 6 start counting from the 0-cleared state, and when the count values reach A, B, and m, respectively, the corresponding comparators 7, 8 and 9 respectively.
It resets by the reset signal from and repeats counting again.

The counter counting instruction circuit 2 for A takes in cell slot signals synchronized with cell slots continuously generated at a rate of T per unit time, and enables (enab) state.
If the cell slot signal is
For sending to the counter 4 for counting and disabling (di
If it is in a enabled state, it is ignored and is not sent to the A counter 4.

The B counter counting instruction circuit 1 also takes in the cell slot signal, and if the cell slot signal is in the enabled state (enable state), the cell slot signal is sent to the B counter 5
To count, and if it is in a disallowed state (disabled state), it is ignored and not transmitted to the B counter 4.

The comparator 7 compares the count value of the A counter 4 with the value of the A value holding register 10, and if they match, the slot matching the timing among the cell slots is designated as a cell transmittable slot. Then, the cell generation permission signal is output to the cell transmission unit 52. m counter counting instruction circuit 3
Takes in the cell generation enable signal from the comparator 7 and sends it to the m counter 6 for counting.

The comparator 9 compares the count value of the m counter 6 with the value of the m value holding register 12, and if they match, A
A disable signal for causing the B counter counting instruction circuit 2 to take a non-permission state is output, and an enable signal for causing the B counter counting instruction circuit 1 to take a permission state is output. The comparator 8 compares the count value of the B counter 5 and the value of the B value holding register 11 and, if they match, outputs an enable signal for causing the A counter count instruction circuit 2 to take an enable state, and A disable signal is output to the B counter counting instruction circuit 1 to bring it into a non-permission state.

The m counter counting instruction circuit 3 monitors the value of B output from the control unit 3 and when it is 0, even if the cell generation permission signal from the comparator 7 is fetched, This is not sent to the m counter 6 (because it is not necessary in itself).

As is clear from the above description, in this embodiment, as compared with the conventional method of scheduling the transmission cell slot using the memory, the memory is not used and the counter having a small hardware scale is used. It has become possible to reduce wear. At the same time, since the operation speed of the counter is generally higher than the access speed of the memory, it is possible to configure a cell slot designating device that operates at a higher speed.

FIG. 4 shows the second embodiment of the present invention.
It is an explanatory view showing an example of specifying a cell slot position when transmitting a cell, and the maximum speed of the cell that can be transmitted from the test cell generation circuit is Tbps, but S is on the transfer path of the cell.
When there is a DH (Synchronous Digital Hierarchy) transmission line, etc., the bandwidth that can be occupied by the cell (transmission speed) is reduced by the amount of overhead information such as SDH, and the maximum speed is T'bps.
T ′ × m in the case where it falls to (T ′ ≦ T)
9 shows an example of cell slot position designation for transmitting a test cell at a speed of / nbps (1 ≦ m ≦ n; n = Am + B).

In order to realize this designation method, the cell transmission from the test cell generation circuit is (T-T ') / T = D / C.
(However, C and D are each an integer) Among the C cells calculated by forcibly stopping the transmission of D cells only once, there is no signal state or empty cells for D cells. Then, under this condition, the sending cell slot may be designated according to the method shown in the first embodiment.

For example, for a speech path having a bit rate of 155.52 Mbps, STM-1 of 155.52 Mbps SDH
When the transmission line is accommodated, the cell can occupy the SDH transmission line at the bit rate corresponding to 149.76 Mbps excluding the SDH overhead information on this transmission line. ) / T = (155.52-
Of the 27 cells calculated by (149.76) /155.52=1/27, it is sufficient to create a non-signal state or an empty cell for one cell at a time.

FIG. 3 is a block diagram showing the configuration of a transmission cell slot designation device (device for executing the transmission cell slot designation method shown in FIG. 4) as the second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that
A / B counter counting instruction circuit 21 and C counter 2
2, a D cell slot delay circuit 23, a comparator 24,
A C value holding register 25 and a control unit 26 for further calculating the C value and the D value are added as shown in the figure.

The circuit operation unique to this embodiment will be described below. For a transmission path in which the maximum cell transmission rate is theoretically T cells per unit time, a rate of T × (m / n) (where m and n are integers and n ≧ m ≧ 1) ), The test cell is not transmitted, but since the maximum transmission rate of the cell actually allowed is T ′ (where T ′ ≦ T),
As a result, when the test cells are to be transmitted at a rate of T'x (m / n), which cell slot can be transmitted among the cell slots continuously generated at a rate of T per unit time. It is a transmission cell slot designation as to whether or not it is designated as a slot.

Therefore, in the present embodiment, the control unit 26 controls (n
/ M) where A is the quotient and B is the remainder, n = Am + B
In addition to calculating A and B that have the following relationship, (TT ′) /
C and D satisfying the relationship of T = D / C (where C and D are integers) are calculated and set in corresponding holding registers to be held.

The counter counting instruction circuit 21 for A and B takes in cell slot signals which are continuously generated at a rate of T per unit time, and is in an enabled state (enabled state).
If it is, the cell slot signal is output, but if it is in the disapproved state (disabled state), it is not output.

The C counter 22 takes in cell slot signals continuously generated at a rate of T per unit time,
When counting and the count value reaches C, the comparator 24 resets by the reset signal which should be output at that time, and repeats counting again. The comparator 24 compares the count value of the C counter 22 with the value of the C value holding register 25, and if they match, outputs a disable signal for causing the A and B counter count instruction circuit 21 to be in the disallowed state. (In addition, the coincidence output resets the C counter 22).

The D cell slot delay circuit 23 is set with the value of D (time length corresponding to the number of D cell slots) as the delay amount, and takes in the disable signal output from the comparator 24. After delaying by D value, A,
The signal is output as an enable signal for causing the B counter counting instruction circuit 21 to enter the enable state.

Other than the above, it is the same as that described with reference to FIG. 1 and will not be repeated. In this way, the transmission cell slot as shown in FIG. 4 can be designated.
According to this embodiment, the SDH has such an action.
Even if a test cell passes through the transmission path, all the test cells are transferred on the path without being discarded, even though SDH overhead information is newly inserted on the transmission path. Become.

As is clear from this result, in this embodiment, the ATM corresponding to the transmission overhead on the transmission line is used.
Since the transmission cell slot is specified by pre-calculating the amount of cell bandwidth reduction, the cell at the time of interface conversion between the speech path and the transmission path can be used even when a new SDH transmission path is accommodated in the ATM switch. It is possible to avoid loss (disposal).

[0061]

As described above, according to the present invention,
Since it is possible to specify the transmission cell slot in the test cell transmission circuit using a counter, register, comparator, etc., the memory required for scheduling is no longer required as in the past, and less hardware is required compared to the conventional method. ,
There is an advantage that it is possible to provide a cell slot designation device that operates at a higher speed while realizing the designation of a transmission cell slot.

Further, the present invention is not limited to the designation of the transmission cell slot in the test cell transmission circuit, but the designation of the transmission cell slot of the user cell in various ATM terminals, etc.
It can be applied to all devices having a transmission mechanism of TM cells, and has an advantage that it can correspond to reduction of hardware and high speed in a wide range of application.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a transmission cell slot designating apparatus as a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of specifying cell slot positions when transmitting cells in the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a transmission cell slot designation device as a second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of cell slot position designation when transmitting cells in the second embodiment of the present invention.

FIG. 5 is a conceptual diagram showing a configuration example of a conventional transmission cell slot designation device.

[Explanation of symbols]

1 ... B counter counting instruction circuit, 2 ... A counter counting instruction circuit, 3 ... m counter counting instruction circuit, 4 ... A counter, 5 ... B counter, 6 ... m counter, 7-9
Comparator, 10 ... A value holding register, 11 ... B value holding register, 12 ... m value holding register, 13 ... Control unit, 21
... A / B counter counting instruction circuit, 22 ... C counter, 23 ... D cell slot delay circuit, 24 ... Comparator, 2
5 ... C value holding registers 25, 26 ... Control unit, 51 ... Cell buffer, 52 ... Cell sending unit

Claims (3)

[Claims] 1. The maximum transmission rate of a cell is T per unit time.
When transmitting test cells at a speed of T × (m / n) (where m and n are integers and n ≧ m ≧ 1) to a transmission line that is a number of cells, the unit time is In the transmission cell slot designating device which designates which cell slot is designated as a slot which can be transmitted among cell slots continuously generated at a rate of T per cell, the quotient of (n / m) is A and the remainder is B. Then n = Am +
A means for calculating A and B having a relationship of B, an A value holding means for setting and holding the values of A, B, and m, a B value holding means, and an m value holding means, respectively. When the count value is started and the count value reaches A, B, and m, respectively, and resets and repeats counting again, the counter for A, the counter for B, and the counter for m are continuously generated at a rate of T per unit time. If the cell slot signal synchronized with the cell slot is taken and is in the permitted state, the cell slot signal is sent to the A counter for counting, and if it is not permitted, it is ignored and is not sent to the A counter. A counter counting instruction means for A and a cell slot signal which is synchronized with the cell slot continuously generated at a rate of T per unit time are taken in, and in a permit state, Cell slot signal is sent to the B counter for counting, and if it is in a non-permitted state, it is ignored and is not sent to the B counter, B counter counting instruction means, the A counter count value and the A value. The first comparison means for comparing the value of the holding means and, if they match, a slot that matches the timing of the cell slots is designated as a transmittable slot to generate a designated output, and the first comparison means. The designated output from the means is fetched, sent to the m counter and counted, and the count value of the m counter is compared with the value of the m value holding means. An enable signal for outputting a disable signal for causing the counter counting instruction means for B to take the non-permission state and for enabling the counter counting instruction means for B with the permission state Second comparison means for outputting a signal for comparing the count value of the B counter and the value of the B value holding means, and if the values match, the A counter counting instruction means is allowed to enter the enable state. And a third comparing means for outputting an enable signal and a disable signal for notifying the B counter counting instruction means. Designated device. 2. The transmission rate of cells is theoretically T × (m /
n) speed (where m and n are integers, and n ≧
Although the test cell is not transmitted when m ≧ 1), the maximum transmission rate of the cell actually allowed is T ′ (however, T ′ ≦ T), so that T ′ × (m / n) results. When a test cell is to be transmitted at the speed of, the transmission cell slot designation of which cell slot is designated as the transmittable slot among the cell slots that are continuously generated at a rate of T per unit time In the apparatus, when the quotient of (n / m) is A and the remainder is B, n = Am +
Means for calculating A and B, which have a relationship of B, (T
−T ′) / T = D / C (where C and D are integers), means for calculating C and D, and values of A, B, m, and C set and held, respectively. A value holding means, B value holding means, m value holding means, and C value holding means, start counting from the 0-cleared state, and when the count values reach A, B, and m, respectively, reset and count again. A counter for A, a counter for B, and a counter for m which are repeated, and a cell slot signal which is continuously generated at a rate of T per unit time and which is synchronized with the cell slot are fetched. If it is output, but is in the non-permission state, the A / B counter counting instruction means which does not output, and the cell slot signal output from the A / B counter count instruction means are taken in, and in the permission state, The cell slot signal is sent to the A counter for counting,
If it is in the non-permission state, the counter count instruction means for A, which is ignored and not sent to the counter for A, and the cell slot signal output from the counter count instruction means for A, B are taken in. A cell slot signal is sent to the B counter to count,
If it is in the non-permission state, the B counter counting instruction means that ignores and does not send to the B counter is compared with the count value of the A counter and the value of the A value holding means. A first comparing means for generating a designated output by designating a slot that coincides with the timing as a transmittable slot, and fetching a designated output from the first comparing means and sending it to the m counter. The m counter counting instruction means for counting and the count value of the m counter and the value of the m value holding means are compared, and if they match, the disk for causing the A counter counting instruction means to be in the disapproved state. Second comparing means for outputting an enable signal and an enable signal for allowing the B counter counting instruction means to be in an enable state; and a counter for the B counter. Value and the value of the B value holding means are compared, and if they match, an enable signal for causing the A counter counting instruction means to take an enabling state is output, and at the same time, to the B counter counting instruction means. Is a third comparing means for outputting a disable signal for taking the disabling state, and a cell slot signal synchronized with the cell slots continuously generated at a rate of T per unit time is taken in, counted and counted. When the counter reaches C, the counter for C which resets and repeats counting is compared with the count value of the counter for C and the value of the C value holding means, and if they match, the counter counting instruction means for A and B And a fourth comparing means for outputting a disable signal for causing the disabling state, and a value of D set as a delay amount, which is output from the fourth comparing means. Delaying means for taking in the disable signal, delaying it by a D value, and outputting it as an enable signal for bringing the counter counting instruction means for A and B into an enable state. Sending cell slot designation device to perform. 3. The transmission cell slot designating apparatus according to claim 1, wherein the m counter counting designating means monitors the value of the B and when the value is 0, the first comparison is performed. A sending cell slot designating device comprising an instructing means for not outputting the designated output from the means to the m counter.