JPH01500074A - Adaptive speed multiplexer-demultiplexer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Adaptive Speed Multiplexer-Demultiplexer Background of the Invention.

The present invention multiplexes multiple sub-channels of various transmission rates into a fixed transmission rate channel. It relates to a device for transmitting and disassembling sub-channel transmission. Concerning equipment for adapting to various combinations of speed and fixed channel transmission rate. Ru.

"Frame ψ Arrangement for Multiplexing φγ - Briny Lary Tee-off subchannels ◆On-to-a fixed rate φ channel (Frase Arrangement for MultlplEIXlng a Pluralityor 5ubchannels onto a Pl xed Rate Channel) J on April 17, 1985. In my pending U.S. Patent Application No. 724.199, I am For a framing structure consisting of j sets of l-tuples for Lj bits per frame. states. Parameters i and j are a function of the transmission rate of the secondary channel and a fixed channel. Mathematically determined as a function of the transmission rate of the channel. At l-tuple j-1 The i-1 bits are used for information, and the i-1 bits at either end of the l-tuple are One bit is set to 1 (or O). In one of the l-tuples, all The l bit is set to 0 (or 1).

cannot occur elsewhere in the frame regardless of the data pattern; 1 Monitor for one consecutive 0 (or 1) followed or preceded by (or 0) It is detected by ° Remaining (i-1) (j-1) bit positions in the frame In , the desired transmission rate for each subchannel is given, An integral number of information bits from each subchannel are distributed.

In my said patent application, i and j are calculated and the bit allocation is done within the frame. Once done, this frame structure can be used to set any combination of subchannel transmission rates. I have a multiplexer and a demultiplexer that can multiplex and demultiplex respectively. It is explained in detail. As the number of digital links directly connected to users increases, Flexible multiplexing and decomposition equipment available. Additionally, mixing different transmission speeds A device that can provide both sides of a user's data channel mix on a single line It is desirable to give users the flexibility to

Summary of the invention The multiplexer-demultiplexer of the present invention provides on/off fixed transmission rate channels. Identification of the frame structure of the data, on and off, multiple side channels at various transmission speeds Adaptive multiplexing and adaptive decomposition according to the parameters. Those parameters are It is determined by the transmission speed of the secondary channel and the transmission speed of the fixed channel. Multiplayer The multiplexer-demultiplexer structure stores the bit allocation pattern for the frame. and a storage device that responds to an internally generated clock signal at the transmission rate of the secondary channel. data exchange between the multiplexer-demultiplexer and the secondary channel. Multiple secondary channel interfaces with each clocking and fixed transmission rate connected to the degree channel and storage device and multiple sub-channel fist interfaces, The secondary channel interface responds to the bit allocation pattern stored in storage. data flow from the interface to the output channel and from the output channel to the subchannel. a core that controls the data flow of the interface.

It also provides a clock signal whose frequency is determined as a function of the stored frame structure. No., a nucleus is generated. To obtain the clock signal for each subchannel, The channel interface uses that clock signal. The mixing of the secondary channels changes. A new frame structure is obtained from the secondary channel transmission rate, and a new bit allocation is obtained. When stored in a storage device as a pattern, the multiplexer demultiplexer of the present invention The multiplexer adapts to the new frame structure and routes the clock signal to a new subchannel. Figure 1 shows that (i-1) (j-1) of the information bits are automatically transmitted at the transmission speed. The multiplexer demultiplexer of the present invention includes j one type of bits such that shows the frame organization used by the multiplexer, FIG. 2 is a block diagram of the adaptive transmission rate multiplexer-demultiplexer of the present invention. , Figure 3 is a block diagram of the main parts of the multiplexer-demultiplexer in Figure 2; FIG. 4 shows one subchannel input of the multiplexer-demultiplexer of FIG. Figure 5 is a block diagram of the secondary channel interface in Figure 4. A block diagram of the secondary channel clock generator, FIG. timing during the transmit cycle between the signal and the secondary channel interface signal. showing the relationship, Figure 7 shows the transmission cycle of the last bit in a frame between these various signals. Figure 8 shows the timing relationships between these various signals during the receive cycle. shows the timing relationship, Figure 9 shows the relationship between these various signals during the reception cycle of the last bit in the frame. Show timing relationships.

detailed description In my said pending patent application mentioned here for reference, several different transmissions I created a frame structure for multiplexing rate sub-channels into fixed transmission rate channels. has been established. The frame structure shown in FIG. 1 is composed of five 1-tuples. 1st lta All bits in the pull are set to 0, and the first and last bit in each other l-tuple is set to 0. bit is set to 1. Therefore, in each frame there are (i-1) (j-1) There are bits of information. By examining the received data stream for a 1 followed by a 0. If the framing is lost, the framing can be easily recovered. .

As mentioned in my said application, the transmission rate r(k) of the various subchannels The parameters i and j can be calculated from the transmission rate R of the common channel. channel biography The frame length i j − xQ can be found for any combination of transmission speeds. Ru. In each frame of 1j-xQ bits, xp (k) bits are sent to each subchannel. bits are assigned and distributed over (i-1) (j-1) information bit positions. Here , p (k) cod Qr (k)/R.

Once the frame structure is redefined, the bit allocation pattern can be changed to The command can be stored in a storage device as a series of commands entered on the keyboard at the target location.

Select the appropriate bit to send next in the multiplexed stream from a particular subchannel , or to select them as forced 1 or 0 framing bits. commands can be selected. Similarly, directing the received bits to the appropriate subchannel Decomposes the multiplexed stream received by The same instruction can be used to detect framing by scanning.

As will be explained in detail later, the multiplexer-demultiplexer of the present invention required to clock the data bits and turn the various subchannels on and off. storage by generating a lock signal r(k) from the bit allocation distribution. Automatically adapts to the existing frame structure.

Referring to Figure 2, the multiplexer-demultiplexer has up to 12 subchannels. Contains secondary channel interfaces 201-0 to 201-11 for handling nothing.

Secondary channel interfaces 201-0 to 201-11 are connected to the core by bus 202. 203. Its core is the storage device 204, the human power channel 205, and the output Connected to channel 206. Storage device 204 stores a particular subchannel transmission rate set. bit allocation patterns for bit and fixed channel transmission rate sets; A subchannel number is included in each bit position from number 1 to number ij within the frame. the Sends the data bit of that number to each bit position of the secondary channel number, and receive the data bits of the subchannel number from each bit position of the channel number, or That bit is the framing bit. For each framing pit, the memory Device 204 determines whether the bit position in the frame is 0, 1, or Stores one of three special codes indicating whether it is the last 1 in the frame. do. In response to the address on ADDR lead 207, which indicates the bit position in the frame. In response, storage device 204 sends one of the 12 secondary channels to data lead 208. A 4-bit channel identification number that identifies the data, or one of the three special codes mentioned above. respond to lead 208;

The core 203, which will be explained in detail later, has sub-channels and input and output channels 205, 2. functions as a traffic controller during 06, accesses the storage device 204, and Manage the transfer of bits as specified by the contents of the storage device.

By maintaining the bit count within the frame in the multiplexing and decomposition directions, 203 reads the address in the form of a bit count to the storage device 204 via read 207; supply to The response of storage device 204 given to lead 208 is the secondary channel ID. code, or one of the special codes mentioned above. If it is a secondary channel ID, the core 203 is Alerts the identified secondary channel φ interface via bus 202 and bits are caused to enter or exit from the interface. Storage device response is special code, the kernel 203 inserts a forced 1 or 0 into the multiplexed stream. , or compare the received bits with their predicted values to determine if an out-of-frame condition exists judge whether

Each bit in the multiplexed bit stream from input channel 205 is connected to lead 209. into the core 203 in response to the external clocking signal RXC on the top. Each RXC In response to the clock pulse, core 203 increments its receive counter; A storage device that stores the code associated with that bit position! Search from 204, Distribute the bits. In the transmit direction, external clocking on lead 210 In response to clock signal TXC, kernel 203 clocks each bit to output channel 206. Control and give. In response to each TXC pulse, nucleus 203 counters its transmit counter. increments the bit position and retrieves the stored code for that bit position from storage and searches for the next bit to send.

In response to the transmitted and received bits, bus 202 extracts kernel 2 from the frame structure. 03 transmits the clock signal extracted internally. That clock signal is In order to synthesize the channel clock frequency r(k), Used by faces 201-10 to 201-11. I'll explain in detail later In other words, those clock signals are stored in a new frame structure automatically adapts to. Bus 202 also carries other clock and control signals discussed below. I can do it. Those signals are transmitted by external systems whose frequencies are sufficiently higher than the transmission rate of the channel. Includes clock SYS CLOCK. Speeds up processing of codes stored inside the nucleus. For speed, the system clock is input to the core 203 via lead 211. be done. Also, SYS CLOCK is the secondary channel interface 201-0 ~201-11.

Each sub-channel O interface 201- has a multiplexed data output terminal 20 The serial data bits to be output to 6 and the associated sub-channel data It is received from input terminal 215-k. Similarly, each subchannel φ interface 20 1- is combined with the decomposed data received at the data input terminal 205. is applied to the sub-channel data output terminal 216-. In addition, each subchannel The interface 201- is provided with a synchronous clock at the subchannel transmission rate r (k). Occur. Its synchronized clock clocks bits within the secondary channel interface. Used to lock and turn the secondary channel on and off, and to Feed externally to secondary channel.

As will be explained in more detail below, the clock signal generated by the nucleus 203 These clock signals are adaptively and automatically derived. As explained later, Each secondary channel interface 201- includes a bus 202 from channel 205. buffers the data bits addressed to it aperiodically and transfers those bits to is output at subchannel transmission rate r(k). Similarly, the input of the transmission rate r(k) The side channel bits are buffered by the secondary channel interface 201-k. bus 20 when kernel 203 addresses that subchannel for a certain bit. 2 aperiodically.

The nucleus 203 will be explained in detail with reference to FIG.

Elements that appear in many figures are given the same number. Nucleus 203 is channel in interface 301, storage interface 302, and microsequencer 303. Channel 0 interface 301 has an input data channel. 205, output data channel 206, RXC clock lead 209, and TX C clock lead 210, micro sequencer 303, and bus 202 are connected be done. Storage interface 302 provides transmit and receive bits per frame. Keep count of cuts. Those bits provide address information when requested. The information is given to the storage device F204 via the ADDR lead 207. lead A microcontroller that operates in response to the high-speed device clock SYS CLOCK on the 211. -controller 303 generates a tiqm signal. Its control signals record address information. The channel input is applied to memory ff1204 and is set to 0 or 1 in the transmitted bit stream. To signal interface 301 and signal bit request or bit arrival is used on bus 202.

The operation of the nucleus is best understood with reference to the timing diagrams of FIGS. 6-9. Figure 6 During a normal transmit cycle shown in Figure 2, each TXC pulse on lead 210 is a free strobes flip-flop 304; rCH, DATAOUTJ timing line As shown above, flip-flop 304 has its D input terminal and flip-flop The data stored in the Q output terminal of the flop 305, that is, the framing bits” to channel 206.

This same TXC pulse is applied to microsequencer 303 at the same time. This ma The microsequencer responds to that pulse as shown on the rTXENJ timing line. First, enable the TXEN lead 306. EN of transmission TX counter 307 The TXEN lead 306 connected to the input terminal connects the A Enables its current count to DDR read 207.

The ADDR timing line represents the parallel transmission of this 16-bit count. after that, Storage device 204 (shown in FIG. 2) stores the secondary channel ID, or three previous response with a 4-bit word on DATA lead 203 indicating one of the special codes. this is shown on the DATA timing line. In that DATA timing line, rS UBH, IDJ represent the response of the 4-bit parallel storage device. This response DATA word is bus for transmission to secondary channel interfaces 201-0 to 201-11. In addition to being available on 202 channel identification CHID leads, - Interpreted by controller 303. Then, the micro sequencer 303 The DIRID lead on bus 202 as marked on the DIR timing line. 310 to indicate the direction of transmission on the channel (1 for transmit, 0 for receive).

Then, as noted on the BUS, CLK timing lines, The controller enables the BUS CLK lead 311 and displays reasonable HID data. and DIR data are present on bus 202. Let me know.

The secondary channel code on CHID data lead 203 will be explained in detail later. The secondary channel interface 201- addressed by the TXD lead 312, the oldest stored by that secondary channel interface. bit, it is sent to flip-flop 3 via NOR gates 313 and 314. It is input to the D input terminal of 03. The TXD timing line is connected to this 1 bit or 0 bit. The bit is indicated as the "oldest bit in the secondary channel FIFO". Next, the microsi -controller 303 is marked on the DSTB timing line. D-8TB lead By enabling 315 and strobing flip-flop 305, This secondary channel data bit is input to the primary bit of flip-flop 304. Transfer to terminal. NEXTB IT timing line is free from TXD lead 312 Transfer of the “oldest bit” to this “next bit” input terminal of flip-flop 304 Indicates sending. Then, the microsequencer 303 causes the TX counter 307 to Pulse the TXUP lead connected to the terminal to record on the TXUP timing line. As has been said, increase the power ° runt of it.

Rather than responding with a secondary channel ID, storage device 204 may respond with a special code of those that respond with one special code indicating that framing 1 or 0 should be transmitted Then, the micro sequencer 303 is FORCEON E IJ-do 319* Or enable the FORCE ZEROIJ-dead 320. those leads are Connected to Noah gates 313 and 314, respectively. 1 or 0 is flip-flop is placed at the input terminal of step 305, and the flip-flop is activated in response to the next D-STB pulse. A clock is input to the input pin 304. A special code indicates the last bit of the frame. If not, the TXUP read 317 is enabled and the TX counter 30 A count of 7 is incremented.

Figure 7 shows the timing when responding with a special code indicating the last bit in the frame. Show relationships. As noted on the DATA timing line, the DATA response is “1”. The force-one code-bit is J, From now on, the Micro Detector Sasa 303 will be able to use the FORCEONE lead 119. (F, shown on the ONEN timing line). NEXTB IT time In response, a 1 is placed in flip-flop 305, as noted on the line. recorded. The micro sequencer 307 also clears the TX counter 307. Enable the CLR person (marked on the TXCLR timing line). To be so Then, the TX counter 307 clears the count to 0.

Microsequencer 303 enables D-STB lead 315 and flips After the bit at the D input terminal of flop 305 is held at its Q terminal, Whether the bit is a secondary channel bit or a forced 1 or 0 bit. Even if this is the case, all transmission bit processing is completed. Micro sequencer 303 disables the TXEN lead 306 and is now stored in the flip-flop 305. This “next bit” is responsive to the next TXC pulse on lead 210. and is ready to be held from flip-flop 304 to output channel 206. death Therefore, as shown on the CH and DATAOUT timing lines in FIGS. 6 and 7, In response to the leading edge of this next TXC pulse, the previously processed The ``oldest bit'' or ``forced 1'' bit is output. However, the following TXC pulse, kernel 203 processes the received bits from input channel 205. The timing diagrams in Figures 8 and 9 illustrate normal receive signals during the receive cycle. indicates the timing relationship between each bit and the last bit in the frame. It is.

Data bits received on input channel 205 (CLDATA I N timing line ) is held in flip-flop 326 in response to the RXC pulse on lead 209. is connected to the microsequencer 30 via the lead 327 (RXD timing line). 3 and via bus 202 to the secondary channel interface 201- Given from 0 to 201-11. In response to the leading edge of the RXC pulse (RXC timing ), the microsequencer 303 has a reception RX counter Enable the RXEN lead 328 connected to the EN input terminal of the 329. (marked on the RXEN timing line). Then, the RX counter 329 outputs its current count to ADDR read 207. according to that count In response, storage device 204 writes the secondary channel ID code or the Output one of the special codes (ADDR timing line and DATA timing line ). Then, the microsequencer 303 responds to the reception direction (0). to set the DIR lead 310 and activate the BUSCLK lead 311 (D (see IR timing line and BUSCLK timing line).

Microsequencer 303 examines the codewords returned by storage 204. So RXD lead 325 is the secondary channel ID, as described below. The bits received are written on the SUB and FIFO (RX) timing lines. the RXUP timing line is maintained on the appropriate secondary channel interface. As noted above, the microsequencer 303 connects to the RXUP lead 330. A pulse is applied to increase the count of the RX counter 329. the word is a special code If so, the microsequencer 303 reads the bit received by the RXD read 327, Compare with the predicted framing bits, as indicated by the special sign. received The predicted bit matches the predicted bit, and the predicted bit is the last bit in the frame. If not, the microsequencer 303 will be programmed to the signal to increase the count of the RX counter 329. The received bit is predicted If the bits do not match, the microsequencer 303 will go into an out-of-frame condition; A pulse is given to the RXCLR lead 332 to clear the RX counter 329 and reset the counter. start operation again. The reframe sequence will be explained later.

FIG. 9 shows the timing relationship for the last frame bit. Storage device 204 CH, DATAIN timing when the special code from indicates the last frame bit. The received bit is expected to be 1, as marked on the timing line and RXD timing line. be measured. In response to the special sign of the last bit, microsequencer 303 Give a pulse to the XCLR332 (see RXCLR timing diagram) and actually receive the pulse. The RX counter 329 is cleared regardless of the data bits added.

As mentioned earlier, when the received bits match the predicted framing bits, Microsequencer 303 always enters an out-of-frame state. In response, the RX Counter 329 is reset. for the first i bit positions in the frame Since the frame structure requires that the received bit be 0, i 0s are accepted. The RX counter 329 is reset one after another until the received data Ensure that the flow is in the frame.

When all bit processing is completed in the receive direction, the microsequencer 303 returns the RXEN. 328, BUSCLK lead 311, and DIR lead 310. so that kernel 203 can process the next bit sent to output channel 206. I will do it.

In addition to acting as a traffic controller for transmitted and received bits, the kernel 2 03 generates a clock signal RXQ on lead 335 of bus 202. That black The frame signal is generated adaptively as a function of the frame parameters. I'll explain later , the secondary channels associated with secondary channel interfaces 201-0 to 201-11. In order to obtain the clock signal r(k) determined by the channel, the secondary channel - The interface uses RxQ clock signals. storage interface 302 includes a latch 340. This latch has as input the counter of TX counter 307. count output 308 is received. The count of the TX counter 307 is immediately cleared. is latched to the output of latch 340 in response to each TXCLR pulse.

Therefore, the callan that is latched in each output frame) (TXCLR is the last (enabled only in response to frame bits) is the number of bits in the frame or, as stated earlier, always equal to xQ. Therefore, the latch The output of the 340 always remains xQ as long as the frame is xQ bits long, and the output of the 341. The count of the counter 341 is sent to the down DN input terminal. decrease in response to each subsequent TXC pulse on connected lead 210. It will be done. When the count reaches zero, the CY output terminal connected to RxQ lead 335 A pulse is generated on the child. This same CY output terminal is the load LD of the counter 341. By connecting to the input terminal, xQ is input to the counter every time the count becomes zero. Reload. xQ One pulse is given to CY for every TXC clock pulse Therefore, the frequency of the pulses on RxQ lead 335 is equal to or greater than the frequency of TXC. is equal to R/x divided by Q. where R is the input channel 205 and the output is the transmission rate of channel 206. Each frame consists of a different number of bits xQ. When the frame structure stored in storage device 204 is changed so that Since the output of switch 340 automatically changes to the new value of xQ, RxQ Adapt to wave number.

The operation of the sub-channel interface 201 will be explained with reference to FIG.

Each subchannel interface 201- has a destination in the transmission direction (to channel 206). buffer 401 (in-first-out FIFO) and reception direction (from channel 205). ) FIFO buffer 402.

In the transmission direction, the data bits from the subchannel data input terminal 215-k are sequentially input into the latch 403. This latch is used by the secondary channel clock generator. bit in response to the secondary channel clock signal r(k) generated by Output to the input terminal of FIFO 401.

As will be explained later, the sub-channel Φ clock generator 405 Automatically generate a clock signal of the relevant frequency r(k). FIFO401 buffers the bits being read. Those bits are clocked in response to a clock signal generated by face controller 406 .

Secondary channel interface controller 406, secondary channel indicating last frame bit. CHID lead 211 on bus 202 for codewords or special codes in the channel. Monitor the codeword above. If a sign is present in the secondary channel, the secondary channel is bit Controller 406 determines from DIR lead 310 whether to transmit or receive.

When DIR lead 310 is set to 1 (transmit), BUSCLK lead 311 The enablement of the controller 406 triggers the CHS E L E CT IJ- enable the bit 420 and the oldest stored bit in the FIFO 401. The TX lead 312 is clock-controlled and output via the gate 407, and the FIFO Shift the data in 401 and write the upper subchannel clock r (k) to 217- move data in response to When DIR lead 310 is set to zero (receive) , enablement of BUS CLK lead 311 triggers controller 406 to Activate the input clock of IFO 402 and read the data bit on RXD lead 327. Load. The FIFO 402 sequentially stores the decomposed bits and stores the upper sub-chip in 217-. In response to the channel clock r(k), their The bits are clocked up to the secondary channel 216-.

By storing transmit bits and receive bits in FIFOs 401 and 402, respectively. It is possible to synchronize the data in the transmit direction and the receive direction, and it is possible to synchronize the external circuit. A stored frame bit allocation meter that allows operation in a periodic manner. A multiplexed stream in which data is buffered and exits by the kernel as specified by the image. placed in Average transfer rate is equal for both the 8 secondary channels and the ingress channel However, the data is sent bit by bit, ostensibly periodically.

The sub-channel clock generator 405 will be described with reference to FIG. This horn Lock generator 405 is a digital phase-locked loop with an output frequency f including. Its output frequency is shown to be equal to r(k), and the sub This is the required frequency for the channel. Clock generator 405 also includes a counter 501. nothing. This counter counts every time subchannel k is selected for transmission. , by the CH-SELECT lead 420 of the secondary channel interface controller. is increased.

A special code indicating the last frame bit in the transmit direction is used on the secondary channel or interface. When the controller 406 detects the SOF lead 421, it activates the SOF lead 421. accordingly In response, the contents of counter 501 are loaded into latch 502, and the contents of counter 501 are loaded into latch 502. The count is cleared. Therefore, each frame equal to xp(k) by definition A latch 502 holds the number of bits sent from secondary channel k during the system.

That value is loaded into counter 503. The counter 503 is a storage device shown in FIG. A counter 311 in the interface 302 divides the TXC frequency by the divisor xQ. In the same way as we did, the frequency of a conventional digital voltage controlled oscillator (VCO) 501 Divide the number f by the divisor xp (k). Therefore, the CY output of counter 503 Since the lead 506 is pulsed once for each xp(k)f pulse , the frequency is equal to f/xp(k). A conventional phase comparator 505 converts this signal into Rx Compare with Q clock signal. The frequency of that clock signal is R/xQ. was shown earlier. The frequencies at both input terminals of phase comparator 505 are unequal. i.e., xp (k) xQ The phase comparator raises or lowers the frequency of VCO 504 until . death Therefore, f is driven by Rp(k)xQ. This is the desired secondary channel Equal to the lock frequency r (k).

As mentioned earlier, the frequency of the RxQ clock signal adapts to changes in the frame structure. Therefore, the clock generator associated with each subchannel has a new frame structure. Adapt to. The reason is that the frequency divisor xp(k) within each subchannel is automatically set a value equal to the number of bits allocated to that subchannel in the frame structure. This is because it takes

The storage device 204 of the multiplexer-demultiplexer may be ROM or RAM. can be done. If ROM is used, the frame structure can be static, but It can be modified to suit different transmission speeds required by changing the ROM. Limited Assuming that you require a different set of transmission speeds, the ROM can be Can hold turns. Suppose you require a limited set of different transmission speeds. , externally selected using a switch or one-chip microprocomputer The ROM can hold several possible patterns. Highly dynamic transmission speed If you have trouble setting the frame parameters, you can use the RAM storage to save the frame parameters. Configure the bit allocation for new frames, calculated from the transmission rate, and A microcombination unit that can change the contents of RAM according to the new frame value of can be included. Although the invention has been described in relation to the ij frame format, Frame parameters determined as a function of primary and secondary channel transmission rates Other frame formats may also be employed in accordance with the present invention.

The embodiments described above illustrate the principles of the present invention.

Other embodiments can be constructed by those skilled in the art without departing from the spirit of the invention.

Engraving (change in content L) Engraving (no changes to the content) Engraving (no changes in content) RXCLR--111--11111-Engraving (no change in content) Clean# (no change in content) FIG.8 Zhu Yi ≦ [y427mu There is no summer heat in the clean heat CV'j Akuta) FIG.9 Shikufugu 27k (Kyo (Mugi no t'7) N Procedural amendment form) 1.Display of the incident PCT/US 86101190 2. Name of the invention Adaptive speed multiplexer-demultiplexer 3, corrector Relationship to the incident: Patent applicant bell, communications, Research, Inc. 4. Representative (zip code 100) 3-2-3 Marunouchi, Chiyoda-ku, Tokyo Telephone Tokyo (211) 2321 representative 7. Contents of correction (1) As per the attached sheet.

(2) Engraving of drawing translation (no change in content), l11.11. l□− to τ/U S 86101190 2ANNEX To 1ff: INTERNATIO NAL 5 EAR 4 REPORT ON

Claims (26)

[Claims] 1. Has a frame structure in which the transmitted bits and received bits consist of a fixed number of bits. The number of bits per frame is determined by the transmission speed of the digital subchannel. multiple digital signals, determined as a function of transmission rate and fixed transmission rate channel transmission rate. multiplexes the secondary channels into the transmitted bit stream on a fixed rate channel A multi-speed channel that decomposes the transmitted bit stream from a speed channel into multiple digital sub-channels. In the plexer-demultiplexer, the bit allocation pattern of the frame structure is a storage device for storing; a plurality of transmission bit storage means and reception bit storage means; the storage device, the plurality of transmission bit storage means, reception bit storage means, and is connected to a fixed transmission rate channel, and the transmission bits from the plurality of transmission bit storage means are connected to a fixed transmission rate channel. the plurality of transmission bit storage means according to the stored bit allocation pattern; forming the transmitted bit stream by selecting bits from the stored bits; The bits in the received bit stream are allocated to the plurality of received bit streams according to an allocation pattern. a bit distribution means for distributing to the storage means; a plurality of clocking means; , one transmission bit storage means and one reception bit storage means each correspond to one digital each transmission bit storage means is associated with it. The bits to be multiplied are stored in the transmitted bit stream from the digital sub-channel, and each received The bit storage means stores digital data associated with it from the received multiplied bit stream. stores the bits to be distributed to the secondary channels, One clocking means is associated with each one digital sub-channel, one A digital subchannel and a transmission associated with that one digital subchannel A clock for clocking bits between the bit storage means and the received bit storage means. each of said plurality of clocking means is responsive to a frame structure to generate a clock signal; Automatically synchronizes the clock signal of it with the transmission speed of the digital sub-channel occurs, The multiplexer-demultiplexer is configured to control the transmission rate of a plurality of digital sub-channels. stored in said storage device as a function of transmission rate and fixed transmission rate channel. A multiplexer-demultiplexer that adapts to the frame structure being used. 2. A multiplexer-demultiplexer according to claim 1, wherein each frame frame contains j 1-tuples, where i and j are the transmission rates of multiple digital sub-channels. and is determined mathematically as a function of the transmission rate of the fixed transmission rate channel, and one Each bit in the j-tuple has a framing bit set for the first given binary digit. and one bit at one end of the other j-1 i-tuples is the opposite second is the framing bit set for the binary digits of and the remaining (i-1)(j- 1) An integer number of bits from each decimal subchannel are placed in a predetermined pattern at a bit position. for each bit in the frame, the bit is a code indicating that the bit is assigned to one of the secondary channels; A first special code indicating one of the framing bit sets for the number. and the bit is one of the framing bit sets for said first binary digit. a second special code indicating that the A j-tuple that is temporally adjacent to said one j-tuple containing a framing bit set of hexadecimal digits. The multiplayer frame contains a third special code indicating that the framing bits are xa-demultiplexer. 3. A multiplexer-demultiplexer according to claim 2, wherein said The bit distribution means counts the bits in each frame in the received bit stream. It is equipped with a counting means and a transmission counting means for counting the bits in the transmission bit stream. Furthermore, the reception counting means and the transmission counting means calculate their respective counts to the a plurality of digital bit distribution means in response to each count; said code indicating one of said three special codes of said secondary channel; A multiplexer-demultiplexer receiving from a storage device. 4. A multiplexer-demultiplexer according to claim 3, wherein said The bit distribution means divides the transmission rate of the fixed transmission rate channel into bits in each frame. further comprising means for generating a clock signal at a rate divided by the number of clock signals; The signal is based on the transmission rate of the fixed transmission rate channel and the file stored in the storage device. A multiplexer-demultiplexer that adapts to frame structures. 5. A multiplexer-demultiplexer according to claim 3, wherein said The bit distributing means includes a count of the transmission counting means and a set in the storage device. Transmission bit storage means combined with the code according to the code being matched by selecting the bits stored in or framing bits. A multiplexer-demultiplexer further comprising means for forming a transmit bit stream. 6. A multiplexer-demultiplexer according to claim 3, wherein said The bit distribution means generates a direction signal indicating the transmission direction and reception direction for each bit. the multiplexer-demultiplexer further comprises means for generating a plurality of controls; further comprising controllers, each controller being combined into one digital sub-channel, each controller is responsive to the specific code of the subchannel associated with it and the direction signal. and when the bit distribution means receives the specific code from the storage device, A transmission bit storage means or a reception bit storage means of the sub-channel and the bit distribution means. Multiplexer-demultiplexer for clocking bits between stages. 7. The multiplexer-demultiplexer according to claim 4, wherein the Each clocking means is a controllable oscillator means for generating a first clocking signal. and a frame from a secondary channel that is combined with said first clocking signal. means for dividing the divided first clocking signal by the number of bits per frame; said clock at the transmission rate of said fixed transmission rate channel divided by the total number of bits of a comparator for generating a control signal in comparison with a lock signal, the control signal being a subchannel coupled to said first clocking signal by driving said oscillator means; output at the channel transmission rate, and the new file taken from the new subchannel transmission rate. When the frame structure is stored in the storage device, the first clocking signal is multiplexer-demultiplexer that automatically adapts to new sub-channel transmission rates of Kusa. 8. A multiplexer-demultiplexer according to claim 1, wherein the multiplexer-demultiplexer comprises: the storage device comprises means for storing bit allocation patterns of a plurality of frame structures; Each frame structure has a digital subchannel transmission rate and a fixed transmission rate channel transmission rate. A multiplexer-demultiplexer determined from different combinations of degrees. 9. A multiplexer-demultiplexer according to claim 1, wherein the multiplexer-demultiplexer comprises: The bit allocation pattern of the frame structure stored in the storage device is Other frames determined from different transmission rates of the channel and fixed transmission rate channels A multiplexer-demultiplexer that can be replaced with the bit allocation pattern of the structure. sa. 10. A frame with a frame structure in which the transmitted bits consist of a fixed number of bits. The number of bits depends on the transmission rate of the digital subchannel and the fixed transmission rate cha Fixed transmission of multiple digital sub-channels determined as a function of channel transmission rate At the multiplexer that multiplexes the transmitted bit stream onto the speed channel, a storage device for storing a bit allocation pattern of a frame structure; a plurality of bit storage means each associated with one digital sub-channel; connection to said storage device and said plurality of bit storage means and a fixed transmission rate channel; and storing the plurality of bits according to the stored bit allocation pattern. bit distributing means for selecting bits from the means to form the transmitted bit stream; multiple clocking means; , each storage means multiplexing the transmitted bit stream from one digital sub-channel. one clocking means is associated with each digital sub-channel. combined with one digital sub-channel and one digital sub-channel. generates a clock signal to clock the bits between the bit storage means , each of said plurality of clocking means are combined in response to a frame structure. Automatically generates its clock signal at the transmission rate of the digital sub-channel and A multiplexer supports multiple digital sub-channel transmission rate and fixed transmission rate channels. the frame structure stored in said storage device as a function of the transmission speed of the channel. corresponding multiplexer. 11. 11. The multiplexer according to claim 10, wherein each frame has j Contains an i-tuple, where i and j are the transmission rates and fixed transmissions of multiple digital sub-channels. Each j-tuple in a j-tuple is determined mathematically as a function of the transmission rate of the rate channel. bits is the framing bit set for the first given binary digit; One bit at one end of j-1 i-tuples corresponds to the opposite second binary digit. and the remaining (i-1) (j-1) bit positions , an integer number of bits from each digital sub-channel are distributed in a predetermined pattern. and the storage device stores, for each bit in the frame, one bit of the digital sub-bit. a code indicating that the bit is assigned to the first binary digit; a first special code indicating that the bit is one of the the one j-tuple containing the framing bit set of the first binary digit; A map containing a third special code indicating that the framing bit set is adjacent to Lutiplexa. 12. 12. The multiplexer according to claim 11, wherein the bit distribution means is a receive counting means for counting the bits in each frame in the received bit stream; , comprising transmission counting means for counting bits in the transmission bit stream, count means supplying the count to said storage device; said bit distribution means: In response to each count, one of the plurality of digital sub-channels or said three special A multiplexer receiving from the storage device the code indicating one of the codes. 13. 13. The multiplexer according to claim 12, wherein the bit distribution means is the transmission rate of the fixed transmission rate channel divided by the number of bits in each frame. further comprising means for generating a clock signal at a speed, said clock signal being Transmission rate Adapts to the transmission rate of the channel and the frame structure stored in the previous storage multiplexer. 14. 13. The multiplexer according to claim 12, wherein the bit distribution means is the combined count of said transmission counting means and said storage device. According to the code, the bits stored in the transmission bit storage means associated with the code are The transmitted bit stream is controlled by selecting the framer bits or framing bits. A multiplexer further comprising means for forming. 15. 13. The multiplexer according to claim 12, wherein the multiplexer - the demultiplexer further comprises a plurality of controllers, each controller having one digital subchannel; channel, and each controller controls a particular sign of the subchannel to which it is associated. said bit distributing means receives said particular symbol from said storage device in response to said particular symbol. At times, the bits between the transmission bit storage means of the sub-channel and the bit distribution means multiplexer for clocking. 16. 14. The multiplexer of claim 13, wherein each clocking The means includes controllable oscillator means for generating a first clocking signal; Number of bits per frame from the secondary channel combined with the clocking signal and means for dividing the divided first clocking signal by the total number of bits per frame. The ratio of the clock signal to the transmission rate of the fixed transmission rate channel divided by a comparator for generating a control signal by comparing said oscillator means; the transmission rate of the secondary channel being driven and combined with the first clocking signal; , and the new frame structure derived from the new subchannel transmission rate is When stored in the storage device, the first clocking signal becomes the new subchannel. Multiplexer that automatically adapts to channel transmission speed. 17. 11. The multiplexer according to claim 10, wherein the storage device includes a plurality of storage devices. a means for storing bit allocation patterns for each frame structure; is another combination of the digital secondary channel transmission rate and the fixed transmission rate channel transmission rate. multiplexer determined from the 18. The multiplexer according to claim 10, wherein the multiplexer is stored in the storage device. The bit allocation pattern of the frame structure is fixed with the digital sub-channel. Bit allocation of other frame structures determined from different transmission modes of transmission rate channels. A multiplexer that can be replaced with a guess pattern. 19. A frame with a frame structure in which the received bits consist of a fixed number of bits. The number of bits depends on the transmission rate of the digital subchannel and the fixed transmission rate cha bits received on a fixed transmission rate channel, determined as a function of the transmission rate of the channel In a multiplexer that decomposes a stream into multiple digital sub-channels, a storage device for storing a bit allocation pattern of a frame structure; a plurality of bit storage means each associated with one digital sub-channel; connection to said storage device and said plurality of bit storage means and a fixed transmission rate channel; bits in the received bit stream according to the stored pit allocation pattern. bit distribution means for distributing bits to the plurality of bit storage means; and a plurality of clocking means. and , each storage means multiplexing the transmitted bit stream from one digital sub-channel. one clocking means is associated with each digital sub-channel. combined with one digital sub-channel and one digital sub-channel. generates a clock signal to clock the bits between the bit storage means , each of said plurality of clocking means are combined in response to a frame structure. Automatically generates its clock signal at the transmission rate of the digital sub-channel and A multiplexer supports multiple digital sub-channel transmission rate and fixed transmission rate channels. the frame structure stored in said storage device as a function of the transmission speed of the channel. corresponding demultiplexer. 20. Claim 19: The demultiplexer according to claim 19, wherein each frame has j , where i and j are the transmission rates and fixed transmission rates of multiple digital subchannels. The transmission rate is determined mathematically as a function of the transmission rate of the channel, and the Each bit is a framing bit set for the first predetermined binary digit; one bit at one end of j-1 i-tuples of is converted into the opposite second binary digit This is the framing bit set for the remaining (i-1) (j-1) bits. An integer number of bits from each digital subchannel are distributed in a predetermined pattern at the and the storage device stores, for each bit in a frame, the bit as a digital subchannel. a code indicating that the bit is assigned to one of the channels and the bit corresponds to said first binary digit. a first special code indicating that the bit is one of the framing bit sets; said one j-tuple whose bits include a framing bit set of said first binary digit; a third special code indicating that the framing bit set is temporally close to Demultiplexer including. 21. 21. The multiplexer according to claim 20, wherein the bit distribution means is a receive counting means for counting the bits in each frame in the received bit stream; , comprising transmission counting means for counting bits in the transmission bit stream, count means supplying the count to said storage device; said bit distribution means: In response to each count, one of the plurality of digital sub-channels or said three special a demultiplexer receiving from said storage device said code indicative of one of said codes; 22. 22. The demultiplexer according to claim 21, wherein the bit distribution means step divides the transmission rate of the fixed transmission rate channel by the number of bits in each frame. further comprising means for generating a clock signal at a speed determined by the fixed speed. The transmission rate depends on the transmission rate of the channel and the frame structure stored in the storage device. Adaptive demultiplexer. 23. 22. The demultiplexer according to claim 21, wherein the demultiplexer is configured to replace a plurality of controllers. In preparation, each controller is combined into one digital sub-channel, and each controller In response to the particular sign of the associated sub-channel, said bit distributing means When the specified code is received from the storage device, the transmission bits of the subchannel are stored. a demultiplexer for clocking bits between the means and the bit distribution means; 24. 23. The demultiplexer of claim 22, wherein each clock The clocking means includes controllable oscillator means for generating a first clocking signal; bits per frame from the subchannel combined with the clocking signal of means for dividing the divided first clocking signal by a number of bits per frame; the clock signal at the transmission rate of the fixed transmission rate channel divided by the total number of channels; and a comparator for generating a control signal, said control signal being connected to said oscillator means. the transmission rate of the sub-channel that is combined with the first clocking signal by driving the first clocking signal. The new frame structure derived from the new subchannel transmission rate is When stored in the storage device, the first clocking signal Demultiplexer that automatically adapts to channel transmission speed. 25. 20. The demultiplexer according to claim 19, wherein the storage device is each frame structure. The structure has a different combination of digital sub-channel transmission rate and fixed transmission rate channel transmission rate. Demultiplexer determined from the 26. 20. The demultiplexer according to claim 19, wherein the demultiplexer stores data in the storage device. The bit allocation pattern of the stored frame structure is unique to the digital subchannel. Other frame structure bits determined from different transmission rates of a constant transmission rate channel Demultiplexer that is replaceable with penalty patterns.