JPH06268551A - Synthesizer circuit - Google Patents

Abstract

PURPOSE:To attain high quality communication in all radio channels even in a broad band system so that adverse effect of harmonics of a reference oscillation signal is not given onto the radio channel. CONSTITUTION:When a radio channel receiving the effect of harmonics of a reference oscillating frequency fr is selected, a control circuit 240 applies an ON-control signal to a switch circuit 11, which is closed and then the reference oscillating frequency fr generated from an inverter 8 is changed by a predetermined quantity and to compensate a change in the reference oscillating frequency fr, the control circuit 240 sets a compensation frequency division number R' to a frequency divider 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synthesizer circuit provided as a local oscillating circuit in a wireless device such as a vehicle-mounted wireless device, a mobile phone, a cordless phone, a selective call receiver to which a multi-channel access system is applied.

[0002]

2. Description of the Related Art Conventionally, this type of synthesizer circuit is constructed as shown in FIG. 7, for example. That is, the reference oscillation signal (frequency fr) oscillated by the reference oscillator 1
Is frequency-divided by the frequency divider 2 and then input to the phase comparator (PD) 3. The local oscillator signal (frequency fv) generated by the voltage controlled oscillator (VCO) 4 is frequency-divided by the frequency divider 5 and then fed back to the phase comparator 3.
The phase comparator 5 compares the phase of the divided local oscillation signal with the phase of the divided reference oscillation signal, and outputs a signal representing the phase difference. This phase difference signal is integrated by the loop filter 6 and becomes a control voltage, which is supplied to the VCO 3. The VCO 3 generates a local oscillation signal having a frequency corresponding to the control voltage. Further, in this synthesizer circuit, when the local oscillation frequency is changed in accordance with the switching of the receiving channel, the control circuit (not shown) outputs channel data, and the frequency division number of the frequency divider 5 is changed by this channel data. To be done. In addition,
The phase comparator 3 and the frequency dividers 2 and 5 are PLLIC 7
Often integrated as.

By the way, the reference oscillator 1 used in such a conventional synthesizer circuit is, for example, as shown in FIG.
It is configured as shown in. That is, first, as shown in FIG. 8, a crystal oscillator 9 is connected between the input and output ends of an inverter 8 provided in the PLLIC 7, and both ends of the crystal oscillator 9 are connected to capacitors C1 and C2, respectively.
The reference oscillation frequency fr is generated from the inverter 8 according to the capacitance of the capacitors C1 and C2. On the other hand, what is shown in FIG. 9 is an oscillation circuit composed of a transistor Tr, capacitors C1 to C4, and resistors R1 and R2. The oscillation frequency of the crystal oscillator 9 and the capacitances of the capacitors C1 to C4 of the oscillation circuit are shown. A corresponding reference oscillation frequency fr is generated.

[0004]

However, in such a conventional synthesizer circuit, the reference oscillation frequency fr generated from the reference oscillator 1 is fixed to a constant value.
It had the following problems.

That is, in a wireless communication system to which the multi-channel access system is applied, generally, a plurality of wireless channels are arranged at a fixed interval within a predetermined communication allocation band, and a wireless device is selected from the plurality of wireless channels. Communication is performed by selecting an available wireless channel. Here, the normal wireless channel system is, for example, as shown in FIG.
As shown in (a), the interval Δf between the wireless channels is set wider than the bandwidth fw of each wireless channel. Therefore, even if the harmonic nfr of the reference oscillation frequency generated from the reference oscillator of the synthesizer circuit falls within the communication allocation band, the harmonic frequency nfr of the radio channel as shown by A in FIG. If the reference oscillation frequency fr is set in advance so as to be located between the bandwidths, there is no fear that the above harmonic wave nfr will adversely affect the wireless channel.

However, for example, in a radio communication system adopting an interleave system, the radio channel system is shown in FIG.
Since they are more densely configured as shown in (a) and (b), the interval between wireless channels is Δf / 2, which is narrower than each wireless channel bandwidth fw. In this case, it becomes impossible to set the reference oscillation frequency fr so that its harmonic frequency nfr is located between the bandwidths of the radio channels. Therefore, at least one of the radio channels is always affected by the harmonics nfr of the reference oscillation signal, and the deterioration of communication quality cannot be avoided.

In order to prevent the above-mentioned problems, it is considered to set the reference oscillation signal frequency fr so that its harmonic wave nfr does not fall within the communication allocation band.
However, in order to implement this, it is necessary to increase the operation upper limit frequency of the PLLIC 7. However, this would hinder the reduction of power consumption, making it difficult to apply to wideband systems.

The present invention has been made in view of the above circumstances, and an object thereof is to prevent the adverse effect of the harmonics of the reference oscillation signal from affecting the wireless channel without increasing the power consumption and the cost. In this way, it is possible to provide high-quality communication on all the radio channels within the communication allocation band, and to provide a synthesizer circuit suitable for a radio device used particularly in a broadband radio communication system.

[0009]

To achieve the above object, the present invention provides a reference in a synthesizer circuit provided in a radio device for selecting a desired radio channel frequency from a plurality of radio channel frequencies for communication. In addition to a reference oscillating circuit for generating an oscillating frequency and a PLL circuit for generating a local oscillating frequency corresponding to the desired radio channel frequency based on the reference oscillating frequency generated by the reference oscillating circuit, Reference oscillation frequency varying means,
And parameter changing means. And the above PL
When a local oscillation frequency corresponding to a specific radio channel frequency is generated from the L circuit, the reference oscillation frequency changing means changes the reference oscillation frequency generated by the reference oscillator, and the local oscillation is generated by changing the reference oscillation frequency. The parameter of the PLL circuit is changed by the parameter changing means in order to correct the change in frequency.

[0010]

As a result, according to the present invention, the reference oscillator generated by the reference oscillator itself when the harmonics of the reference oscillation frequency may adversely affect the radio channel frequency selected for communication. The oscillating frequency is changed, whereby the harmonic of the reference oscillating frequency is shifted to a position where it does not adversely affect the wireless channel. Therefore, no matter which radio channel is selected from the plurality of radio channels, it is possible to avoid the influence of the harmonics of the reference oscillation frequency, thereby improving the communication quality. Further, it can be applied to a wide band system. Further, since it is not necessary to increase the operation upper limit frequency of the PLL circuit, neither the power consumption of the circuit nor the cost increase will occur.

[0011]

1 is a circuit block diagram showing a configuration of a receiving system of a digital radio device provided with a synthesizer circuit according to an embodiment of the present invention.

In FIG. 1, a radio carrier signal transmitted from a radio device of a communication partner (not shown) is received by an antenna 110 and then input to a high frequency amplifier 130 via an antenna duplexer (DUP) 120. 1
After being amplified by 30, it is first input to the first mixer 140. In the first mixer 140, the radio carrier signal is mixed with the first local oscillation signal generated from the synthesizer circuit (SYN) 150, whereby the frequency is converted into the first reception intermediate frequency signal. The synthesizer circuit 15
0 generates a first local oscillation signal corresponding to the radio channel frequency to be received, according to the radio channel data given from the control circuit (CONT) 240. The first reception intermediate frequency signal output from the first mixer 140 is subjected to level control by an intermediate frequency amplifier 170 having an automatic gain control function, after removing excess frequency components by the first intermediate frequency filter 160. , The second mixer 18
Input to 0. In the second mixer 180, the first mixer
The reception intermediate frequency signal is mixed with the second local oscillation signal generated from the local oscillator 190 and frequency-converted into the second reception intermediate frequency signal. The second received intermediate frequency signal is passed through the second intermediate frequency filter 200, and then further converted into a frequency capable of being subjected to digital demodulation processing.
It is input to the mixer 210. In the third mixer 210, the second received intermediate frequency signal is mixed with the third local oscillation signal generated from the local oscillator 220, whereby the frequency is converted into a received baseband signal. Then, the received baseband signal is input to the digital demodulation circuit (DEM) 230 and demodulated.

By the way, the synthesizer circuit 150 is constructed as follows. FIG. 2 is a circuit block diagram showing the configuration. Incidentally, in FIG.
The same parts as those in FIG.

A crystal oscillator 9 is connected between both ends of an inverter 8 for reference oscillation provided in the PLLIC 71.
One end of the crystal unit 9 has a variable capacitance type capacitor C1.
It is always grounded via. The other end of the crystal unit 9 is always grounded via the capacitor C2,
When the switch circuit 11 is closed, it is further grounded via the capacitor C3. That is, the other end of the crystal unit 9 is grounded only through the capacitor C2 when the switch circuit 11 is in the open state, and the parallel circuit of the capacitor C2 and the capacitor C when the switch circuit 11 is closed. Grounded through. The switch circuit 11 is provided in the PLLIC 71 and turns on / off according to an on / off control signal generated from the control circuit 240.

The control circuit 240 includes a synthesizer circuit 1
A memory table is provided for controlling 50. Radio channel control data is stored in this memory table. This wireless channel control data is associated with each wireless channel, the frequency division number N, the switch circuit 1
The ON / OFF control information of 1 and the frequency division number R are set. The control circuit 240 reads the frequency division number N corresponding to the radio channel used, the ON / OFF control information of the switch circuit 11, and the frequency division number R from the memory table when performing the wireless communication, and these pieces of information are respectively synthesized by the synthesizer circuit 150. Frequency divider 5, switch circuit 11 and frequency divider 2
Supply to.

Next, the operation of the synthesizer circuit configured as described above will be described based on a concrete example. Now suppose
Consider a system in which a plurality of radio channels are arranged at 12.5 KHz intervals in a communication allocation frequency band of 275 MHz to 287 MHz. In the radio used in this system, assuming that the reference oscillation frequency fr generated in the synthesizer circuit 150 is 6 MHz, the center frequency f0 is f0 = 276 MHz and f0 = 282.
In the radio channel set to MHz, the harmonics of the reference oscillation frequency fr appear in the channel width.

Therefore, in order to prevent harmonics of the reference oscillation frequency from appearing in these radio channels, the reference oscillation frequency fr is switched in each radio channel as follows in this embodiment.

That is, for example, the frequency fIF1 of the first reception intermediate frequency signal of the above radio is set to fIF1 = 21 MHz,
Further, when the synthesizer circuit 150 is of the lower quintuple system, the phase comparison frequency fpd is equal to the channel interval (12.5).
From KHz), fpd = 12.5 KHz / 5 = 2.5 KHz. Since the first local oscillation signal frequency fL1 corresponding to the radio channel having the center frequency f0 = 276 MHz is fL1 = f0-fIF1 = 255 MHz, the oscillation frequency before being multiplied by 5, that is, the oscillation frequency of VCO4 is fL1 / 5 = 51 MHz. Similarly, the oscillation frequency of the VCO 4 corresponding to the wireless channel having the center frequency f0 = 282 MHz is fL1 / 5 = 52.2 MHz.

Now, with this condition held, each of the above-mentioned radio channels (center frequency f0 = 276 MHz, f0 = 2)
In order to vary the reference oscillation frequency fr at 82 MHz), the capacitance value of the capacitor C3 is set so that the reference oscillation frequency fr becomes, for example, fr = 6.025 MHz. At the same time, the frequency division number R of the frequency divider 2 is set to R'incremented by 1, and the switch control information for turning on the switch circuit 11 is associated with each of the radio channels and stored in the memory of the control circuit 240. Remember in the table.

With this setting, the above radio channels (center frequency f0 = 276 MHz, f0 =) are used for communication.
282 MHz) is selected, an ON control signal is supplied from the control circuit 240 to the switch circuit 11 in accordance with the radio channel control data in the memory table, whereby the switch circuit 11 is closed. Therefore, from the inverter 8, the natural frequency of the crystal unit 9, the capacitance of the capacitor C1, the capacitors C2 and C
Reference oscillation frequency fr =
6.0025 MHz is generated. Therefore, at this time, the harmonics generated by the reference oscillation frequency are generated by the respective radio channels (center frequency f0 = 276 MHz, f0).
= 282MHz)
Therefore, the reference oscillation frequency fr for each of the radio channels is
Problems that adversely affect the harmonics of are prevented.

At this time, the frequency dividing number R '(value increased by 1 from the normal value) is set in the frequency divider 2 from the control circuit 240. Therefore, the reference oscillation frequency f
r = 6.025 MHz is frequency-divided by R'in the frequency divider 2 to be compensated for the phase comparison frequency fpd = 2.5 KHz, and then supplied to the phase comparator 3. Therefore, from the VCO 4, the above radio channel frequencies f0 = 276 MHz, f
0 = 282 MHz corresponding to 51 MHz, 52.2 MH
z will be generated, which results in the first mixer 140
Then, the radio carrier signals of the radio channels are correctly mixed.

The above radio channels (center frequency f
When a wireless channel other than 0 = 276 MHz, f0 = 282 MHz) is selected, an OFF control signal is supplied from the control circuit 240 to the switch circuit 11. For this reason, the switch circuit 11 is held in the open state, and as a result, the reference oscillation frequency determined by the natural frequency of the crystal unit 9, the capacitance of the capacitor C1, and the capacitance of the capacitor C2 from the inverter 8. fr = 6 MHz is generated. Further, the control circuit 240 sets a normal value to the frequency divider 2. Therefore, the phase comparator 3 is supplied with the phase comparison frequency fpd = 2.5 KHz.

As described above, in the synthesizer circuit of this embodiment, when the radio channel affected by the harmonic of the reference oscillation frequency fr is selected, the control circuit 240 supplies the ON control signal to the switch circuit 11. The control circuit 24 closes the switch circuit 11, changes the reference oscillation frequency fr generated from the inverter 8 by a certain amount, and compensates for the change in the reference oscillation frequency fr.
The frequency division number R'for compensation is set to the frequency divider 2 from 0.

Therefore, even when the radio channel affected by the harmonic of the reference oscillation frequency fr is selected, the harmonic is removed from the radio channel according to the change of the reference oscillation frequency, whereby the reference for the radio channel is obtained. It is possible to prevent adverse effects of harmonics of the oscillation frequency.
Therefore, high-quality communication can be performed in all radio channels without being affected by the reference oscillation frequencyless harmonics. Further, in this embodiment, the switch circuit 1
1 and the addition of the capacitor C3 and the change of the wireless channel control data are all that is required. It is not necessary to increase the upper limit frequency of the operation of the PLL circuit or prepare a special crystal oscillator with a high oscillation lower limit frequency. There are advantages that can be realized.

The present invention is not limited to the above embodiment, but various modifications can be made as follows.
That is, in the above embodiment, the case where the reference oscillation frequency fr is varied without changing the phase comparison frequency fpd has been described. According to this method, only by changing the frequency division number R of the frequency divider 2 according to the variable amount of the reference oscillation frequency fr, the PLL
It can be easily implemented without changing any other parameters of the circuit. However, in this method, the reference oscillation frequency f
Since r is variable from 6 MHz to 6.0025 MHz, the variable width is as large as +417 ppm. This frequency variable width may be difficult depending on the circuit configuration.

Therefore, if the reference oscillation frequency fr is varied while the phase comparison frequency fpd is not fixed and is slightly changed, the variable width of the reference oscillation frequency fr can be reduced. For example, it is assumed that the phase comparison frequency fpd is set to fpd = 2.500121 KHz and the reference oscillation frequency fr is set to fr = 6.000022 MHz for two radio channels having center frequencies f0 = 276 MHz and f0 = 282 MHz. Then, the variable range of the reference oscillation frequency fr at this time is +48.447 ppm.

When the reference oscillation frequency fr is set in this way, each of the above radio channels (center frequency f0 = 276 MHz)
z, f0 = 282 MHz), and the harmonics of the reference oscillation frequency fr generated near the band of 276.0134 M
Hz and 282.0137 MHz, which are outside the band of each radio channel.

When the phase comparison frequency fpd and the reference oscillation frequency fr are set as described above, each of the above-mentioned radio channels (center frequency f0 = 276 MHz, f0 = 2).
82MHz) synthesizer frequency VCO4
Therefore, it is necessary to change the frequency division number N of the frequency divider 5 appropriately. For example, the center frequency f0 = 276
The frequency division number N is set to N = 20399 for the radio channel of MHz, and the frequency division number N is set to N = 20879 for the radio channel of the center frequency f0 = 282 MHz. With this setting, the synthesizer frequency before quintuple multiplication (oscillation frequency fv of the VCO 4) becomes fv = N × fpd = 50.99997MHz in the radio channel with the center frequency f0 = 276MHz, and the radio frequency with the center frequency f0 = 282MHz In the channel, fv = N × fpd = 52.200029 MHz. These values are -0.57p for the accurate frequency fv (51MHz) that the VCO 4 should generate.
The deviation is pm and +0.56 ppm.

That is, according to the above method, the reference oscillation frequency f is obtained by only slightly changing the phase comparison frequency fpd.
r can be varied within a small variable range of about 50 ppm, and the oscillation frequency f of the VCO 4 generated at this time f
v, that is, the deviation of the first local oscillation frequency fIL1 is 1 ppm
It can be suppressed to the following.

When only one radio channel needs to change the reference frequency fr, the phase comparison frequency fpd, the reference oscillation frequency fr, and the frequency division number N should be appropriately selected according to the radio channel frequency. Thus, it is possible to generate an accurate first local oscillation frequency fIL1.

In such an embodiment, it is possible to prevent all the radio channels from being affected by the harmonics of the reference oscillation frequency, and the reference oscillation frequency fr has a variable width of about 50 ppm. By making it small, there is an advantage that it can be realized with a relatively simple circuit configuration.

Further, in the above embodiment, the reference oscillation frequency fr is varied by controlling the connection / non-connection of the capacitor C3 by the switch 11, but in addition, the reference oscillation frequency variable circuit is constructed as follows. May be.

First, in the synthesizer circuit shown in FIG.
Inverters 8a and 8b in the LLIC 73, crystal oscillators 9a and 9b, and capacitors C1a, C1b and C2.
Two independent sets of reference oscillators a and C2b are provided, and the oscillation frequencies of these reference oscillators are selectively switched by the change-over switch 12 and output.

Next, in the synthesizer circuit shown in FIG. 4, separate crystal oscillators 9a and 9b and a variable capacitor C are used.
1a and C1b are provided, and the inverter 8 and the capacitor C2 in the PLLIC 73 are shared by 2
One reference oscillator is provided, and the reference oscillation frequency generated from these reference oscillators is selectively switched by the change-over switch 13 and output.

Further, in the synthesizer circuit shown in FIG. 5, variable capacitors C1a and C1 serving as loads of the reference oscillator.
b is switched by the change-over switch 14 and is selectively connected to the crystal oscillator 9, whereby the reference oscillation frequency is switched.

Further, in the synthesizer circuit shown in FIG.
Crystal oscillator 9, transistor Tr, capacitors C1 to C
4 and the external reference oscillator consisting of resistors R1 and R2 are PL
When provided separately from the L circuit, the oscillation frequency varying capacitor 5 is connected in parallel with the capacitor C1 to the crystal oscillator 9 of the reference oscillator. The capacitor C5 is grounded when the switch circuit 15 in the PLLIC 75 is closed, so that the reference oscillation frequency value is variable.

In each of the above embodiments, the synthesizer circuit for generating the receiving local oscillation frequency is described, but the present invention can be similarly applied to the synthesizer circuit for generating the oscillation local oscillation no frequency. In addition, the circuit configuration of the reference oscillator, the circuit configuration for varying the oscillation frequency thereof, the configuration of the PLL circuit, the variable reference oscillation frequency value, and the like can be variously modified and implemented without departing from the scope of the present invention. .

[0038]

As described in detail above, according to the present invention, in the synthesizer circuit provided in the radio device for selecting a desired radio channel frequency from a plurality of radio channel frequencies and performing communication, the reference oscillation frequency changing means is provided. , A parameter changing means is additionally provided, and when a local oscillation frequency corresponding to a specific radio channel frequency is generated from the PLL circuit, the reference oscillation frequency changing means changes the reference oscillation frequency generated by the reference oscillator, and The parameter of the PLL circuit is changed by the parameter changing means to correct the change of the local oscillation frequency due to the change of the reference oscillation frequency.

Therefore, according to the present invention, it is possible to prevent the adverse effect of the harmonics of the reference oscillation signal from affecting the radio channel without increasing the power consumption and the cost, and thereby, all the signals within the communication allocation band can be obtained. It is possible to provide a synthesizer circuit that enables high-quality communication in the wireless channel and is suitable for a wireless device used in a wideband wireless communication system.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a receiving system of a digital wireless device including a synthesizer circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the configuration of the synthesizer circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a synthesizer circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a synthesizer circuit according to another embodiment of the present invention.

FIG. 5 is a circuit section showing a configuration of a synthesizer circuit according to another embodiment of the present invention.

FIG. 6 is a circuit section showing a configuration of a synthesizer circuit according to still another embodiment of the present invention.

FIG. 7 is a circuit block diagram showing a basic configuration of a synthesizer circuit.

FIG. 8 is a circuit unit showing an example of the configuration of a reference oscillator.

FIG. 9 is a circuit section showing another example of the configuration of the reference oscillator.

FIG. 10 is a diagram showing an example of an arrangement system of wireless channels.

[Explanation of symbols]

 1 ... Reference oscillator 2, 5 ... Divider 3 ... Phase comparator 4 ... Voltage controlled oscillator (VCO) 6 ... Loop filter 7, 71, 72, 73, 74, 75 ... PLLIC 8, 8a, 8b ... Inverter 9, 9a, 9b ... Crystal oscillator 11, 15 ... Switch circuit 12, 13, 14 ... Changeover switch 110 ... Antenna 120 ... Antenna duplexer (DUP) 130 ... High frequency amplifier 140 ... First mixer 150 ... Synthesizer circuit (SYN) 160 ... First intermediate frequency filter 170 ... Automatic gain control amplifier 180 ... Second mixer 190 ... Second local oscillator 200 ... Second intermediate frequency filter 210 ... Third mixer 220 ... Third local oscillator 230 ... Demodulator (DEM)

Claims (1)

[Claims] 1. A reference oscillator circuit for generating a reference oscillation frequency in a synthesizer circuit provided in a radio device for performing communication by selecting a desired radio channel frequency from a plurality of radio channel frequencies, and the reference oscillation circuit. A PLL circuit for generating a local oscillation frequency corresponding to the desired radio channel frequency based on a reference oscillation frequency generated by the circuit, and a local oscillation frequency corresponding to a specific radio channel frequency from the PLL circuit In this case, the reference oscillation frequency changing means for changing the reference oscillation frequency generated by the reference oscillator, and the reference oscillation frequency changing means for changing the reference oscillation frequency generated by the reference oscillator The parameter of the PLL circuit is corrected to correct the variation of the local oscillation frequency due to the variable frequency. Synthesizer circuit, characterized by comprising a parameter changing means for changing the over data.