JPH06259049A - Control system for crt display device - Google Patents

Abstract

PURPOSE:To make a device able to give various instructions body without increasing the number of interface signal lines by inserting digital data controlling a CRT display device to a blanking period of picture data of a picture data signal line. CONSTITUTION:A CRT display device 1 consists of a digital data separating circuit 11 for control, an electronic circuit 12 for control and a CRT 13, and an interface signal line 3 consists of a vertical synchronizing signal line, a horizontal synchronizing signal line and plural luminance signal lines. The ON period of a vertical synchronizing signal of this vertical synchronizing signal line is a fly-back period of a CRT, and this period is a blanking period in which a luminance signal is masked so that a fly-back line is not displayed on the CRT. Therefore, even if digital data is inserted to a luminance signal in the blanking period, the data is not displayed. Then, various digital data being instruction data for controlling the CRT display device can be inserted to a blanking period section of the luminance signal (video data signal).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to C of various information processing devices.
The present invention relates to control of an RT display device, and more particularly to a control method of a CRT display device capable of supplying various control data to the CRT display device without increasing the number of interface signal lines.

[0002]

2. Description of the Related Art In recent years, advances in semiconductor technology have made it possible to perform high-performance information processing, and further to improve the man-machine interface to realize an easy-to-use information processing apparatus. In the information processing apparatus, while the performance of the graphic display is improved, it is required that the application created for the low performance display operates in the same information processing apparatus. Therefore, for example, with the same display device, the resolution
The number of display devices capable of displaying different resolutions such as 640 x 400 dots or 640 x 200 dots is increasing. In addition, in order to meet the needs for power saving, even if the information processing device is powered on, when the display device of the information processing device is in a standby state, the resolution is lowered or the display function of the display device is lowered. Therefore, there is an increasing demand for a display device having a function of reducing power consumption of the display device. In addition, there are various requests to control the display device to realize multiple functions.

Under such circumstances, many proposals have been made for a control system for a CRT display device that meets the needs of realizing a plurality of resolutions on the same display device.
As one of the points to meet this demand, it is important not to increase the number of interface signal lines connecting the main body of the information processing device and the CRT display device. That is,
When the number of interface signal lines is increased, the size of the device is increased and the manufacturing cost is increased by increasing the size of the bundled wires and the number of connectors. Therefore, how to notify the display device of the switching of the resolution is an important issue. That is, how to notify the switching of resolution using the existing synchronization signal line and image data signal line.

As one of means for solving this problem, for example, there is a proposal described in Japanese Patent Laid-Open No. 61-100791. As shown in FIG. 7, this method uses image data signal lines (video signal lines).
The decision pulse is superposed during the blanking period of the image data (video signal) to notify the switching of the resolution. That is, the discrimination pulse superimposing means, the discrimination palace detecting means, and the resolution switching means are provided, and the resolution is A when the discrimination pulses are superposed, and the resolution is B when the discrimination pulses are not superposed. In addition, JP-A-61-
The means proposed in the publication No. 27585 is as shown in FIG.
The resolution of either A or B is designated and selected by reversing the polarity of the synchronization signal.

[0005]

However, as is clear from the above, the resolution of the conventional technique has been reduced to A.
Or you can only choose between B and B,
This is not applicable when a desired resolution is selected from three or more types as recently required. Further, when the display device is in the standby state, it has not been possible to meet the demand for putting the display device into a power saving state or giving various other instructions to the display device to control various display devices.

[0006]

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art as described above, and can give various instructions to the CRT display device from the outside and realize various controls without increasing the number of interface signal lines. It is an object to provide a control system for a CRT display device.

[0007]

[Means for Solving the Problems] To achieve the above object,
According to the present invention, in controlling a CRT display device having an interface signal line including a synchronization signal line and an image data signal line, digital data for controlling the CRT display device is supplied during a blanking period of image data on the image data signal line. Inserting the digital data for controlling the CRT display device during the blanking period of the required image data signal line in the control of the CRT display device having the interface signal line including the synchronization signal line and the plurality of image data signal lines. However, it is characterized in that a plurality of existing image data signal lines are used so as to insert a clock signal in the blanking period of other image data signal lines, and several kinds of control signals are transmitted.

[0008]

According to this method, since the digital data for controlling the CRT display device is inserted in the blanking period of the image data of the image data signal line, the digital data for controlling the CRT display device is inserted into the CRT display device without increasing the number of interface signal lines. Various instructions can be given from the information processing apparatus main body.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of a display device to which the present invention is applied. In the figure, reference numeral 1 is a controlled CRT display device, which is connected to an information processing apparatus main body, for example, a main body 2 of a personal computer by an interface signal line 3. The CRT display device 1 includes a control digital data separation circuit 11 and a control electronic circuit.
12 and CRT13. The interface signal line 3 is generally composed of a vertical synchronizing signal line, a horizontal synchronizing signal line, and one or more luminance signal lines (image data signal lines).

The period during which the vertical synchronizing signal on the vertical synchronizing signal line is ON corresponds to the retrace line of the CRT, and this period is C.
This is a so-called blanking period in which the luminance signal is masked so that a blank line is not displayed on RT. Therefore, even if digital data is inserted into the luminance signal (image data signal) in this blanking period, the data is not displayed. The present invention utilizes such characteristics to insert various digital data as instruction data for controlling the CRT display device in the blanking period portion of the luminance signal (image data signal).

FIG. 2 shows an example of the vertical synchronizing signal, the horizontal synchronizing signal and the luminance signal (image data signal). As described above, the period in which the vertical synchronization signal is on (the LOW period in the figure) is the blanking period of the luminance signal. FIG. 3 is a timing chart in which one cycle of the horizontal synchronizing signal indicated by the symbol t in FIG. 2 is enlarged and shown. In this example, the digital signal for controlling the CRT display device is inserted into the luminance signal (image data signal) at a cycle T in synchronization with the horizontal synchronizing signal (after a delay of T / 2 from the horizontal synchronizing signal). . Assuming that one piece of digital data per one cycle is 1-bit data, eight pieces of digital data, that is, 1-byte digital data can be inserted into bit serial in the period of 8T. It should be noted that the insertion of this digital data is performed in the information processing device main body 2. The sampling clock shown in FIG. 3 is a signal for separating the digital data inserted in the blanking period of the luminance signal as described later, and is generated by the control digital data separation circuit 11 as shown in FIG. This example is effective when there is only one luminance signal (monochrome).

FIG. 4 shows that there are two or more luminance signals (color).
7 is a timing chart of an example when the present invention is applied to a display device. In this example, the sampling clock shown in FIG. 3 is also generated by the information processing device main body 2, and is inserted as the luminance signal b shown in FIG. 4 into the blanking period of another luminance signal line and sent to the CRT display device 1. . The luminance signal a in FIG. 4 is digital data for display device control inserted during the blanking period. According to this embodiment, CR
There is an advantage that the control digital data separation circuit on the T display device side is simplified.

FIG. 5 shows an embodiment of the control digital data separation circuit 11 shown in FIG. In the figure, 21 is an n-bit shift register, 22 is a counter, and 23 is a switch. In the present circuit, even when the sampling clock is supplied from the counter 22 of the circuit by switching the switch 23, the information processing apparatus main body 2 is also supplied through the interface.
It is configured so that it can be used even when supplied from. The sampling clock is generated in this circuit by free running the counter 22 with a fast clock having a period of about 1 / (2n) of the period T and resetting with a horizontal synchronizing signal to establish synchronization. That is, while the horizontal synchronizing signal (LOW signal) is being input to the reset input terminal of the counter 22, the counter value is 0 and the horizontal synchronizing signal is HI.
Counting is started by a clock pulse input to the clock input terminal of the counter 22 from a clock source (not shown) after GH, and when the counter reaches n, LOW
If a sampling clock signal is extracted from the output terminal of the counter 22 that changes from HIGH to HIGH, the signal becomes HIGH during counting of the next n clocks, and LOW and HIGH
Is similarly repeated, it is possible to generate a sampling clock having a period T synchronized with the trailing edge of the horizontal synchronizing signal.

The n bit strings of the control digital data inserted in the blanking period of the luminance signal (luminance signal a) are likewise synchronized with the trailing edge of the horizontal synchronizing signal, and n in FIG. It is input to the shift input terminal of the bit shift register. Strictly speaking, as shown in FIG. 3, the leading edge of the first bit (data 1 shown in FIG. 3) of the control digital data comes after T / 2 from the trailing edge of the horizontal synchronizing signal. In order to realize the insertion of the control digital data at the above timing in the information processing apparatus main body 2, the same n as in FIG.
A circuit provided with a bit shift register and a counter may be used, and the illustration thereof is omitted. Prior to the transfer to the n-bit shift register 21 in the CRT display device 1, the control digital data to be transferred to the CRT display device 1 is set in the n-bit shift register in the information processing device body 2. At this time, the first bit (data 1 shown in FIG. 3) is located on the serial output end side of the n-bit shift register, and as in the case of the counter 22 shown in FIG. The first rising bit of digital data (data 1) is transferred to the CRT display device 1 by the rising clock with a delay of 1/2 (corresponding to the sampling clock of FIG. 5), and then n bits are generated by the rising clock of the cycle T. The data in the shift register is shifted and the control digital data for switching to the next data bit at the cycle T is successively input to the n-bit shift register 21 of the CRT display device 1. Therefore, as shown in FIG. 3, the sampling clock which enters the clock input of the n-bit shift register 21 from the counter 22 via the switch 23 (which is assumed to be switched to the B side at that time) has a falling edge as a control digital signal. It is located at the center of the data 1 to n, and by this fall, the control digital data bit string input to the n-bit shift register 21 is set in the n-bit shift register 21 and is shifted to the output side. The enable input of the n-bit shift register 21 is controlled as needed.

As a method of extracting the control digital data from the n-bit shift register 21 and finally controlling the CRT display device, there is a method of extracting the control digital data from the n-bit shift register 21 in parallel.
Generally, as shown in FIG. 6, the control digital data is fetched as a bit string from the shift register 21 of the control digital data separation circuit 11 into the microcomputer 31 and is controlled by the microcomputer 31. FIG. 6 shows a circuit that realizes power supply control, standby mode (power saving mode) control, screen position control, etc. using the microcomputer 31 by the control digital data. In the figure, 32 is C
An RT control circuit, 33 is a heater control circuit, and 34 is a power source.
That is, 31 to 33 correspond to the control electronic circuit 12 in FIG. The microcomputer 31 incorporates the control digital data into a RAM (not shown) in the microcomputer 31 via the I / O port 41 and is built in a ROM (not shown) in the microcomputer 31. The contents of the control digital data are decoded by software, and if the control digital data is the vertical synchronization frequency, horizontal synchronization frequency, screen position, brightness of the CRT display device,
For control of contrast or the like, the corresponding bit of the I / O port 42 in the microcomputer 31 is set to 1 to control the CRT control circuit for the corresponding item. Further, when the control digital data is in the standby mode (power saving mode) control and the power supply control, the corresponding bit of the I / O port 43 in the microcomputer 31 is set to 1 to control the power supply 34, / O port
Heater control circuit 33 by setting 1 to the corresponding bit of 42
To control.

[0016]

As described above, according to the present invention,
During the blanking period of the image data on the image data signal line,
By inserting various digital data for controlling the CRT display device, it is possible to give various instructions to the CRT display device from the information processing device body without increasing the number of interface signal lines. Various CRT display device controls can be realized at low cost. For example, by setting the CRT display device to the standby mode (power saving mode) according to an instruction from the information processing device main body, the CR
T power consumption of the display device is reduced, or multiple resolutions are switched, vertical / horizontal sync frequency control, screen position, brightness adjustment,
Many controls such as contrast adjustment can be performed.
Further, since the clock for separating the digital data in the CRT display device can be given from the information processing device main body, the circuit of the CRT display device itself becomes simple, which is effective in achieving low cost and miniaturization. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a display device according to the present invention.

FIG. 2 is a diagram showing an example of a timing chart of interface signals used in the present invention.

FIG. 3 is a timing chart for explaining an embodiment of the present invention.

FIG. 4 is a timing chart for explaining another embodiment of the present invention.

5 is a specific circuit diagram showing an embodiment of the control digital data separation circuit shown in FIG.

FIG. 6 is a block diagram showing an embodiment of the control electronic circuit shown in FIG.

7A and 7B are signal waveform diagrams for explaining an example of a conventional technique.

8A and 8B are signal waveform diagrams for explaining another example of the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CRT display device, 2 ... Information processing device main body, 3 interface signal lines, 11 ... Control digital data separation circuit, 12 ... Control electronic circuit, 13 ... CRT, 21 ... n-bit shift register, 22 ... Counter, 23 ... switch, 31 ... microcomputer, 32 ... CRT control circuit, 33 ... heater control circuit, 34 ... power supply.

Claims (5)

[Claims] 1. In a control of a CRT display device having an interface signal line including a synchronization signal line and an image data signal line, a digital control device for controlling the CRT display device during a blanking period of image data of the image data signal line. A control system for a CRT display device characterized by inserting data. 2. The control system for a CRT display device according to claim 1, wherein a plurality of digital data are inserted at equal time intervals during the blanking period of the image data of the image data signal line. 3. Control of a CRT display device having an interface signal line including a synchronizing signal line and a plurality of image data signal lines, wherein digital data for controlling the CRT display device during a blanking period of a desired image data signal line. CRT, and a clock signal is inserted during the blanking period of another image data signal line.
Display system control method. 4. A CRT to be inserted into the image data signal line.
A control system for a CRT display device, wherein digital data for controlling the display device is used as data for controlling power consumption of the CRT display device, and the CRT display device is set to a standby mode as necessary. 5. A CRT to be inserted into the image data signal line
The display device control digital data includes at least one of vertical control frequency, horizontal control frequency, screen position, brightness, contrast, and power control data of the CRT display device, and the CRT display device is controlled by the included data. The CRT according to claim 1, wherein
Display system control method.