JPH06242944A - Command execution circuit - Google Patents

Abstract

PURPOSE:To provide a command execution circuit provided with flexibility, extendability and realtime-ability while accelerating a processing speed. CONSTITUTION:This command execution circuit is provided with a command register 110 for storing command signals 201 from a host device, directory registers 120-123, comparators 130-133 for checking the contents of the command register 110 and the contents of output signals 124-127 from the directory registers 120-123, memories 140-143 for reading microinstructions for executing commands by coincidence signals 134-137 from the comparators, an OR circuit 150 for ORing the microinstructions and an arithmetic processing part 160 operated by microinstruction signals 151 from the OR circuit 150. The arithmetic processing part 160 reads data from a work memory 170 through a bus 180 by the microinstructions, performs processings and stores the data again in the work memory 170.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device having a configuration (slave) added to an information processing device serving as a host, and more particularly to a command execution circuit.

[0002]

2. Description of the Related Art Generally, in a system composed of a host device and a slave device, there are roughly two types of structures of the slave device.

One is an operating system (OS)
The slave device itself has a configuration capable of operating independently, and the other has a configuration that does not have a self-management function such as an OS and is controlled and operated by an instruction from the host device. Figure 1
4 shows a configuration in which a slave device having a conventional OS is incorporated. In this configuration, the host device 1 and the slave device 2 are connected by a line 3. When using such a slave device, it operates as follows.

First, the host device 1 issues a command to the slave device 2 via the line 3. The slave device 2 constantly monitors data, commands, and the like flowing on the line 3, receives a command issued from the host device 1, interrupts a CPU (not shown) in the slave device 2, and outputs the data. Recognize the reception of.

The slave device 2 analyzes the received data (command) and performs the instructed operation. Hardware for executing the corresponding command (H
If W) is incorporated, the HW operates. However, when there is no HW, a program that realizes the operation of the command is started.

After the command is executed, the code indicating the completion is notified to the host device 1 via the line 3. The slave device 2 also performs settings necessary for command processing, reset operation of each register after processing, resource management, and the like.

On the other hand, when a slave device having no OS is incorporated, it operates as follows. Here, this configuration is equivalent to the configuration shown in FIG. 14, and the slave device 2 is replaced with a device having no OS.

First, the host device 1 issues a command to the slave device 2 via the line 3. Since the central processing unit (CPU) (not shown) of the slave device 2 only has to execute the command, it does not need to take the form of interrupt and immediately analyzes and executes the command.

For such execution, a dedicated HW is provided and may be activated, or a program necessary for command processing may be activated. Depending on the command, the slave device 2 must perform necessary register setting and reset operation after processing by setting a dedicated command. Similarly, resource management must be executed with a dedicated command. Although different from the configuration shown in FIG. 14, the same applies to the case where a dedicated processing board is provided in the host device.

[0010]

However, when the above-mentioned slave device has an OS, the slave device itself performs resource management and timer processing of the slave device. Therefore,
The processing speed of the slave device must be sufficiently large for the signal to be processed. Actually, in consideration of image processing and the like, in order to secure a sufficient processing speed, a large computer with high processing capacity is used, or if it is a small computer, HW processing etc. is not implemented. And difficult. Further, in both cases, when a process that requires a long time is performed, a process by a timer or the like interrupts during the process, which causes a problem in real-time property.

On the other hand, in the case of a slave device that does not have an OS, it is preferable that all of them be HW and operated under the control of the host device, but it is difficult to make all the processes HW. Further, there is a problem in flexibility and expandability to make HW. Therefore, it is a general practice that the processing is performed in order from the one with the strictest requirement for the processing speed, and the other processing is executed by the program.
HW processing is good, but when processing is done by program,
Processing such as command analysis and program loading is required, and this processing may affect real-time processing. Therefore, an object of the present invention is to provide a command execution circuit having flexibility, expandability, and real-time property while increasing the processing speed.

[0012]

In order to achieve the above object, the present invention stores an upper level instruction consisting of a command from a host in an information processing device configured to be added to a host device to perform processing. A first command register, a plurality of directory registers for storing previously executed higher level instructions, and the information processing apparatus for executing the upper level instructions stored in the directory registers corresponding to the directory registers. A memory for storing a lower-level instruction composed of instructions;
And a comparator for comparing the upper level instruction of the command register with the upper level instruction of the directory register. When executing the upper level instruction, the comparator compares the two upper level instructions. , A command execution circuit for reading and executing a lower level instruction from the corresponding memory is provided.

[0013]

[Operation] With the command execution circuit having the above configuration,
The upper level instruction stored in the directory register is immediately put into execution by the lower level instruction at the output of the memory.

That is, the command signal from the host device is stored in the command register, the contents of the command register and the contents of the output signal from the directory register are checked by the comparator, and the memory is determined based on the coincidence signals from the comparators. From which micro-instructions to execute the command are read. The arithmetic processing unit is operated by the microinstruction signal, data is read from the work memory through the bus, processed, and stored again in the work memory.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, the command execution circuit of the present invention will be outlined. In order to process a signal or the like from the outside in real time, it is preferable to have a processing unit that simply executes only a command, in addition to a processing unit required as an apparatus.
This command processing unit executes only low-level instructions necessary for executing the command at high speed. Therefore, it is preferable to store the low-level instructions for all commands in one memory having a sufficient capacity and execute the instructions, after storing them in the small-capacity high-speed memory for easy control. . Further, instead of having no OS function, it has some expandability.

FIG. 1 is a block diagram of the entire system including a slave device using the command execution circuit of the present invention. In FIG. 1, the slave device 100 is a host device 200.
And a signal generator 300 that generates a signal to be processed. The signal generator 300
The signal generated by the slave device 100 is processed by the slave device 100,
It is returned to the signal generator 300 again. Next, FIG. 2 is a block diagram showing a specific configuration of the slave device 100 described above.

In this slave device 100, the command signal 201 from the host device is transmitted to the command register 11
Stored in 0. The command register 110 includes the directory registers 120 to 123, the contents of the command register 110 and the directory registers 120 to 12
The comparators 130 to 133 for checking the contents of the output signals 124 to 127 from the H.3 are connected. These comparators 1
As a result of the comparison of 30 to 134, when they match, the match signals 134 to 137 consisting of “1” are output to the memories 140 to 143 corresponding to the directory registers, respectively.

The memories 140 to 143 store microinstructions for executing the commands stored in the command register 110. Further, the memories 140 to 143 have an address generating circuit built therein, and the coincidence signals 134 to 137 are "
When it is "1", the memories 140 to 143 output data while automatically incrementing the address.

On the other hand, the coincidence signals 134 to 137 are "
When it is "0", the memories 140 to 143 output "0". The microinstruction signals 144 to 147 are outputs of the microinstructions from the memories 140 to 143.

However, in this embodiment, in order to facilitate the explanation, the circuit is simplified and the following conditions are added when the micro instructions are stored in the memories 140 to 143. When storing a microinstruction, the inside of the memory is once cleared to "0" and writing is performed for the required number of words. Therefore, "0" is written in places where no writing is performed.
Holds the data of. The memory size is one larger than the maximum number of written microinstructions.

As a result, at least one word is "at least one word after the microinstruction is written in executing any command.
It holds the value of 0 ". Also, the micro instruction is
It is assumed that the description is made without branching.

And, in the memories 140 to 143,
The bitwise logical sum of the read microinstructions 144 to 147 is processed by the logical sum circuit 150. In these memories 140 to 143, the coincidence signals 134 to 137 are "
Micro-instruction is output only for 1 ", and other than"
0 "is output. Therefore, the memories 140 to 143 are output.
If only one of them outputs a coincidence signal, the OR circuit 150
The output signal 151 of 1 is to output the micro instruction issued by any of the memories 140 to 143 as it is.

Further, the coincidence signals 134 to 137 are simultaneously 2
It is ensured that the same command is not stored in the directory registers 120 to 123 at the same time (the directory register 12).
Even if the same command exists in 0 to 123, the memory 1
There is no problem because the same microinstruction is stored in 40 to 143, but this is not possible in this embodiment).

The arithmetic processing section 160 operates according to the micro command signal 151. The arithmetic processing unit 160 reads the data from the work memory 170 through the bus 180 according to the micro instruction, performs the process, and stores the data in the work memory 170 again. When the micro instruction 151 is “0”, the arithmetic processing unit 160 outputs the signal 10
Set 1 to "1". This is the host device 20 shown in FIG.
It becomes a permission signal for issuing the next command to 0. When the host device 200 detects that the signal 101 has changed from "0" to "1", it issues one command.

Simultaneously with the change of the signal 101, the arithmetic processing section 160 sets the signal 162 to "1", and the comparators 130-
Reference numeral 134 detects a change in the signal from "0" to "1" and sets the signals 134 to 137 to "0". And signals 101,1
62 is "when the micro instruction 151 is not" 0 ""
Changes to 0 ".

When the contents of the command register 110 and the contents of the directory registers 120 to 123 do not match, the match signals of the comparators 130 to 133 are put together and transmitted as an output signal 138 to the arithmetic processing section 160. . Inside the arithmetic processing unit 160, a command from the host device is checked, and the microinstruction storage memory 17
The ROM 165 stores a routine for transferring the microinstruction necessary for command processing from the memory 1 to the memories 140 to 143, and the signal 138 activates this routine.

Then, the arithmetic processing section 160 receives the signal 11
1, the command is checked, and the corresponding microinstruction is stored from the microinstruction storage memory 171 into any of the memories 140 to 143 through the bus 180. Which one is stored is determined by performing LRU control in the directory registers 120 to 123. After the transfer of the micro instruction is completed, the contents of the command register 110 are stored in any of the corresponding directory registers 120 to 123.

The signal to be processed is the output signal 301 from the signal generator 300 shown in FIG.
The signal is received by the transmission / reception / signal converter 190, converted into an appropriate signal, and then stored in the work memory 170. The output signal 191 from the transmission / reception / signal converter 190 is a signal for notifying the arithmetic processing unit 160 of the reception timing.
The signal stored in the work memory 170 is transferred to the bus 18
It is read out to the arithmetic processing unit 160 through 0, processed, and then stored again in the work memory 170. The processed signal is read by the transmission / reception / signal converter 190, converted into a signal suitable for the signal generator 300, and then the signal 10
2 is output to the signal generator 300.

Next, the operation will be described by setting a specific numerical value in the embodiment thus constructed. FIG. 3 shows the command register 110 and the directory registers 120 to 123.
And LRU values are shown. FIG. 4A shows the relationship of the LRU control of the directory registers 120 to 123.
(B) shows the relationship between the LRU value and the selected directory register. In FIG. 4A, the direction corresponding to the arrow is represented by "1". First, bit n is LR
Let us denote it by U (n). Directory register 120
Represents LRU (0), LRU (1), LRU (2)
And the value is (LRU (0), LRU (1), LRU (2)) =
When (0,0,0), the directory register 120 is selected. The bit value starts with an initial value of all "0", and is replaced so as to point to a directory register opposite to the matched directory register.

The value of the command register shown in FIG. 3 has just been updated and will be described as being executed. Memory 1 since the previous command has just been executed
The outputs of 40 to 143 are “0”, and the arithmetic processing unit 160
The microinstruction signal 151 given to is also "0".

Therefore, the signals 101 and 162 are "1".
Is output as. In response to this, the coincidence signal 134-
The value of 137 is “0”. Signal 101 "
The command issued by the host device 200 due to the change from 0 "to" 1 "is that of the command register 110 shown in FIG.

The contents of the command register 110 are "
6A00 ″. This value is used as the signal 111 by the comparator 1
Passed to 30-133. The comparators 130-133 output the output signals 124- of the directory registers 120-123.
Compare with 127. The directory register 12
Since the content of 1 is "6A00", only the comparator 131 detects a match. As a result, only the signal 135 of the signals 134 to 138 generated by the comparators 130 to 134 is obtained.
1 "is output.

Subsequently, the memory 141 starts issuing microinstructions. The memories 140, 142, 143 output "0". Signals 144 to 1 by the OR circuit 150
47 performs a logical sum for each bit and is given to the arithmetic processing unit 160 as a signal 151.

Since the signal 151 is not "0", the values of the signals 162 and 101 change from "1" to "0". Then, the arithmetic processing unit 160 reads the data from the work memory 170 according to the micro instruction, performs the processing, and then stores the result in the work memory 170 again.

Since at least one word "0" is stored in the memories 140 to 143 after the microinstruction necessary for the command, the memory 141 outputs "0" when the valid microinstruction is completed. This completes the execution of the command register 110. Arithmetic processing section 160
Signals 151, 16 because the signal 151 has become "0"
2 changes from "0" to "1", the command issuance permission is issued to the host device 200, and the signal 135 is changed to "0".
To reset the command execution circuit itself to the initial state.
FIG. 5 shows a command issued next after the above-mentioned processing.

The command from the command register 110 becomes "1B03". The other registers have not changed from the states shown in FIG. The new command is passed to comparators 130-133 as signal 111 and compared with the contents of directory registers 120-123. Since there is no match, the signals 134 to 137 remain “0” and the mismatch signal 138 becomes “1”.

As a result, the arithmetic processing section 160 recognizes that the command stored in the command register 110 is not in the directory register. The arithmetic processing unit 160 is R
Activates micro-instruction stored in OM165, signal 1
11, the command is checked, the corresponding microinstruction is read from the microinstruction storage memory 171, and the LR
It is stored in the memory 142 corresponding to the directory register 122 designated by U.

When the transfer to the memory 142 is completed, a signal 161 notifies the directory register section of the completion,
As a result, the contents of the command register 110 are stored in the directory register 122, and each bit of LRU is updated.

FIG. 6 shows a state in which each bit of the LRU is updated. Since the directory register 122 is updated, the contents of the command register 110 are matched, and the processing is performed as described above. By repeating the above operation, the commands issued by the host device 200 are sequentially executed.

Next, FIG. 7 shows the configuration of a command execution circuit as a second embodiment according to the present invention, which will be described. Here, of the constituent members shown in FIG. 7, the same members as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 7, there are subdirectory registers 400 to 403 corresponding to the directory registers 120 to 123.

A high speed memory 4 for storing microinstructions
20 and output signals 404 to 407 of the subdirectory registers 400 to 403, a circuit 410 for controlling the memory 420 is provided. The memory 420 stores micro-instructions for executing the commands stored in the directory registers 120 to 123. The sub-directory registers 400 to 403 store the start address and the number of words of the microinstruction for executing the command. When the comparators 130 to 133 detect a match, the corresponding signals of the match signals 134 to 137 change to "1". As a result, the content of the corresponding subdirectory register is transmitted to the control circuit 410.

The control circuit 410 increments the supplied address as a start address by the number of words to generate an address, and as a signal 411, the memory 42.
Access 0. In response to this, the memory 420 continues to give a micro instruction to the arithmetic processing unit 160. Further, the control circuit 410 accesses address 0 of the memory 420 when the addresses for the number of words are generated. “0” is always stored in the address 0 of the memory 420, and the memory 420 stores the micro-instruction whose code is all “0” in the arithmetic processing unit 16.
Output to 0.

The subsequent operation is the same as in the first embodiment. At the same time, the control circuit 410 controls the L of the directory register section.
The directory register to be updated next is known from the value of RU, and the area of the corresponding memory 420 is organized. The memory 420 is rearranged so that the microinstruction of a command that has not been executed is moved so that there are many unstored areas behind the area where the microinstruction to be updated next is stored. The new start address is transmitted to the subdirectory registers 400 to 403 by the signal 412.

When the comparators 130 to 133 detect the non-coincidence, the signal 138 becomes "1" and the arithmetic processing unit 160 is notified. The arithmetic processing unit 160 is a ROM 165.
The micro-instruction stored in the memory is started, the start address of the area of the memory 420 for storing the micro-instruction is known by the signal 413, and the necessary micro-instruction is transferred. Upon completion, the signal is sent to the directory register section by the signal 161, and the corresponding directory register, sub-directory register and LRU are updated.

Next, FIG. 8 shows a specific structure of a command execution circuit as a third embodiment according to the present invention, and will be described. In this embodiment, a plurality of command registers are provided and serially connected, and the command register at the subsequent stage (close to the host device) detects a match with the directory register. Here, the components shown in FIG. 8 which are equivalent to those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

In this command execution circuit, a command register 115 is newly added. By the output of the command register 115, a match with the directory register is checked. The command currently being executed is stored in the command register 110.

The processing unit of this embodiment is an arithmetic processing unit 1 for executing microinstructions purely for command execution.
64 and microinstruction transfer unit 1 for transferring microinstructions
Divided into 63. The signal 179 is for transmitting the value of the LRU, and the microinstruction transfer unit uses the disagreement signal 138.
Becomes "1", the LRU value and the command register 115
Depending on the contents of, the necessary microinstruction is transferred to the corresponding memory. By setting the signal 172 to "1" during the transfer execution, the arithmetic processing unit 164 recognizes that the micro instruction transfer is in progress. The comparison results of the comparators 130 to 133 are output to the flags 166 to 169. When the command register, the directory register and the flag are updated, the signals 101 and 161 indicating that the previous command has finished are "0".
It is performed when the value changes from "1" to "1". Next, the operation of the command execution circuit shown in FIG. 8 will be described by setting specific numerical values as shown in FIG.

It is assumed that the command register, directory register, LRU, and flags 166 to 169 are currently in the state shown in FIG. The command being executed is “6A00” stored in the command register 110. This command matches the directory register 121, and the corresponding flag 167 is in the state of "1". In this state, the signal 176 shown in FIG. 8 becomes "1", the memory 141 outputs the micro instruction, and the arithmetic processing unit 164 is executing the process. The comparators 130 to 133 compare the contents of the directory registers 120 to 123 with the contents of the command register 115, and the result matches the value of the directory register 122. Therefore, after the command "6A00" is completed, the directory register and the memory are not updated, and only the flag and the LRU bit are updated.

The command "6A00" is stored in the memory 14
It ends when the output of 1 becomes "0". In the above-described embodiments, when recognizing that the output of the memory 141 has become "0", the arithmetic processing unit changes the signals 101 and 161 to "1" and notifies the host device 100 and the directory register unit. In the third embodiment, the transfer of microinstructions, which may be in parallel, must be completed in order to execute the next command.

The arithmetic processing unit 164 is configured such that the output from the memory 141 is "0" and that the micro instruction transfer unit 1
When the two conditions that the output signal 172 from 63 is "0" are satisfied, the end signals 101 and 161 are set to "1".
Change to. As a result, the host device 100 issues a new command, and the respective bits of the flag and LRU are updated. FIG. 10 shows the updated state.

The command newly issued from the host device 100 is "1B06". Since this command does not match the contents of the directory registers 120 to 123, it is necessary to read the micro instruction. Signal 1
38, the microinstruction transfer unit 163 is notified of the mismatch. Upon receiving this notification, the micro instruction transfer unit 163 sets the signal 172 to "1" and activates the micro instruction of the ROM 150. The command is confirmed by the signal 172, and the necessary microinstruction is transferred. The memory of the transfer destination is the memory 143 from the value of LRU.

When the micro instruction transfer is completed, the micro instruction transfer section 163 sets the signal 176 to "0".
When the command execution is completed, the output of the memory 142 is "
0 ”, and the arithmetic processing unit 164 outputs the signals 101 and 161.
To "1". As a result, the host device 100 issues a command, and the directory register, LRU, and flag are updated. This state is shown in FIG.

Next, FIG. 12 shows a specific configuration of the command execution circuit as a fourth embodiment of the present invention and will be described. Here, of the constituent members shown in FIG. 12, the same members as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted.

In this command execution circuit, command registers 110, 115 and 119 are provided as compared with the first embodiment.
3 are added. This command register 119
Is provided with a tag 173 indicating the context of the command. The tag 173 does not depend on the execution result of the immediately preceding command, and has a value of "1" only when the execution of the own command first does not affect the execution of the command whose result has passed. The outputs of the command registers 115 and 119 are selected by the selector 118. The output of the command register 115 is the signal 116, and the comparators 130-
It is sent to 133. The output of command register 119 is signal 117, which is transmitted to comparators 130-133.

These comparators 130 to 133 first compare the signal 116 with the contents of the directory registers 120 to 123. The comparators 130-133 then output the signal 117.
And the contents of the directory registers 120 to 123 are compared. If the signals 116 match, the command in the command register 110 is executed, and then the command in the command register 115 is executed, as described in the third embodiment. When the contents of the directory registers 120 to 123 and the signal 116 do not match and the signal 117 does match, the following operation is performed.

The value of the tag 173 is transmitted by the same signal 117 as the command. The comparators 130 to 133 check the tag value. If the value is "1", the command stored in the command register 115 is overtaken and the command stored in the command register 119 is executed. Therefore, the selector 118 is switched to the output signal 117 of the command register 119 according to an instruction from the comparator.

After the execution of the command in the command register 110 is completed, the command stored in the command register 119 is stored in the command register 110, and the flags 166 to 169 and LRU are updated to the corresponding values.

A new command and tag are sent from the host device 200 shown in FIG. 1 and stored in the command register 119. While the command previously stored in the original command register 119 is being executed, the command register 11
Transfers micro-instructions necessary to execute the command stored in 5.

The processing of the other blocks is the same as the previous example.
The setting of the tag 173 is performed by the host device 200, but once the order of command execution is changed, it is necessary to reset the tag value of the subsequent command. This is done by the host device 200 in anticipation of replacement, or by the command register 1
It can be done by either giving it to 19.

Next, FIG. 13 shows a configuration of a command execution circuit as a fifth embodiment according to the present invention, which will be described. The tag 174 shown in FIG. 13 stores the number of times the command has been executed, unlike the tag of the fourth embodiment described above. This tag 17
The contents of 4 are issued together with the command from the host device 200 shown in FIG. The content of the tag 174 is transmitted to the control circuit 410.

The control circuit 410 has a memory 42 for executing the commands stored in the command register 110.
0 is controlled, but the subdirectory register 400-
Based on the start address and the number of words given by 403, the micro instructions for the number of words are read from the start address for the number of times designated by the tag 174. Then, after repeating the designated number of times, all 0s, which is the data at the address 0 of the memory 420, are output, thereby ending the command execution. The processing of the other blocks is the same as the above-mentioned fourth step.
It is similar to the embodiment.

With the command execution circuit having the above configuration, the upper level instruction stored in the directory register is immediately executed by the lower level instruction output from the memory. This eliminates the time to decode the upper level instruction and read the lower level instruction from the main memory to execute it.

Further, in the command execution circuit of the present invention, a subdirectory register and a submemory corresponding to the directory register are provided in place of the memory corresponding to the plurality of directory registers, and the subdirectory register is stored in the directory register. The address and the number of words of the sub memory in which the lower level instruction group for executing the upper level instruction is stored are stored.

When the comparator detects that there is a match, the contents of the corresponding subdirectory are called, the submemory is accessed with the read contents, and the lower level instruction is executed.

As described above, by adding the sub-directory register to the command execution circuit, the sub-memory for storing the lower level instruction can be constructed as one memory. In other words, it is necessary to provide one memory for each of the directory registers, or to divide one memory by assuming a certain size so that the memory can be used more efficiently. Will get better.

In the command execution circuit of the present invention, the command register n for storing the higher level instruction subsequent to the command register stored in the command register.
A comparator n for comparing (n = 2, 3, ...) With the contents of the command register n and the directory register is provided. Thus, when the upper level instruction stored in the command register is being executed, the content of the command register n is checked, and if it is not in the directory register, the upper level instruction executed before the execution of the own instruction is executed. By rewriting the memory, sub-directory, etc., which are not stored and correspond to the directory register, to the necessary contents, the processing efficiency can be improved and the matching rate with the contents of the directory register can be increased.

Further, a tag indicating the relationship before and after the upper level instruction stored in the command register n is provided,
When a mismatch occurs between the command register n and the contents of the directory register A, the tag is checked, and the subsequent instruction of the instruction that is not related is executed first. This is because if lower-level instructions continue to be read due to a mismatch and execution of commands stops, the commands in the directory register that have no relation to the subsequent commands are executed first, and processing efficiency is improved. Is improved.

When the upper level instruction is repeatedly executed, a necessary tag is provided in the subdirectory and the lower level instruction can be repeated as many times as necessary based on the output of the subdirectory so that the upper level instruction can be repeated. it can. By changing the setting of the tag of the sub-directory register in this way, expandability is provided. Therefore, by using the command execution circuit of the present invention, a slave device suitable for real-time processing can be created. Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications and applications can be made without departing from the scope of the invention.

[0070]

As described in detail above, according to the present invention, it is possible to provide a command execution circuit having flexibility, expandability and real-time property while increasing the processing speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an entire system including a slave device using a command execution circuit of the present invention.

FIG. 2 is a block diagram showing a specific configuration of the slave device shown in FIG.

[FIG. 3] Command register, directory register, and L
It is a figure which shows a RU value.

FIG. 4A shows a directory register 120-.
123 shows the relationship of the LRU control of 123, and FIG.
It is a figure which shows the relationship between a U value and the directory register selected.

FIG. 5: Command register, directory register and L
It is a figure which shows a RU value.

FIG. 6 is a diagram showing a command register, a directory register, and an LRU value in which each bit of LRU is updated.

FIG. 7 is a block diagram showing a configuration of a command execution circuit as a second embodiment according to the present invention.

FIG. 8 is a block diagram showing a configuration of a command execution circuit as a third embodiment according to the present invention.

FIG. 9: Command register, directory register and L
It is a figure which shows a RU value.

FIG. 10 is a diagram showing a command register, a directory register, and an LRU value.

FIG. 11 is a diagram showing a command register, a directory register, and an LRU value.

FIG. 12 is a block diagram showing a configuration of a command execution circuit as a fourth embodiment according to the present invention.

FIG. 13 is a block diagram showing a configuration of a command execution circuit as a fifth embodiment according to the present invention.

FIG. 14 is a block diagram showing a configuration in which a slave device having a conventional operation system is incorporated.

[Explanation of symbols]

1,200 ... Host device, 2,100 ... Slave device,
3 ... Line, 101, 111, 138, 161, 172
176, 179 ... Signal, 110, 115, 119 ... Command register, 116, 301 ... Output signal, 120-1
23 ... Directory register, 124-127 ... Output signal, 130-133 ... Comparator, 134-137 ... Comparison signal, 138 ... Mismatch signal, 140-143 ... Memory, 1
44 to 147, 151 ... Micro instruction signal, 150 ... Logical sum circuit, 151 ... Output signal, 160, 164 ... Arithmetic processing section, 163 ... Micro instruction transfer section, 166-169 ...
Flag, 170 ... Work memory, 171 ... Microinstruction storage memory, 173, 174 ... Tag, 180 ... Bus, 1
90 ... Transmission / reception / signal converter, 201 ... Command signal, 3
00 ... Signal generator.

Claims (1)

[Claims] 1. An information processing apparatus configured to be added to a host device and configured to perform processing, comprising: a first command register for storing an upper level instruction consisting of a command from a host; and an upper level instruction executed last time. A plurality of directory registers to be stored; a memory corresponding to the directory registers; And a comparator for comparing the upper level instruction of the command register with the upper level instruction of the directory register. When executing the upper level instruction, the comparator compares the two upper level instructions. , If they match, read the lower level instruction from the corresponding memory, Command execution circuit, characterized in that the rows.