JPH06237147A - Method and device for applying adapting processing to active filter - Google Patents

Abstract

PURPOSE:To reduce a residual error by reducing a convergence time of a coefficient arithmetic operation of the adaptive filter corresponding to a response waveform of an impulse response of an identification system of a communication channel from which a fixed delay component is excluded. CONSTITUTION:A tap control circuit 61 is provided with a storage circuit 83 storing a tap control group number, an output circuit 82 outputting an upper limit and a lower limit of a tap number of a selected group, a maximum tap retrieval circuit 81 retrieving a tap coefficient whose absolute is maximum for each control group and outputting the retrieved maximum tap coefficients in the larger order, a counter circuit 84 commanding revision of the tap control group number to the storage circuit 83 every time the number of revision times of a tap coefficient reaches a predetermined number of times, a counter circuit 85 outputting a revision signal of the order of control groups every time the number of command signals counted by the counter circuit 84 reaches a predetermined count, and a control group revision circuit 86 writing the tap control group number outputted from the maximum tap retrieval circuit 81 into the storage circuit 83 by the command of the counter circuit 85.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for adapting an adaptive filter used to fix an unknown system on a transmission line.

[0002]

2. Description of the Related Art Echo cancellers, noise cancellers, howling cancellers, adaptive equalizers, and the like are known as devices to which an unknown system of a transmission line is fixed by an adaptive filter. Here, a conventional technique will be described by taking an echo canceller that removes an echo leaking from a transmission circuit to a reception circuit on the 4-line side of a 2-line / 4-line conversion circuit as an example. Echo cancellers are adaptive adaptive filters with tap coefficients longer than the impulse response length of the echo path.
Operates to suppress the echo leaking from the transmission circuit to the reception circuit on the 4-wire side of the 2-wire / 4-wire conversion circuit by generating a corresponding pseudo echo (echo replica) of the transmission signal using a filter. To do. At this time, adaptive
Each tap coefficient of the filter is corrected by taking the correlation between the error signal obtained by subtracting the echo replica from the mixed signal in which the echo and the received signal are mixed, and the transmitted signal. As a typical example of such a coefficient correction of the adaptive filter, that is, a convergence algorithm, "LMS ALGO
RITHM "(PROCEEDINGS OF IE
EE 63 Volume 12, 1975, 1692-1716
See page; "Reference 1" below) and "LEARING.
IDENTIFIATION METHOD; LI
M "(IEEE TRANSACTION AU
TOMATIC CONTROL Volume 12, No. 3, 196
7 pages, pp. 282-287; hereinafter referred to as "reference 2").

By the way, when there is a fixed delay between a point on the 4-wire line where the echo canceller is actually inserted and a point on the 4-wire / 2-wire conversion circuit, the tap number of the echo canceller is assumed. It requires a maximum fixed delay amount and a length that sufficiently covers the response waveform portion of the substantial impulse response. Therefore, when the assumed fixed delay amount is large, the tap length becomes enormous, and the increase in the number of taps increases the mutual interference between the coefficients, resulting in an increase in the convergence time. Moreover, since the tap coefficient memory and the multiplier of the adaptive filter increase, the cost increases.

In order to solve the above-mentioned problems, the position of the substantial response waveform part excluding the fixed delay part of the impulse response of the echo is estimated, and adaptive position around the estimated position is estimated.
"A FAST CONVERGENE AL" that controls the tap position so that the tap coefficient of the filter is arranged
GORITHM FOR ADAPTIVE FIRF
ILTERS WITH COARSELY LOCA
TED TAPS "(PROCEEDINGS OF
INTERNATIONAL CONFERENCE
ON ACOUSTICS, SPEECH AND S
IGNL PROCESSING 1991, 1991
Year, see pages 1525 to 1528; hereinafter "Reference 3")
Is proposed.

FIG. 3 is a block diagram showing the configuration of the echo canceller proposed in "Document 3". The adaptive filter shown in FIG. 3 includes delay circuits 20 ₁ to 2 that delay the transmission signal input from the transmission signal input terminal 1.
The adaptive filter has (N-1) delay circuits up to 0 _N-1 , and the total number of taps including the delay "0" taps is N taps. On the other hand, the coefficient updating circuit for calculating the tap coefficient of the adaptive filter includes L circuits from the coefficient updating circuits 50 ₁ to 50 _L ,
There is a relation of N> L between the total number N of taps of the adaptive filter and the number L of coefficient updating circuits. That is, unlike the conventional adaptive filter, the adaptive filter shown in FIG. 3 has a number of tap coefficients that can represent a substantial response waveform portion excluding the fixed delay portion, and the tap coefficient is used as the response waveform. A pseudo echo is generated by adaptively arranging the parts. Therefore, the tap switching circuit 7 that switches the connection between the output of the delay circuit and the coefficient updating circuit 7
For controlling the tap switching circuit 7,
It has a tap control circuit 60. The respective outputs of the tap switching circuit 7 are supplied to the corresponding coefficient updating circuits 50 ₁ to 50 _L and the multiplication circuits 40 ₁ to 40 _L. Multiplier circuits 40 ₁ to 4
0 _L multiplies the tap coefficient values output from the coefficient update circuits 50 ₁ to 50 _L by the delay signal output from the tap switching circuit, and supplies the result to the adder circuit 5. The adder circuit 5
The multiplication results of the multiplication circuits 40 ₁ to 40 _L are added and output as a pseudo echo. The transmission signal input to the transmission signal input terminal 1 is transmitted from the transmission signal output terminal 2 to the transmission line,
Although it is sent to the 2-wire side in the 2-wire / 4-wire conversion circuit 8, part of the transmission signal leaks to the reception side as an echo signal due to impedance mismatch. The echo signal input from the reception signal input terminal 3 is input to the subtraction circuit 6. The subtraction circuit 6 subtracts the pseudo echo output from the addition circuit 5 from the echo signal, and the reception signal output terminal 4 as an echo removal signal.
And is supplied to the coefficient updating circuits 50 ₁ to 50 _L as an error signal for coefficient updating.

Here, the internal operation of the coefficient update circuits 50 ₁ to 50 _L will be described. FIG. 4 shows a coefficient updating circuit 50 _X (x =
1, 2, ..., L) is a block diagram showing an internal configuration.
In FIG. 4, X is a delay signal, M is a coefficient update step size, E is an error signal, C is a coefficient clear signal, and W is a tap coefficient value. Here, the "LMS algorithm" shown in "Document 1" is assumed and described as the coefficient updating algorithm. The delay signal X and the error signal E are multiplied by the multiplication circuit 51, and further multiplied by the step size M output from the control circuit 60 by the multiplication circuit 52. The multiplication result of the multiplication circuit 52, which is a correction term of the tap coefficient, is added to the pre-updated tap coefficient value stored in the delay circuit 54 by the addition circuit 53, and the updated filter coefficient value is newly provided to the delay circuit 54. Is entered. The value stored in the delay circuit 54 is output as the tap coefficient value W. The delay circuit 54 has a function of forcibly reducing the coefficient value held therein to zero when the coefficient clear signal C is input from the control circuit 60. As described above, the tap coefficients of the adaptive filter are connected only to some of the taps selected by the tap switching circuit 7. Hereinafter, taps with tap coefficients connected will be called valid taps, and taps that are not connected will be called invalid taps. Next, the operation of the tap control circuit 60 that controls the tap switching circuit 7 and generates the coefficient clear signal will be described.

In the adaptive filter of FIG. 3, there are two operating states. The determination circuit 78 determines the operating state based on the input and outputs the result to the switch 79 and the selector 8
0 is being supplied. Here, the information indicating the operating state is
There are two types, “0” and “1”, and the state when “0” is called “first state” and the state when “1” is called “second state”. If the “first state” is the initial state, the output of the determination circuit 78 is “0”. The switch 79 is configured to be off when the signal supplied from the determination circuit 78 is “0” and on when the signal is “1”. Further, the selector 80 selects μ ₁ in the “ _first state” and
It is configured to select μ ₂ in “state of”. μ ₁ , μ ₂
Is a constant that satisfies μ ₁ <μ ₂ . Therefore, in the initial state, μ ₁ is selected as the step size and is supplied to the coefficient updating circuit.

The memory circuit 70 includes a FIFO (First-
In-First-Out) storage circuit,
The (N−L) invalid tap numbers are stored. However, N is the total number of taps, and L is the number of effective taps. The tap calculation circuit 73 calculates a tap number obtained by removing the invalid tap number stored in the storage circuit 70 from all tap numbers, that is, a valid tap number, and supplies the tap number to the tap switching circuit 7 as a tap switching control signal. The tap switching circuit 7 operates so as to select the output of the delay circuit corresponding to the L effective tap numbers received from the tap calculation circuit 73 and output it to the coefficient updating circuit. Invalid tap number in the initial state,
That is, the initial setting values of the memory circuit 70 are selected so that the valid taps are evenly spaced. For example, the total number of taps N is 1
3, valid tap number L is 5, invalid tap number (NL) is 8
When all are selected, all tap numbers are 1, 2, 3, ..., 13. At this time, the effective tap numbers are 1, 4, 7, 10,
The invalid tap numbers held by the memory circuit 70 are 2, 3, 5, 6, 8, 9, 1 in order to make the intervals equal to 13.
Initially set to 1,12.

After the above initial state is set, the tap coefficient of the tap (valid tap) selected by the tap switching circuit 7 is updated. The maximum tap search circuit 75 is
Each time the coefficient is updated, the tap coefficient value output from each coefficient update circuit and the valid tap number output from the tap calculation circuit 73 are received, and the valid tap number corresponding to the tap coefficient having the maximum absolute value is controlled with the storage circuit 77. It is supplied to the tap output circuit 76. The storage circuit 77 stores the latest P number (P is a predetermined positive constant) of the tap numbers that are continuously input, and transmits all of them to the determination circuit 78 collectively. The determination circuit 78 changes the output from “0” to “1” when the appearance probability of the one having the highest appearance frequency out of the P tap numbers exceeds a predetermined set value P _TH , and the echo canceller The operating state of "from the first state" to the "second state"
Change to. As described above, the purpose of the operation of the “first state” described above is at the effective tap positions distributed at equal intervals,
It is to estimate the approximate position of the substantial response waveform portion by continuously performing coefficient updating using a small step size and continuously detecting the tap position corresponding to the coefficient having the maximum absolute value. Next, the operation of the “second state” will be described.

When the output of the decision circuit 78 changes from "0" to "1", the switch 79 is turned on and the selector 80
Changes the output step size from μ ₁ to μ ₂ .
In the "second state", the effective tap position is updated every Q times (Q is a positive constant) of coefficient update. The tap position is updated according to the following procedure.

The minimum tap search circuit 72 receives the effective tap number output from the tap calculation circuit 73 and the tap coefficient output from each coefficient updating circuit, and switches the effective tap number corresponding to the coefficient having the smallest absolute value. It is supplied to the memory circuit 70 and the coefficient clear circuit 74 via 79. The coefficient clearing circuit 74 outputs a coefficient clearing signal to the coefficient updating circuit corresponding to the input tap number, thereby zeroing the corresponding tap coefficient value having the smallest absolute value. The memory circuit 70 stores the tap number input through the switch 79 at the end of the queue and outputs the tap number S at the head of the queue to the determination circuit 71. On the other hand, the tap number I _max corresponding to the coefficient having the maximum coefficient absolute value output from the maximum tap search circuit 75 is input to the control tap output circuit 76. The control tap output circuit 76 receives the tap number I _max supplied from the maximum tap search circuit 75.
Then, (I _max -L) and (I _max + L) are calculated,
It outputs to the determination circuit 71 (however, L is the number of effective taps). The determination circuit 71 indicates that the input tap number S is
It is determined whether or not the condition of (I _max −L) ≦ S ≦ (I _max + L) is satisfied, and if not satisfied, the tap number S is returned to the end of the queue, and a new tap at the head of the queue is again displayed. The number is taken out and input to the judgment circuit 71. This repetitive operation is performed until the above determination condition is satisfied. When the above determination condition is satisfied, the invalid tap number held in the memory circuit 70 is determined, and as a result, a new valid tap is determined.

In the above-described method of updating the effective tap position, the effective tap having the smallest absolute value is invalidated, and the newly validated taps are limited to the periphery of the tap having the largest coefficient absolute value. Coefficients are concentrated in the response waveform portion, and the convergence speed can be improved.

[0013]

The method proposed in the above-mentioned "Document 3" has the following problems. In the impulse response to be approximated by the adaptive filter, when there are a plurality of substantial response waveform parts excluding the fixed delay part, for example, in the case of an echo canceller for canceling multi-echo, In the conventional method shown in “3”, since the newly effective tap position is fixed around the tap having the maximum absolute value of the coefficient,
No tap coefficient is placed in the response waveform portion having a small amplitude outside the limited range. Therefore, there arises a problem that the residual error is not reduced. Also, if you expand the limited range, instead of expanding the range where taps are newly placed,
The taps cannot be intensively arranged due to the limitation of the tap control range, and the convergence time increases.

An object of the present invention is to propose an adaptive filter adaptation method and apparatus which solve the above problems.

[0015]

According to the present invention, among all the taps of an adaptive filter, some tap coefficient numbers used for product-sum calculation are stored as effective coefficient numbers and are not used for the product-sum calculation. The tap coefficient number is stored in the queue as an invalid coefficient number, and each time the coefficient corresponding to the valid coefficient number is updated, the number in which the absolute value of the corresponding coefficient is the smallest among the valid coefficient numbers is invalidated and the wait coefficient is stored. When the invalid coefficient number at the head of the queue is taken out at the end of the queue and the invalid coefficient number is within the tap control range centered on the effective coefficient number having the largest absolute value of the coefficient, A new valid coefficient number is set, and if it is not within the tap control range, it is not validated and returned to the end of the queue, and is repeated until the invalid coefficient number extracted from the head of the queue becomes newly valid. In the adaptive filter that operates so as to adaptively control the tap position, all the taps of the adaptive filter are divided into a plurality of tap control groups each having an equal number of consecutive taps, and the tap control range is the tap control. The tap control group is limited to taps belonging to the selected tap control group, and the selection of the tap control group is changed for each predetermined coefficient update, and the selection order is the effective tap coefficient of each tap control group. This is an adaptive filter adaptation method characterized in that the tap position is adaptively controlled by performing it in order of the group having the largest absolute value.

Further, according to the present invention, in the adaptive filter for identifying the unknown system, the coefficient is updated using an error signal obtained by subtracting the identification signal output by the adaptive filter from the output of the unknown system. , A plurality of delay circuits connected in series that give a delay to an input signal, a tap switching circuit that selects and outputs a part of the delay signals of the delay circuit, and a delay signal that the tap switching circuit outputs And a plurality of coefficient updating circuits that output the tap coefficient values in response to the error signal and the coefficient clear signal, and a plurality of multipliers that multiply each tap coefficient value of the coefficient updating circuit by each delay signal output by the tap switching circuit. Of the multiplication circuit, an addition circuit that adds the outputs of the multiplication circuit and outputs the identification signal, and an identification that the output of the unknown system outputs from the addition circuit. At least a tap control circuit for receiving a tap coefficient value output from the coefficient updating circuit and generating a switching signal of the tap switching circuit and the coefficient clear signal. Then, the coefficient updating circuit multiplies a first multiplying circuit that multiplies the delay signal and the error signal, and a second multiplying circuit that multiplies an output of the first multiplying circuit and a step size that determines a coefficient updating amount.
Of the second multiplying circuit, an adding circuit for adding the output of the second multiplying circuit and a feedback signal, an output of the adding circuit is held as the tap coefficient value, and is supplied to the adding circuit as the feedback signal, A delay circuit reset to zero by a coefficient clear signal, wherein the tap control circuit comprises a first memory circuit for holding the supplied tap numbers in the order in which they are supplied, and all tap numbers of the adaptive filter. A tap calculation circuit that calculates the remaining tap numbers excluding the tap numbers held by the first storage circuit and outputs the tap numbers to the tap switching circuit, the tap number output by the tap calculation circuit, and the output of the coefficient update circuit. A tap number corresponding to the tap coefficient value having the smallest absolute value and writing the tap number corresponding to the tap coefficient value to the tail end of the first memory circuit; And coefficient clear circuit which outputs the coefficient clear signal to the coefficient updating circuit corresponding to the tap number of the output of the flop retrieval circuit, a group number representing the tap control group composed of a plurality of consecutive tap number,
A second memory circuit that stores in accordance with the order of the group to be controlled, and a control tap that receives the tap control group number output from the second memory circuit and outputs the upper limit value and the lower limit value of the tap number belonging to the group number The output circuit and the tap number stored at the head of the first storage circuit are taken out, and it is determined whether the tap number is within the range between the upper limit value and the lower limit value of the tap number output by the control tap output circuit. However, when the tap number is not within the range, the determination circuit for returning the tap number to the end of the first storage circuit, the tap number output by the tap calculation circuit, and the tap coefficient value output by the coefficient update circuit are set. Then, the tap coefficient value with the maximum absolute value is searched for each control group, and the tap control group number is output in the order of the tap control group with the largest absolute value maximum coefficient value. Up search circuit, a first coefficient circuit for instructing the second memory circuit to change the tap control group number each time the number of tap coefficient updates reaches a predetermined number, and the first coefficient circuit. A second counting circuit that outputs a tap control group order change signal every time the counting circuit instruction signal is output a predetermined number of times, and an output of the maximum tap search circuit according to the second output change signal. The second tap control group number is input in the order of input.
And a control group update circuit for writing in the storage circuit of the adaptive filter adaptation device.

[0017]

According to the tap position control of the present invention, all taps are divided into a plurality of tap control groups having the same number of taps, and the range of newly validated taps is selected from all tap control groups. Limit to taps that belong to the tap control group. Further, the tap control group to be selected is changed for each predetermined number of coefficient updates, and the selection order is set in the order of the largest maximum absolute value of the tap coefficients in each tap control group. The selection order is updated every time the tap control group is selected.

The tap position control limited to the selected tap control group places the taps centrally, and promotes coefficient growth while the group located in the waveform response section is selected. On the other hand, the selection control of the limited range is performed in the case where there are a plurality of waveform response parts having different amplitudes such as multi-echo, by preferentially growing the coefficient of the response part having a large amplitude, the amplitude that is easily affected by noise is changed. It can help the coefficient growth of the small response part. Also, the limited range is not one place as in “Reference 3”,
Since the entire tap range is moved by changing the selected tap control group, multi-echo can be supported.

[0019]

The present invention will be described in detail with reference to the drawings. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a coefficient updating circuit 30 _x (X
Is a block diagram showing details of (= 1, 2, ... L). The coefficient update circuit 30 _X (x = 1, 1) according to the present invention shown in FIG.
2, ... L) is composed of a multiplication circuit 51, a multiplication circuit 52, an addition circuit 53, and a delay circuit 54, and does not control the step size, so that the step size input terminal M is not provided. Different from the update circuit 50 _x . 1 showing the configuration of the present invention and FIG. 3 showing a conventional example are exactly the same except for the coefficient updating circuit and the tap control circuit 61, and only the operation of the tap control circuit 61 will be described in detail below.

The memory circuit 83 is a memory circuit for storing a group number representing a tap control group composed of a plurality of consecutive tap numbers in the order of the groups to be controlled, and the number of taps belonging to each tap control group. Are set equal. For example, the total number of taps N is 2
When the number of tap control groups is 0 and the number of tap control groups is 5, the number of taps belonging to each tap control group is 4. In addition, the tap control group is GRP (1) (1 = 1, 2, ..., 5),
When the tap number following GRP (1) is represented by {}, GRP (1) = {1,2,3,4} GRP (2) = {5,6,7,8} GRP (3) = { 9, 10, 11, 12} GRP (4) = {13, 14, 15, 16} GRP (5) = {17, 18, 19, 20}.

The memory circuit 83 is set as an initial value of the tap control group number in ascending order of the tap control group number. That is, when the tap control group order stored in the memory circuit 83 is represented by Z (n) (n = 1, 2, ... 5), Z (1) = 1 Z (2) = 2 Z (3) = 3 Z (4) = 4 Z (5) = 5 is initialized. Further, the address pointer of the memory circuit 83 is set to the head and outputs the tap control group number at the head, in the above example, Z (1) = 1.

The memory circuit 70 has an FIF as in the conventional example.
A memory circuit configured by O (First-In-First-Out) stores (N-L) invalid tap numbers. However, N is the total number of taps, and L is the number of effective taps. Further, the tap calculation circuit 73 is also the same as the conventional example, and calculates the tap number excluding the invalid tap number held in the storage circuit 70 from all the tap numbers, that is, the valid tap number,
The tap number is supplied to the tap switching circuit 7 as a tap switching control signal. The tap switching circuit 7 operates so as to select the output of the delay circuit corresponding to the L effective tap numbers received from the tap calculation circuit 73 and output it to the coefficient updating circuit. Unlike the conventional example, the invalid tap number in the initial state, that is, the initial setting value of the memory circuit 70 is selected so that the valid tap numbers are continuously arranged from the head of all tap numbers. For example, if the total number of taps N is 20, the number of valid taps L is 3, and the number of invalid taps (NL) is 17, all tap numbers are 1, 2, 3, ... At this time, the valid tap numbers are 1, 2, 3 and 3 taps from the beginning,
The invalid tap numbers held by the memory circuit 70 are 4, 5, and 5.
..., which is initially set to 20.

After the above initial state is set, the coefficient of the tap coefficient of the tap (valid tap) selected by the tap switching circuit 7 is updated. Every time the coefficient is updated Q times (Q is a positive constant), the effective tap position is updated. The tap position is updated according to the following procedure.

The minimum tap search circuit 72 receives the effective tap number output from the tap calculation circuit 73 and the tap coefficient output from each coefficient updating circuit, and stores the effective tap number corresponding to the coefficient having the smallest absolute value. It is supplied to the circuit 70 and the coefficient clear circuit 74. The coefficient clearing circuit 74 outputs a coefficient clearing signal to the coefficient updating circuit corresponding to the input tap number, thereby zeroing the corresponding tap coefficient value having the smallest absolute value. The storage circuit 70 stores the input tap number at the end of the queue and outputs the tap number S at the head of the queue to the determination circuit 71. Unlike the control tap output circuit 76 of the conventional example, the control tap output circuit 82 receives the tap control group number Z (n) output from the memory circuit 83 and receives the tap control group, that is, QRP (Z (n)). Among the tap numbers belonging to, the smallest tap number K _MIN and the largest tap number K _MAX are calculated and output to the determination circuit 71. For example, in the above example, if Z (n) = 1,
GRP (Z (n)) = GRP (1) = {1, 2, 3,
4}, and K _MAX = 4 and K _MIN = 1 are output. The determination circuit 71 determines that the input tap number S is K _MIN ≦ S ≦ K
_{It is} judged whether or not the condition of _MAX is satisfied, and if not satisfied, the tap number S is returned to the end of the queue, and a new tap number at the head of the queue is taken out again and the judgment circuit 7
Input to 1. This repetitive operation is performed until the above determination condition is satisfied. When the above determination condition is satisfied, the invalid tap number held in the memory circuit 70 is fixed, and as a result, a new valid tap is determined. As described above, by the tap position control limited to the tap control group described above,
Allows for intensive placement of taps.

On the other hand, the tap control group is changed by the following procedure.

The counting circuit 84 is a counter which counts the number of times the coefficient of tap coefficient is updated, and the control circuit change signal is stored in the storage circuit 83 every time the number of times of coefficient update is predetermined T.
And to the counting circuit 85. Upon receiving the control group change signal from the counting circuit 84, the memory circuit 83 increments the address pointer and outputs the tap control group number stored at the next address.

The counting circuit 85 counts the control group change signals output by the counting circuit 84, and outputs an update signal in the control group order each time the input change signal reaches the number of tap control groups. The maximum tap search circuit 81 includes a tap coefficient value output from each coefficient update circuit and a tap calculation circuit 73.
In response to the effective tap number output by, the tap coefficient value having the maximum absolute value is calculated for each tap control group, and the tap control group numbers are output in the descending order of the coefficient absolute value. When the control group update circuit 86 receives the update signal in the control group order from the counting circuit 85, by writing the tap control group numbers output from the maximum tap search circuit 81 from the leading address of the storage circuit 83 in the supplied order, The tap control group order held by the memory circuit 83 is changed.

By changing the tap control group described above, the tap control range moves over all the taps, so that the residual error can be reduced even when there are a plurality of substantial response waveform parts such as a multi-echo. You can Furthermore, by prioritizing the tap control group selection order from the group with the largest tap coefficient value, the tap coefficient of the response section with large amplitude grows quickly, and the coefficient of the response section with small amplitude susceptible to noise grows. I can help. In the embodiment, the number of taps changed by one tap control is assumed to be 1 tap, but it is also possible to set it to 2 taps or more.

Although the embodiment of the present invention has been described in detail above by taking the echo canceller as an example, the present invention is based on the same principle as the noise canceller, howling canceller,
It can also be applied to an adaptive equalizer or the like. Further, various algorithms can be applied to the algorithm for updating the tap coefficient.

[0030]

As described above, according to the present invention, by controlling the tap position limited to the tap control group and the selection control of the tap control group, the coefficient growth of the response waveform portion is promoted, and the multi-echo type is realized. It is possible to realize an adaptive filter capable of reducing the residual error even when there are a plurality of substantial response waveform parts.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a coefficient updating circuit included in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a block diagram showing a configuration of a coefficient updating circuit included in FIG.

[Explanation of symbols]

1 transmission signal input terminal 2 transmits the signal output terminal 3 receives the signal input terminal 4 receives the signal output terminal 5,33,53 adder circuit 6 addition circuit 7 tap switching circuit 8 2-wire / 4-wire conversion circuit 34,54,20 20 ₁ to 20 _N-1 delay circuit 30 ₁ to 30 _L , 50 ₁ to 50 _L coefficient updating circuit 31, 32, 51, 52, 40 ₁ to 40 _L multiplication circuit 60, 61 tap control circuit 70, 77, 83 storage circuit 73 tap calculation Circuit 71, 79 Judgment circuit 72 Minimum tap search circuit 75, 81 Maximum tap search circuit 74 Coefficient clear circuit 76, 82 Control tap output circuit 79 Switch 80 Selector

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H03H 21/00 7037-5J

Claims (2)

[Claims] 1. A number of some tap coefficients used for product-sum calculation among all taps of the adaptive filter are stored as effective coefficient numbers, and tap coefficient numbers not used for the product-sum calculation are used as invalid coefficient numbers. Each time a coefficient stored in the queue is updated, and the coefficient corresponding to the effective coefficient number is updated, the number having the smallest absolute value of the corresponding coefficient among the effective coefficient numbers is invalidated and placed at the end of the queue. The invalid coefficient number at the head of the queue is extracted, and if the invalid coefficient number is within the tap control range centered on the effective coefficient number with the largest absolute value of the coefficient, it is set as a new effective coefficient number and tapped. If it is not within the control range, it is not validated and it is returned to the end of the queue, and the tap position is operated by repeating until the invalid coefficient number extracted from the head of the queue becomes valid again. In an adaptively controlling adaptive filter, all taps of the adaptive filter are divided into a plurality of tap control groups consisting of an equal number of consecutive taps, and the tap control range is selected in the tap control group. Existing tap control groups, the selection of the tap control group is changed for each predetermined coefficient change, and the selection order is the largest maximum absolute value of the effective tap coefficients in each tap control group. An adaptive filter adaptation method characterized in that tap positions are adaptively controlled by performing them in the order of groups. 2. Adaptive output from unknown system output
In the adaptive filter that updates the coefficient by using the error signal obtained by subtracting the identification signal output from the filter and identifies the unknown system, a plurality of serially connected delay circuits are provided for the input signal. A delay circuit, a tap switching circuit that selects and outputs a part of the delay signal of the delay circuit, a delay signal output by the tap switching circuit, the error signal, and a coefficient clear signal, and outputs a tap coefficient value. A plurality of coefficient updating circuits for outputting, a plurality of multiplying circuits for multiplying each tap coefficient value of the coefficient updating circuit and each delay signal output by the tap switching circuit, and each output by the multiplying circuit are added to identify An adder circuit for outputting a signal; a subtractor circuit for subtracting the identification signal output by the adder circuit from the output of the unknown system to output the error signal; A tap control circuit for receiving a tap coefficient value to be applied and generating a switching signal of the tap switching circuit and the coefficient clear signal, wherein the coefficient updating circuit multiplies the delay signal by the error signal; , A second multiplication circuit that multiplies the output of the first multiplication circuit and a step size that determines the coefficient update amount, and an addition circuit that adds the output of the second multiplication circuit and the feedback signal. A delay circuit for holding the output of the adder circuit as the tap coefficient value and supplying it to the adder circuit as the feedback signal, and resetting it to zero by the coefficient clear signal. A first storage circuit that holds the tap numbers that have been supplied in the order in which they are supplied, and the tap numbers that the first storage circuit holds from all tap numbers of the adaptive filter. The tap having the smallest absolute value is received by receiving the tap calculation circuit for calculating the remaining tap number and outputting the tap number to the tap switching circuit, the tap number output by the tap calculation circuit and the tap coefficient value output by the coefficient updating circuit. A coefficient for outputting the coefficient clear signal to a minimum tap search circuit that writes a tap number corresponding to a coefficient value at the end of the first storage circuit and a coefficient update circuit that corresponds to the tap number output from the minimum tap search circuit. A clear circuit, a second memory circuit that stores a group number representing a tap control group composed of a plurality of consecutive tap numbers according to the order of the group to be controlled, and tap control output from the second memory circuit. A control tap output circuit for receiving a group number and outputting an upper limit value and a lower limit value of a tap number belonging to the group number; and the first storage. The tap number stored at the beginning of the path is taken out, it is determined whether the tap number is within the range of the upper limit value and the lower limit value of the tap number output by the control tap output circuit, and if it is not within the range. , The tap number output to the tail of the first memory circuit, the tap number output from the tap calculation circuit, and the tap coefficient value output from the coefficient update circuit The maximum tap search circuit that searches for the maximum tap coefficient value and outputs the tap control group number in the order of the tap control group with the largest absolute maximum coefficient value, and every time the number of tap coefficient updates reaches a predetermined number. A first coefficient circuit for instructing the second memory circuit to change the tap control group number, and the first coefficient circuit.
A second coefficient circuit that outputs a tap control group order change signal each time the instruction signal of the coefficient circuit is output a predetermined number of times, and the maximum tap search circuit based on the second output change signal. And a control group update circuit for writing the tap control group numbers output by the above into the second memory circuit in the order in which they are input.