JPH04230112A - Method and device for approximating unknown system by adaptive filter - Google Patents

Abstract

PURPOSE:To shorten the convergence time by switching sequentially tap coefficients of a limited number, allocating the coefficient to a different tap so as to reduce the hardware and replacing a tap position limited in the vicinity of an estimated waveform responsing part. CONSTITUTION:An input signal fed to a delay element 101 is transmitted sequentially to delay elements 102-10N at every clock. A matrix switch 14 connects N delay elements 101 and M coefficient circuits 11i selected by the output of a control circuit 13 adaptively. In the case of approximating an unknown system, the flat delay of the unknown system is estimated in an initial condition. Then plural input signal samples receiving a delay equivalent to the estimated flat delay and plural multiplicands changed adaptively are combined for multiplication and while the combination is changed in a prescribed limit, the multiplicand is updated.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive filter used in identifying an unknown system. These adaptive filters include an echo canceller to remove echoes generated in the 2-wire/4-wire converter, an equalizer to remove intersymbol interference received on the transmission path, and a microphone for audio input. It is applied to noise cancellers to remove noise that enters the room, and howling cancellers to remove howling caused by acoustic coupling from speakers to microphones. [0002] Normally, an unknown system is identified using an adaptive filter by inputting the same signal to the adaptive filter as the unknown system to be identified, and subtracting the adaptive filter output from the unknown system output. Identification error (
(Hereafter, this is called an error signal)
This is done by updating the coefficients of the filter. Applications of unknown system identification using such adaptive filters include echo cancellers, equalizers, noise filters, etc.
Cancellers, howling cancellers, etc. are known (adaptive signal processing,
tive Signal Processing)
, Prentice-Hal
1), 1985; hereinafter referred to as "Reference 1"). Since the basic operations of adaptive filters in these applications are almost the same, the conventional technology will be explained here using an echo canceller as an example. [0003] An echo canceller is an adaptive canceller with a transfer function that approximates the echo impulse response.
By using a filter to generate an approximate echo (echo replica) that corresponds to the echo leaking from the transmitting circuit to the receiving circuit on the 4-wire side of the 2-wire/4-wire conversion circuit, it is possible to prevent echoes from entering the receiving circuit and receiving the test. It works by suppressing echoes that interfere with the signal. In other words, 4 of the 2-wire/4-wire conversion circuit
On the line side, the path from the transmitting circuit to the receiving circuit is
This corresponds to an unknown system that is attempted to be identified using an adaptive filter in a canceller. At this time, the adaptive
Each tap coefficient of the filter is successively corrected by correlating the transmitted signal with a difference signal obtained by subtracting the echo replica from a mixed signal in which echoes and consultation signals are mixed. The LMS algorithm (LMS ALGORITH) is a typical convergence algorithm for the echo canceller that corrects the coefficients of such an adaptive filter.
M; "Reference 2") and the Learning Identification Method (LEARNING IDENTI)
FICATION METHOD; LIM) (IEEE TRANSACTI
ONS ON AUTOMATIC CONTRO
L) Vol. 12, No. 3, 1967, pages 282-287; hereinafter referred to as "Reference 3") is known. FIG. 7 is a block diagram showing an example of the configuration of a conventional echo canceller. The echo ek generated when the transmission signal supplied to the input terminal 1 leaks to the receiving side in the 2-wire/4-wire conversion circuit 2 is supplied to the output terminal 4 after an echo replica ek is subtracted in the subtracter 3. Ru. On the other hand, the transmission signal supplied to the input terminal 1 is also supplied to the first tap circuit 701 of the adaptive filter. The first output of the first tap circuit 701 is connected to the adjacent second tap circuit 701.
The signal is transmitted to the tap circuit 702. First tap circuit 70
The second output of 1 is provided to adder 12. The second tap circuit 702 transmits the first output generated from the signal received from the first tap circuit 701 to the third tap circuit 703 and the second output to the adder 12. Similarly, the i-th tap circuit 70i is the (i-1)th tap circuit 70i-1.
The first output generated from the signal received from
) to the tap circuit 70i+1, the second output is sent to the adder 12
Communicate to. However, i is an integer satisfying 2≦i≦N−1, and N represents the number of taps of the adaptive filter. 1st
The tap circuit 701 transmits the first output generated from the signal received from the input terminal 1 to the second tap circuit 702 and the second output to the adder 12. Nth tap circuit 70N
transmits the second output generated from the signal received from the (N-1)th tap circuit 70N-1 to the adder 12. The adder 12 adds all the second outputs supplied from the i-th tap circuit 70i (1≦i≦N), and creates an echo replica e.
k to the subtracter 3. The i-th tap circuit 70i is supplied with the difference signal that is the output of the subtracter 3 and a constant μ1. Here, μ1 is called a step size and is deeply involved in coefficient updating. FIG. 8 shows a block diagram of the i-th tap circuit 70i (1≦i≦N). However, when i=1, the delay element 81 is not included. Furthermore, when i=N, the output 804 is not used. Input signal 800 is a signal transmitted from input terminal 1 or (i-1)th tap circuit 70i-1, output signal 804 is a signal transmitted to (i+1)th tap circuit, input signal 8
01 is the difference signal that is the output of the subtracter 3, the output signal 803 is the signal supplied to the adder 12, and the input signal 802 is the step size μ1. Input signal 800 is input to delay element 8
1 and delayed by one sample period, it becomes an output signal 804 and is supplied to the (i+1)th tap circuit and simultaneously transmitted to the coefficient generation circuit 82 and the multiplier 83. The coefficient generation circuit 82 is also supplied with an input signal 801 which is a difference signal and an input signal 802 which is a step size μ1. Coefficient generation circuit 82 supplies coefficient values generated using these input signals to multiplier 83. Multiplier 83
multiplies the signal from the coefficient generation circuit 82 and the signal from the delay element 81, and outputs the result as an output signal 803. FIG. 9 shows a block diagram of the coefficient generation circuit 82 assuming the LMS algorithm. The input signal 95 is the output signal of the delay element 81 in FIG. 8, the input signal 801 is the difference signal, the input signal 802 is the step size μ1, and the output signal 96 is the coefficient value. The input signal 95 and the input signal 801 are multiplied by a multiplier 91, and the correlation between the transmitted signal of the echo canceller and the difference signal is determined. The output of multiplier 91 is multiplied by step size μ1 in multiplier 92 and supplied to adder 93. The adder 93 adds the output of the multiplier 92 and the fed-back output of the delay element 94 and supplies the result to the delay element 94 . The output of the delay element 94, which is a coefficient value, is outputted as an output signal 96 every clock. [0007] Now, assume that the transmitted signal is xk (where k is an index indicating time), the echo is ek, and the additional noise received by ek is δk. Considering that the echo canceller generally performs adaptive operation only during single talk when there is no received signal and only the echo ek exists, the subtracter 3
The signal uk supplied to uk consists of echoes and additional noise and is expressed by the following equation. uk = ek + δk ………………
…………………………………………… (1) The purpose of the echo canceller is to generate a replica ek of the echo ek in equation (1) and use this to cancel the echo. . The difference signal dk, which is the output signal of the subtractor 3, is expressed by the following equation, considering that δk is generally sufficiently small compared to ek -ek . dk =ek −ek ………………
...................................................... (2) In equation (2), (ek - ek ) is called a residual echo. LM
In the S algorithm, the m-th coefficient cm,k of the adaptive filter is updated according to the following equation. cm,k =cm,k-1 +μ1
・dk ・xk−m−1 ………………………(3)
Expressing equation (3) regarding all N coefficients in matrix form, we get
ck = ck-1 + μ1 ・dk
・xk-1 …………………………………(4). Here, vector ck and vector xk are respectively given by the following equations. ck = [c0,k c1,k...
…cn-1,k ]T ………………………(5)
xk = [xk xk-1 ...... xk
−N+1]T …………………………………(6) On the other hand,
In LIM, coefficients are updated according to equation (7) instead of equation (4). ck = ck-1 + (α/Nσx2
)・dk・xk−1 ………………………(7) α is
The step size for LIM, σx2, is the average power input to the adaptive filter. σx2
is used to make the value of step size α inversely proportional to the average power and to achieve stable convergence. σx2
There are several ways to calculate, for example, the formula (
8). ##EQU1## The step size in equations (4) and (7) defines the speed of convergence of the adaptive filter and the residual echo level after convergence. In the case of LMS, μ
The larger 1, the faster the convergence, but the higher the residual echo level. On the other hand, in order to achieve a sufficiently small residual echo level, it is necessary to adopt a commensurately small μ1, which results in a decrease in the convergence speed. The same applies to the step size α of LIM. In identifying an unknown system, cases in which a long flat delay is included at the beginning of the impulse response of the unknown system to be identified are frequently observed, especially in echo cancellers intended for satellite lines. Even for an impulse response including such a long flat delay, it is necessary for the conventional echo canceller to have a number of taps corresponding to the impulse response length in order to sufficiently suppress the echo. In reality, the tap coefficients of the flat delay section are zero, so it is wasteful to use these coefficients in calculating the filter output. There is a method to solve this problem and perform system identification efficiently even for impulse responses that include long flat delays.
“Proceedings of the 1981 National Conference of the Telecommunications Society of the Institute of Electronics and Communication Engineers, N.
o. 595" (hereinafter referred to as "Reference 4"). In this method, for an impulse response consisting of a flat delay and a substantial waveform response, only coefficients at positions corresponding to a substantial waveform response are used for filter output calculation, thereby reducing the amount of calculation. The method described in Document 4 will be briefly explained below. FIG. 10 is a block diagram showing the echo canceller described in Document 4. The difference from the echo canceller shown in FIG. 7 is that each tap circuit 10 in FIG.
01 , 1002 , ......, 100N After passing through the control circuit 101 , each tap circuit 1001 , 100
2,......,100N and each tap circuit 701,702,......,70N and each tap circuit 1001,1002,......,100
This is a configuration of N. The control circuit 101 includes each tap circuit 1
Using the coefficient values obtained from 001, 1002, ......, 100N, it is determined for which coefficient the calculation should be stopped, and the information is used as a control signal to each tap circuit 1001.
, 1002 , ......, 100N. Each tap circuit 10 is controlled by a signal supplied from the control circuit 101.
01, 1002, ......, 100N stop calculations for unnecessary coefficients. FIG. 11 shows a block diagram of the tap circuit 100i. The difference from the tap circuit 70i shown in FIG. 83. The selector 111 selects the output of the coefficient generation circuit 82 or zero and supplies it to the multiplier 83 . Selector 110 selects input signal 801 or zero and supplies it to coefficient generation circuit 82 . Both selectors 110 and 111 select zero in response to a control signal 115 supplied from the control circuit 101 to each tap coefficient. Therefore, selector 11
When the selector 111 selects zero, the signal supplied to the coefficient generation circuit 82 becomes zero, and when the selector 111 selects zero, the multiplicand in the multiplier 83 becomes zero, and the coefficient update amount and the corresponding tap circuit output become zero. Selectors 110, 11
1 selects and outputs zero when the control signal 115 is 0. Next, the control circuit 101 will be explained. FIG. 12 is a block diagram of the control circuit 101. The control circuit 101 is supplied with tap coefficient values and tap numbers from N taps of the adaptive filter. The control circuit 101 detects a minimum value among tap coefficient values whose corresponding tap number matches a tap number stored in the control circuit, and stores the tap coefficient value in the control circuit in place of the tap number corresponding to the minimum value. A new set of tap numbers is constructed by replacing the value at the head of the current queue as a new tap number, and is supplied to the N taps of the adaptive filter. The input signal 125 to the control circuit 101 is input to each tap circuit 1001, 1002,...
, 100N and supplied to the control circuit 101, the output signal 126 is output from the control circuit 101 to each tap circuit 1.
This is a control signal supplied to 001, 1002, ......, 100N. Therefore, although shown as a single line in the figure, the input signal 125 and output signal 126 are N multiplexed signals. The input signal 125 is first input to the absolute value circuit 121.
The absolute value is converted into an absolute value and transmitted to the minimum value detection circuit 122. A minimum value detection circuit 122 detects the minimum of these absolute value signal components and stores the corresponding tap number in a first-in first-out circuit (FIFO) 123 and a storage device 124.
Communicate to. The FIFO 123 is the minimum value detection circuit 122
When a signal is supplied from the storage device 124, one sample inputted fastest among the sample values stored at that time is transmitted to the storage device 124. The storage device 124 stores 0 or 1 corresponding to each of the N tap numbers to be subjected to the filtering operation, and when a signal is transmitted from the FIFO 123, the value corresponding to the tap number is changed from 0 to 1. change. On the other hand, the value corresponding to the tap number supplied from the minimum value detection circuit 122 to the storage device 124 is changed from 1 to 0. Therefore, the total number of 0's and 1's in the storage device 124 is constant, the total number M of 1's is the effective number of taps to which coefficients are assigned, and the number of 0's NM is the number of taps to which no coefficients are assigned. A signal composed of a sequence of 0's and 1's obtained through the above operations is outputted from the storage device 124 as an output signal 126, and then sent to each tap circuit 1001, 1002,
......, 100N is supplied. i of output signal 126
The second numerical value (0 or 1) becomes a control signal for the tap circuit 100i. The tap circuit 100i outputs the output signal 126
The selectors 110 and 111 are controlled using the i-th value as the control signal 115 in FIG. [0014] As explained using FIG. 11, in the method described in Document 4, the control signal 11
When 0 is supplied as 5, zero is output as the output of the selector 111. Therefore, the coefficient generation circuit 82 is not substantially used and is wasted. Furthermore, as the initial value of the storage device 124 in FIG. 12, a number of 1s equal to the number of effective taps are arranged at equal intervals, and as the initial value of the FIFO 123, that is, the queue, the tap numbers to which 0 is assigned in the storage device 124 are assigned from the smallest to the lowest. Place them in order. When such an initial value is used and an impulse response with a long flat delay is approximated, the tap number corresponding to the waveform response section moves to a position closer to the output in the FIFO 123, is supplied to the storage device 124, and is assigned taps. It takes a long time until it is done. Therefore, there is a problem that the convergence time becomes long. An object of the present invention is to provide an adaptive filter with small hardware scale and short convergence time. [0016] The present invention performs multiplication by adaptively combining a plurality of input signal samples delayed by one sample period with a plurality of multiplicands that adaptively change. When approximating an unknown system with an adaptive filter that stores addresses of multiplicands that are not used in a queue and outputs the sum of the multiplication results, the combination of the input sample and the multiplicand is fixed. updating a multiplicand, monitoring the maximum absolute value of the plurality of multiplicands, and updating the multiplicand when a particular multiplicand is detected as the maximum value at a predetermined frequency; If the first value in the queue is not within a predetermined value range from the position of the maximum value, the first value is stored at the end of the queue and the new value at the beginning of the queue is set. Evaluate the position, repeat this operation until a new queue head value within the predetermined value range is obtained, and use the multiplicand corresponding to the address that is the head value for multiplication. Set,
Detecting the minimum value of the absolute value of the multiplicand, storing the address of the multiplicand corresponding to the minimum value at the end of the queue and removing it from the multiplication target, setting the new multiplicand, and storing the minimum value address in the queue. is repeated until a predetermined number of times is reached, and while the multiplicand is updated a predetermined number of times with the combination of input sample multiplicands fixed, a certain multiplicand is set as the maximum value at a predetermined frequency. If not detected, the combination of the input sample and the multiplicand is changed, and the multiplicand is updated a predetermined number of times until a certain multiplicand is detected as the maximum value at a predetermined frequency; The method is characterized in that the combination of the input sample and the multiplicand is changed. Further, according to the present invention, a predetermined first constant is used for updating the multiplicand when the combination of the input sample and the multiplicand is fixed, and the update is performed while the combination is adaptively changed. A feature is that a predetermined second constant is used to update the multiplicand. Furthermore, in the present invention, when a certain multiplicand is detected as the maximum value at a predetermined frequency, when the maximum value is detected to be sufficiently large compared to other multiplicands, the multiplicand is It is characterized in that the multiplicand is updated and the multiplicand corresponding to the value in the queue is replaced, and when it is determined that the multiplicand is not sufficiently large, the combination of the input sample and the multiplicand is changed. [0019] In the adaptive filter of the present invention, the hardware scale can be reduced by sequentially switching a limited number of tap coefficients and assigning them to different taps. In addition, in the adaptive filter of the present invention, when allocating a limited number of taps to the substantial waveform response part of the impulse response, the rough position of the waveform response part is first estimated, and then the approximate position of the waveform response part is After concentrating the taps, the convergence time can be shortened by replacing the tap positions only in the vicinity of the estimated waveform response section. In particular, when the position of the waveform response section cannot be estimated within a predetermined time, the initial value of the tap assignment is changed and re-estimation is performed. Even when the position of the waveform response unit is estimated, if the estimated position is not determined to be valid, the initial value of the tap assignment is updated and re-estimation is performed. Furthermore, the adaptive filter of the present invention performs stable position estimation using a small step size when estimating the position of the waveform response part, and uses a large step size when replacing the tap position limited to the vicinity of the estimated waveform response part. can be used to perform high-speed convergence and shorten the convergence time. DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, functional blocks given the same reference numbers as in FIG. 10 have the same functions as in FIG. 10. The difference between FIG. 1 and FIG. 10 is that each tap circuit 1001
, 1002 , ......, 100N is the delay element array 10
1, 102, ......, 10N, matrix switch 14, and coefficient circuit 111, 112, ......, 1
The point is that it has been replaced by 1M. Along with this,
The control circuit 13 controls the matrix switch 14 with its output. In FIG. 1, the input signal supplied to the delay element 101 is transmitted to the delay elements 102, . . . every clock.
..., 10N sequentially. Delay element array 101
,102 ,......,10N is matrix switch 1
4 through M coefficient circuits 111, 112,......,
Connected to 11M. However, N>M. The matrix switch 14 includes M delay element arrays 10i selected by the output of the control circuit 13 and M coefficient circuits 11.
i sequentially and adaptively. FIG. 2 shows the configuration of the i-th coefficient circuit 11i.
Shown below. 2 is essentially equivalent to the tap circuit of FIG. 8, the only difference being that it does not include the delay element 81. The input signal 20 of FIG. 2 corresponds to the output signal of the delay element 10i of FIG. Other signals 21, 25, 23 are 801 in FIG.
, 803 and 802, respectively, the difference signal which is the output of the subtracter 3, the signal supplied to the adder 12, and the step signal.
It's the size. Coefficient generation circuit 22 and multiplier 24 operate exactly the same as coefficient generation circuit 82 and multiplier 83 in FIG. FIG. 3 shows a specific example of the control circuit 13. The input signal 300 in FIG. 3 has M coefficient circuits 111 and 112.
, ......, coefficient value supplied from 11M, output signal 3
01 is a control signal for the matrix switch 14. A coefficient value supplied as an input signal 300 is converted into an absolute value by an absolute value circuit 31 and transmitted to a maximum value detection circuit 32 and a minimum value detection circuit 33. The maximum value detection circuit 32 detects the maximum one of the input signals and supplies the corresponding tap number to the delay element 34 , the coincidence detection circuit 36 , the determination circuit 37 and the storage device 39 . Delay element 34 delays the input signal by one sample period and then transmits it to coincidence detection circuit 36 . The coincidence detection circuit 36 checks whether the signal supplied directly from the maximum value detection circuit 32 and the signal supplied via the delay element 34 match. This is equivalent to checking whether the tap number corresponding to the current maximum coefficient matches the tap number corresponding to the maximum coefficient one sample period ago. The coincidence detection circuit 36 is
When the two inputs match, 1 is output, and when they do not match, 0 is output. The counter 38 receives this 1 or 0 from the coincidence detection circuit 36 and counts 1. When 1s continue, the counter 38 continues to count up, and when the 1s reach a predetermined value, its output is changed from 0 to 1. Further, when 0 is detected, the counter is reset. The output signal of the counter 38 is transmitted to a delay element 51,
It is supplied to the coincidence detection circuit 52 and the selector 53,
The selector 53 selects the delay element 54 when this output signal is 0.
When the output is 1, the output of the storage device 39 is selected and outputted as the output signal 301. The output signal 301 is delayed by one sample period via the delay element 54 and then sent to the selector 5.
3 will be returned. Therefore, when the output of the counter 38 is 0, the control signal 301 indicating which tap to allocate a coefficient to is the value of one sample period before, and the coefficient allocation tap does not change, and when the output is 1, the control signal 301 is newly output from the storage device 39. The coefficient assignment tap will change depending on the supplied value. The coincidence detection circuit 52 checks whether the output of the counter 38 matches the signal obtained by delaying the output of the counter 38 by one sample period by the delay element 51 and the output of the counter 38, and transmits 1 if they match, and transmits 0 if not to the storage device 39. The minimum value detection circuit 33 detects the minimum value among the input signals, and stores the corresponding tap number in the FIFO 35.
and is supplied to the storage device 39. When the FIFO 35 is supplied with a signal from the minimum value detection circuit 33, it transmits the earliest input sample among the sample values stored at that time to the determination circuit 37. In the judgment circuit 37, F
The difference between the signal supplied from the IFO 35 and the signal supplied from the maximum value detection circuit 32 is determined, and its absolute value is compared with a predetermined threshold. When the absolute value is larger than the threshold value, the signal supplied from the FIFO 35 is fed back to the FIFO 35 as is. When it is smaller than the threshold value, it is transmitted to the storage device 39. The storage device 39 stores 0 or 1 corresponding to each of the N tap numbers to be subjected to the filtering operation, and when a signal is transmitted from the determination circuit 37, the value corresponding to the tap number is set to 0.
Change from 1 to 1. On the other hand, the value corresponding to the tap number supplied from the minimum value detection circuit 33 to the storage device 39 is changed from 1 to 0. Therefore, the total numbers of 0's and 1's in the storage device 39 are each constant. Further, when the signal supplied from the coincidence detection circuit 52 to the storage device 39 is 1, the storage device 39 places M 1's before and after the tap number supplied from the maximum value detection circuit 32. As an example of the arrangement method 1, the tap numbers are equally distributed in the front and rear around the tap number,
And they can be arranged so that 1's are consecutive. By this operation, effective taps are concentrated and arranged near the estimated waveform response section. The signal composed of the sequence of 0's and 1's obtained by the above operation is sent to the selector 53 from the storage device 39.
is transmitted to. As already explained, the selector 53 switches between the signal supplied from the storage device 39 and the signal supplied from the delay element 54 under control of the output of the counter 38. The counter 38 also supplies the number of consecutive 1s itself to the comparator circuit 55. Comparison circuit 55 normally outputs 0, but compares the number of consecutive 1's supplied from counter 38 with a predetermined threshold value Nth, and outputs 1 when the number of consecutive 1's is equal to Nth. do. The output of the comparison circuit 55 is fed back to the counter 38 at the same time as it is supplied to the FIFO 35 and the storage device 39, and the counter 38 is reset when the signal supplied from the comparison circuit 55 is 1. Further, when the output of the comparator circuit 55 is 1, the FIFO 35 and the storage device 39 perform batch rewriting of the held contents using the outputs of the data conversion circuit 60 and the shift circuit 59, respectively. A sequence of 1's and 0's equal to the number of taps N is stored in the storage device 58 as an initial value of the storage device. At this time, the M 1's are arranged at equal intervals with respect to the total number N of 1's and 0's. The shift circuit 59 shifts the data supplied from the storage device 58, supplies it to the storage device 39 and the data conversion circuit 60, and further shifts the data supplied from the storage device 58.
The data shifted to 8 is also returned. The shift amount can be set arbitrarily, but as an example, the initial value can be set to 1/2 of the interval of 1 arranged at equal intervals. The shift amount is halved each time a shift is performed, and changing the shift amount is repeated until the shift amount becomes equal to 1 (1 sample). The shift amount in shift circuit 59 is supplied from storage device 58 . As is clear from the above explanation, when the output of the counter 38 in FIG.
, 112 , . . . , 11M are unchanged and maintain the initial assignment state. By monitoring how the amplitude of the tap coefficient value grows, the substantial waveform response part can be estimated. When the output of the counter 38 becomes 1, it means that a substantial waveform response section has been estimated, so M coefficient circuits 111 , 112 , . . .
..., 11M are concentrated in the vicinity of the estimated waveform response section, and coefficients are more finely assigned. FIG. 4 is a block diagram showing another embodiment of the present invention. FIG. 4 shows coefficient circuits 111, 112,...
, 11M is different from FIG. 1 in that the step size .mu.1 supplied to . Along with this, the control circuit 13 has been replaced with a control circuit 41. In the embodiment shown in FIG. 4, the selector 42 selects the step sizes μ1 and μ2 according to the control signal from the control circuit 41, and the coefficient circuits 111, 112, 11
Supply to M. FIG. 5 is a block diagram of the control circuit 41 shown in FIG. 4. 5 and 3 differ in that the output of the counter 38 is output as a control signal 302. selector 4
2, the control signal 302 supplied from the control circuit 41 is 0.
When it is 1, select μ1, and when it is 1, select μ2. While the control signal 302 is 0, the coefficients are stably grown to estimate the correct waveform response part, and after the control signal 302 is 1, the coefficients are normally set to 1 in order to rapidly converge to the optimal value.
Set to ≦μ2. FIG. 6 shows another specific example of the control circuit 13. The difference between the control circuits of FIG. 6 and FIG. 5 is that even if the maximum coefficient is detected by the counter 38, the tap placement is not concentrated unless the maximum value is sufficiently larger than the absolute value of the other coefficients, and the control circuit continues to This is the point at which the estimation of the waveform response section continues. For this purpose, a comparison circuit 56, an AND circuit 61, and an OR circuit 57 are provided. The comparison circuit 56 receives outputs from the absolute value circuit 31 and the maximum value detection circuit 32, and compares the maximum value with other coefficients. The comparison can be made using various criteria, but for example, if the ratio between the maximum coefficient value cmax and the second largest coefficient cj is greater than a predetermined threshold, cm
It can be assumed that ax is sufficiently large. Comparison circuit 56
outputs 0 when cmax is sufficiently large, and outputs 1 when it is not sufficiently large, and transmits it to the AND circuit 61. On the other hand, the output of the counter 38 is also supplied to the AND circuit 61, and when the outputs of both are 1, that is, when the tap number giving the maximum coefficient continues a predetermined number of times, but the maximum value is not large enough. Outputs 1 in the following cases, and 0 in other cases. The output of the AND circuit 61 is supplied to the OR circuit 57 together with the output of the comparison circuit 55, and when either input is 1, it outputs 1. Therefore, the output of the OR circuit 57 becomes 1 when the waveform response section cannot be estimated by updating the coefficients a predetermined number of times, or when the maximum value of the coefficient is sufficiently large compared to other coefficients even if it is estimated. This is the case where there is no. At this time, the output of the OR circuit 57 causes the FIFO3
5 and the storage device 39 collectively rewrite the contents held therein, and start estimating the waveform response section from new initial values. The operation of the counter 38 in FIGS. 3, 5, and 6 has been explained by taking as an example a case where it is determined whether the signal from the coincidence detection circuit 36 is continuous a predetermined number of times, but instead of being continuous, a predetermined number of times is determined. The case of determining whether the given probability is reached can be explained in exactly the same way. Also,
Up until now, we have assumed the LMS algorithm, but the LMS
The only unique configuration is the coefficient generation circuit shown in FIG. Therefore, the present invention can be applied to other algorithms including LIM. Although the application of the present invention has been explained using an echo canceller as an example, it can be applied to any system having an impulse response that can be expressed by a combination of a flat delay and a waveform response. As described in detail above, according to the present invention, the hardware scale can be reduced by sequentially switching a limited number of tap coefficients and assigning them to different taps. Furthermore, when assigning a limited number of taps to the substantial waveform response part of the impulse response, the adaptive filter of the present invention first estimates the approximate position of the waveform response part, and then assigns the taps in the vicinity of the estimated position. After concentrating the taps, the convergence time can be shortened by replacing the tap positions only in the vicinity of the estimated waveform response section. Furthermore, the adaptive filter of the present invention performs stable position estimation using a small step size when estimating the position of the waveform response section, and uses a large step size when changing the tap position limited to the vicinity of the estimated waveform response section. - It is possible to perform high-speed convergence using the size and shorten the convergence time. Even if the initial tap placement is a tap with a small impulse response amplitude, the initial value is changed and the search for the waveform response section is started after a predetermined time, so the position of the waveform response section can be estimated quickly and reliably. can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing details of the tap circuit in FIG. 1;

FIG. 3 is a block diagram showing a specific example of the control circuit in FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a specific example of the control circuit shown in FIG. 4;

FIG. 6 is a block diagram showing another specific example of the control circuit in FIG. 4;

FIG. 7 is a block diagram showing an example in which a conventional adaptive filter is applied to an echo canceller.

FIG. 8 is a block diagram showing details of the tap circuit in FIG. 7.

FIG. 9 is a block diagram showing details of the coefficient generation circuit in FIG. 8;

FIG. 10 is a block diagram showing another example in which a conventional adaptive filter is applied to an echo canceller.

FIG. 11 is a block diagram showing details of the tap circuit in FIG. 10.

FIG. 12 is a block diagram showing details of the control circuit of FIG. 10;

[Explanation of symbols]

1 Input terminal 2 2-wire to 4-wire conversion circuit 3 Subtractor 4 Output terminal 10i (1≦i≦N) Delay element 11i (1
≦i≦M) Tap circuit 13 Control circuit 14 Matrix switch 41 Control circuit 42 Selector

Claims (1)

[Scope of Claims] [Claim 1] Multiplication is performed by adaptively combining a plurality of input signal samples delayed by one sample period with a plurality of multiplicands that are adaptively changed, and the multiplicands that are not used in the multiplication are multiplied. When approximating an unknown system with an adaptive filter that stores addresses in a queue and outputs the sum of the multiplication results, the flat delay of the unknown system is estimated under certain initial conditions, and the estimated flat delay is combining the multiplicand with a plurality of input signal samples that have undergone a delay approximately corresponding to the delay, updating the multiplicand value while varying the combination under certain restrictions, and estimating the flat delay. In this case, if the estimation is not completed within a predetermined number of repetitions, or if the reliability of the estimated value does not reach the predetermined value even after the estimation is completed, the process is delayed with a new initial value of the combination. A method for approximating an unknown system using an adaptive filter, characterized by performing estimation, and otherwise updating the multiplicand and replacing the multiplicand with the multiplicand corresponding to a value in a queue. 2. Estimating the flat delay is performed by updating the multiplicand while fixing the combination of the input signal sample and the multiplicand to a certain initial value, and monitoring the maximum absolute value of the plurality of multiplicands. 2. The method for approximating an unknown system using an adaptive filter according to claim 1, wherein the method is performed when a specific multiplicand is detected as the maximum value at a predetermined frequency. 3. Multiplicand updating after flat delay estimation is performed by updating the leading value in the queue to the end of the queue if the leading value in the queue is not within a predetermined range from the position of the maximum multiplicand value. This operation is repeated until a new queue head value within the predetermined range is obtained, and the position is evaluated for the new queue head value. The multiplicand corresponding to the address is set to be used for multiplication, the minimum absolute value of the multiplicand is detected, the address of the multiplicand corresponding to the minimum value is stored at the end of the queue, and the multiplicand is removed from the multiplication target. 3. The method of approximating an unknown system using an adaptive filter according to claim 1, wherein the setting of the new multiplicand and the storing of the minimum value address in a queue are repeated until a predetermined number of times is reached. 4. Determination of completion of estimation in estimating flat delay is performed when a certain multiplicand reaches the maximum at a predetermined frequency while the multiplicand is updated a predetermined number of times with the combination of input sample and multiplicand fixed. Claim 1, 2 or 3 characterized in that the method is carried out by being detected as a value.
A method of approximating an unknown system using an adaptive filter described in . 5. The method of approximating an unknown system using an adaptive filter according to claim 1, 2, 3, or 4, wherein the reliability of the estimated value is determined based on the magnitude of the multiplicand in addition to the maximum value of the multiplicand. . 6. Updating the multiplicand comprises multiplying an externally calculated error signal using a plurality of delayed input signal samples and an adaptive filter output to obtain a first multiplication result; Multiplying the result by a predetermined first constant to obtain a second multiplication result; adding the second multiplication result and the delayed second multiplication result to obtain an addition result; 6. The unknown system approximation by an adaptive filter according to claim 1, 2, 3, 4, or 5, wherein the adaptive filter is used for the addition after being delayed by one sample period, and the addition result is used as the updated multiplicand. the method of. [
7. The adaptive system according to claim 6, wherein the first constant is used for estimating the flat delay, and the predetermined second constant is used for updating the multiplicand after estimating the flat delay.・Method of approximating unknown systems using filters. 8. The adaptive system according to claim 4, 5, 6, or 7, wherein the predetermined frequency is defined as a specific multiplicand being detected as the maximum value consecutively a predetermined number of times. A method for approximating unknown systems using filters. 9. The adaptive method according to claim 4, 5, 6, or 7, wherein the predetermined frequency is determined by detecting a specific multiplicand as a maximum value exceeding a predetermined probability. A method for approximating unknown systems using filters. 10. Multiplying a delay element array consisting of a plurality of cascaded delay elements that delay an input signal by one sample period, and the output of each delay element constituting the delay element array by a coefficient corresponding to each delay element. a matrix switch that determines the connection relationship between the plurality of delay elements and the plurality of multiplier circuits, an adder that sums the outputs of the plurality of multiplier circuits, and the plurality of multiplier circuits. and a control circuit that receives the output of the matrix switch and generates a control signal for the matrix switch; a selector, a multiplier that multiplies the output of the first selector and the output of each of the delay elements to produce an output, and a coefficient generation circuit that selects either an error signal supplied from the outside or a zero. The control circuit includes an absolute value circuit that receives the coefficient generation circuit output and converts it into an absolute value, and a minimum value detection circuit that detects the minimum of the absolute value circuit outputs. a maximum value detection circuit for detecting the maximum of the absolute value circuit outputs; and a first circuit for delaying the output of the maximum value detection circuit.
a delay element, a first coincidence detection circuit that detects coincidence between the output of the first delay element and the output of the maximum value detection circuit, and a counter that coefficients the output of the first coincidence detection circuit;
a second delay element that delays the counter output;
a second coincidence detection circuit that determines whether the output of the delay element matches the output of the counter; a first comparison circuit that compares the output of the counter with a predetermined first constant; and the minimum value detection circuit. a first-in, first-out circuit that receives the output of the first comparator circuit, stores it in the deepest part of the stack, simultaneously outputs the value of the shallowest part, and rewrites all the contents of the stack in accordance with the output of the first comparison circuit, and the output of the first-in first-out circuit. and the output of the maximum value detection circuit, and determine whether the difference between the output of the first-in first-out circuit and the output of the maximum value detection circuit is less than or equal to a predetermined threshold; a determination circuit that feeds back the output of the first-in, first-out circuit to the first-in, first-out circuit; and a determination circuit that receives the output of the determination circuit and the output of the minimum value detection circuit, sequentially rewrites the memory contents, and outputs the second coincidence detection circuit. a first storage device that rewrites all stored contents using the output of the maximum value detection circuit in accordance with the output of the first comparison circuit; and the output of the third
a third selector that selects and outputs the output of the delay element according to the output of the counter; and a second storage device that stores data for resetting the first storage device;
a shift circuit that receives an output of the second storage device, shifts all 1 bits by the same amount, and supplies the output to the first storage device for rewriting the entire storage content, and at the same time changes the shift amount; a data conversion circuit that receives the output of the circuit, inverts all bits, and supplies a bit number of 1 to the first-in, first-out circuit for rewriting the stack contents, and converts the third selector output to the third delay. An unknown system approximation device using an adaptive filter, characterized in that the first and second selectors are controlled by the control signal, which is supplied to the element at the same time as the control signal. 11. The coefficient generation circuit includes a first multiplier that multiplies the output of each delay element by an error signal supplied from the outside, and a predetermined second constant that multiplies the output of the first multiplier. a second multiplier that multiplies the second multiplier, an adder that adds the output of the second multiplier and the output of a fourth delay element, which will be described later; 11. The unknown system approximation device using an adaptive filter according to claim 10, further comprising a fourth delay element that feeds back to the fourth delay element, and outputs the output of the delay element as a coefficient value. 12. A claim characterized in that the device comprises a fourth selector that switches between a predetermined second constant and a predetermined third constant, and the fourth selector is controlled by a counter output. Adaptive device according to item 10 or 11.
Unknown system approximation device using filters. 13. A second comparator circuit that receives and compares the output of the absolute value circuit and the output of the maximum value detection circuit, and A that receives the output of the second comparator circuit and the output of the counter and calculates a product set.
comprising at least an ND circuit and an OR circuit that receives the output of the first comparator circuit and the output of the AND circuit and takes a union, and controls the first-in first-out circuit and the first storage device with the output of the OR circuit; 13. An unknown system approximation device using an adaptive filter according to claim 10, wherein the contents are completely rewritten by signals respectively supplied from the data conversion circuit and the shift circuit. 14. The unknown system approximation device using an adaptive filter according to claim 10, 11, 12, or 13, wherein the counter is a coefficient for determining the continuity of the coincidence circuit output, and is reset when the output is not continuous. 15. The counter monitors the probability that the matching circuit output is determined to be a match, and is reset when the probability does not exceed a predetermined value.
14. An unknown system approximation device using an adaptive filter according to 11, 12 or 13.