JPH06232909A - Contention packet arbitration device - Google Patents

Abstract

PURPOSE:To reduce number of aborted packets due to an overflowed input buffer. CONSTITUTION:The device is provided with an input buffer section 30 storing cells, a decoder section 52 decoding a cell header and decoding an arbitration result, and a contention cell arbitration section 53 making arbitration of contention cells. When each input buffer 30n of the input buffer section 30 has a function to set a congestion indication flag to the cell header when its own buffer is in congestion. Arbitration circuits 53n, 53BC of a contention cell arbitration section 53 set priority of each input buffer 30n and have a function of selecting a buffer with highest priority as a survival buffer when any congestion buffer is in existence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competing packet arbitration device for a self-routing switch of a packet switch so that packets of the same destination are not simultaneously input to a switching network.

[0002]

2. Description of the Related Art Generally, in a packet switching system,
Packets are exchanged based on the destination information inserted in the packet header.

In this case, the packet destination changes randomly. Therefore, a plurality of packets having the same destination may be input to the switching network at the same time.

When such packet competition occurs,
It becomes impossible to exchange packets. Therefore,
The packet switch requires a device for arbitrating competing packets.

As such a competing packet arbitration device, conventionally, "" A study of high-speed switching switch ", IEICE Technical Research Report SE87-132 1987 1
There is a device described on February 18, ".

This device is provided with a buffer at the input stage of the switching network to arbitrate competing packets prior to packet switching.

FIG. 2 is a block diagram showing the configuration of a self-routing switch of a packet switch equipped with this competing packet arbitration device.

In the figure, 11 is an input buffer for temporarily accumulating packets input from the corresponding incoming lines. Reference numeral 12 is a switching network that switches the packets accumulated in each input buffer 11 and outputs the packets to the output line. Reference numeral 13 is a routing network that arbitrates competing packets having the same destination.

The route-around network 13 is composed of a bacha network 131 with a winning-behind reporting function and a winning-behind reporting circuit 132.

The bacha net 131 with the remaining winning report function is
The headers of the packets accumulated in the respective input buffers 11 are exchanged and supplied to the remaining winning report circuit 132.

The remaining winning report circuit 132 compares the destinations of packets for each header arrival terminal with one of the adjacent terminals, and outputs a winning report when the destinations are different and a losing report when the destinations are the same. To do. This report is sent back to the corresponding input buffer 11 by tracing the transmission route of the packet header.

This arbitration is repeated a plurality of times for each exchange cycle. In this case, the same packet header is output thereafter from the input buffer 11 which has received the winning report in a certain arbitration cycle. On the other hand, the next buffer header is output from the input buffer 11 that has received the loss report until it receives the winning report.

When the final arbitration cycle ends, the input buffer that has received the winning report reads and erases the packet that was the target of the winning report. The read packet is exchanged by the exchange network 12 in the next exchange cycle. On the other hand, the input buffer 11 that receives the loss report does not read or erase the packet.

[0014]

However, in the case of the above configuration, when the packets of the input buffer 11 in which a large number of packets are accumulated and the packets of the input buffer 11 in which a large number of packets do not compete with each other, which one of the input buffers 11 is given the winning report. I don't know

Therefore, there is a problem in that the input buffer 11 in which a large number of packets are accumulated overflows, and the packets are not accumulated in the input buffer 11 and are often discarded.

Therefore, an object of the present invention is to provide a contention packet arbitration device capable of reducing the discard of packets due to the overflow of the input buffer.

[0017]

In order to achieve the above object, the present invention comprises means for setting a priority for contention arbitration in each input buffer, and buffers having output requests to the same destination. Means to detect the buffer in the congestion state, and if the congestion buffer is not detected, the buffer with the highest priority is selected as the winning buffer from the output request buffers, and if the congestion buffer is detected, the congestion buffer A means for selecting the buffer having the highest priority as the winning buffer from the inside is provided.

[0018]

According to the above configuration, when the input buffers not in the congestion state and the input buffers in the congestion state compete with each other, the congestion buffer is preferentially selected. This can reduce packet discard due to buffer overflow.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In the following description, the present invention will be described as a representative case where the present invention is applied to contention arbitration in a self-routing switch of an asynchronous transfer mode (ATM) switch which is a kind of packet switch. FIG. 1 shows the overall configuration of this switch.

Further, in the following description, the case where the present invention is applied to competitive arbitration of a 4 × 4 switch having four incoming lines 210 to 213 and four outgoing lines 220 to 223 will be described as a representative example.

First, the overall structure of FIG. 1 will be described.

The illustrated self-routing switch has an input buffer section 30, a switching network 40, and a routing network 50.

The input buffer section 30 includes incoming lines 210 to 21.
The cells input from 3 are temporarily accumulated, and the accumulated cells are supplied to the switching network 40 on the basis of the arbitration result of the routing network 50. The switching network 40 switches the cell supplied from the input buffer unit 30 based on the destination information, and outputs the outgoing line 2
It outputs to 20-223. The routing network 50 arbitrates competing cells based on the cell headers accumulated in the input buffer unit 30 and reports the arbitration result to the input buffer unit 30.

The arbitration of the route routing network 50 is carried out in a pipeline manner with the exchange of the switching network 40, and the arbitration result in a certain exchange cycle is used for the arbitration of the contention cell in the next exchange cycle. Moreover, this arbitration is repeated several times in each exchange cycle.

The input buffer section 30 is provided with each incoming line 21n (n
= 0,1,2,3) corresponding to four input buffers 30
0 to 303. Each input buffer 30n temporarily stores cells input from the corresponding incoming line 21n.
The function of the input buffer 30n will be described later in detail.

The switching network 40 includes an input register unit (IRE
G) 41, a switch unit (SSW) 42, an output register unit (OREG) 43, a control unit (CONT) 44,
It has an incorrect routing detector (REER) 45.

Here, the input register section 41 has four input registers 410 to 4 corresponding to each input buffer 30n.
Have 13. Each input register 41n holds the cell supplied from the corresponding input buffer 30n for each exchange cycle.

The switch section 42 includes the input registers 41n.
The cells held in the cell are exchanged based on the destination information.

The output register section 43 has four output registers 430 to 433 corresponding to each outgoing line 22n. Each output register 430n holds the cell exchanged by the switch unit 42 and outputs it to the corresponding outgoing line 22n.

The control unit 44 controls the switching operation of the switching network 40 based on the reference clock signal CLK of the switch, the reset signal RST of the switch unit 42, and the like. The control unit 44 is also used to control the reroute network 50.

The erroneous routing detector 45 detects a cell having wrong destination information when it passes through the switch 42.

The routing network 50 includes an input register section (IRE
G) 51, a decoder unit (DEC) 52, and a contention cell arbitration unit (CAACK) 53.

Here, the input register section 51 has four input registers 510 to 5 corresponding to each input buffer 30n.
Have 13. Each input register 51n holds the cell header supplied from the corresponding input buffer 21n for each arbitration cycle.

The decoder section 52 includes the input registers 51n.
4 decoders 520 to 523 corresponding to Each decoder 52n decodes the cell header supplied from the corresponding input register 51n, supplies the decoding result to the contention cell arbitration unit 53, and the arbitration result of the contention cell arbitration unit 53, and decodes this decoding result RPT. Is supplied to the corresponding input buffer 30n. The function of the decoder 52n will be described in detail later.

The contention cell arbitration unit 53 has four outgoing line request buffer arbitration circuits 530 to 533 corresponding to each outgoing line 22n.
And a broadcast request buffer arbitration circuit 53BC.

Each outgoing line request buffer arbitration circuit 53n has a function of arbitrating a plurality of input buffers (hereinafter referred to as "outgoing line request buffers") 30n having an output request for the corresponding outgoing line n. The broadcast request buffer arbitration circuit 53BC includes a plurality of input buffers (hereinafter, referred to as “broadcast request buffer”) 30n having output requests to all outgoing lines 220 to 223.
It has the function of arbitrating. These arbitration circuits 53n and 53
The function of BC will be described in detail later.

The decoders 520-523 and the arbitration circuits 530-533, 53BC are mesh-connected. As a result, the decoding results of the decoders 520 to 523 can be transmitted to all the arbitration circuits 530 to 533, 53BC. In addition, the arbitration circuits 530 to 533, 5
The arbitration result of 3BC is returned to all the decoders 520 to 523.
You can reply to.

The above is the overall configuration of one embodiment. Next, the function of the input buffer 30n will be described with reference to FIG.

Here, FIG. 3 is a flow chart showing the operation of the input buffer 30n per one exchange cycle.

As shown, in this operation, first,
A process of supplying the header of the first cell to the corresponding input register 51n is performed (steps S11, S12, S1).
3). In this case, it is determined whether or not the own buffer is in a congestion state, and if it is in a congestion state, a process of setting a congestion display flag BAF at a predetermined position of the header is performed (step S
11, S12).

When this supply is completed, the competitive cell arbitration unit 5
Processing for determining whether or not the winning report WIN has been returned from 3 is performed (step S14). Here, the winning report WIN is a report indicating that the own buffer has won the arbitration.

When the winning report WIN is returned, a process for determining whether or not the final arbitration cycle is completed is performed (step S15). If the final arbitration cycle has not ended, the processes of steps S13 and S14 are performed again.

Once the winning report WIN is returned, the winning report WIN is also returned thereafter, as will be described later. This is to prevent the input buffer 30n that has once received the winning report WIN from receiving the losing report DEF thereafter. Therefore, in this case, the head cell header is output until the final arbitration cycle ends.

When the final arbitration cycle is completed, the head cell is supplied to the input register 41n of the switching network 50 and is erased from the buffer (step S16). As a result, in this case, the processing ends. The cells supplied to the input register 41 are exchanged by the exchange network 40 in the next exchange cycle.

On the other hand, if the winning report WIN is not returned, the process for supplying the header of the second cell is performed this time (steps S17, S18, S19). In this case as well, processing for raising the congestion display flag BAF is performed as necessary (steps S17 and S18).

When this process ends, the winning report W
Processing for determining whether or not IN has been returned is performed (step S20). If the winning report WIN is not returned, the process returns to step S17 via step S21, and the process of supplying the header of the third cell is performed.
Similarly, until the winning report WIN is returned,
The next cell header is sequentially supplied.

When the winning report WIN is returned, the process of outputting the cell header output in step S19 is repeated until the final arbitration cycle ends (steps S22, S23, S19). When the final arbitration cycle ends, the process of supplying the cell corresponding to this cell header to the corresponding input register 41n is performed (step S24).

On the other hand, if the winning report WIN is not returned, the process ends when the final arbitration cycle ends (step S21).

As described above, each input buffer 30n
Has a function of setting the congestion indicator flag BAF as necessary, a function of continuously outputting the cell header at the time of receiving the win report WIN, and a function of outputting the next cell header at the time of receiving the loss report DEF. Have.

Next, the function of the decoder 52n will be described with reference to FIGS. 4, 5, 6 and 7.

FIG. 4 is a diagram showing an example of the structure of cells stored in the input buffer 50n. The cell shown is 56
It consists of bytes worth of data, the first 3 bytes are assigned to the switching tag, and the remaining 53 bytes are assigned to the information field.

Of the switching tags, the first 1 byte is supplied to the decoder 52n as an arbitration cell header as shown in FIG. In this cell header, a cell valid flag CEF, a broadcast cell display flag BC, outgoing line number designation data S3 to S0, and a congestion display flag BAF are inserted. Note that R is a spare bit.

The cell valid flag CEF is a flag indicating whether or not the cell is a valid cell. Broadcast cell display flag BC
Is a flag indicating whether the cell is a broadcast cell. The outgoing line number designation data S3 to S0 are the outgoing lines 22 from which cells should be output.
It is data that specifies the number n of n. The buffer congestion display flag BAF is a flag indicating whether or not the input buffer 21n is in a congestion state.

The outgoing line number designating data S3 to S0 are represented by 4 bits, for example, and can correspond to a 16 × 16 switch. As in the present example, in the 4 × 4 switch, the lower 2 bits S
1 and S0 are not used, only the upper 2 bits S3 and S2 are used.

The cell valid flag CEF, the broadcast cell display flag BC, and the outgoing line number designation data S3 to S0 are
It is inserted in advance at the cell source. On the other hand, the congestion display flag BAF is inserted by the input buffer 30n as described above.

FIG. 6 is a flow chart showing the cell header decoding operation of each decoder 52n per exchange cycle.

In this cell header decoding operation, first, a process of determining whether or not the cell is a valid cell is performed based on the cell valid flag CEF (step S31).
If the cell is a valid cell, a process of determining whether or not the cell is a broadcast cell is performed based on the broadcast cell display flag BC (step S32).

In the case of a non-broadcast cell, a process of decoding the outgoing line number #n is performed based on the outgoing line number designation data S0 to S3 (step S33). When this decoding is finished,
Based on the congestion display flag BAF, a process of determining whether or not the corresponding input buffer 30n is in the congestion state is performed (step S34).

If it is in the congestion state, a process of transmitting the output request REQ and the congestion report OC to the output line request buffer arbitration circuit 53n corresponding to the output line number #n decoded in step S33 is performed (step S35). ). In contrast,
If it is not in the congestion state, a process of transmitting only the output request REQ is performed (step S36).

When it is determined in step S32 that the cell is a broadcast cell, the output request REQ is transmitted to the broadcast request buffer arbitration circuit 53BC (step S39,
S40, S41). Also in this case, the process of transmitting the congestion report OC is performed as necessary.

The above processing is continued until the final arbitration cycle ends (step S41). Then, when the final arbitration cycle ends, the processing ends.

When it is determined in step S31 that the cell is invalid, the processes of steps S41 and S31 are repeated. As a result, the arrival of valid cells is awaited. But,
In this case, since no cell is stored in the input buffer 30n, there is no possibility that a valid cell will be sent.

As described above, each decoder 52n is
It has a function of decoding the destination and the congestion state of the corresponding input buffer 30n and transmitting the decoding result to the contention cell arbitration unit 53.

FIG. 7 is a flowchart showing the arbitration result decoding operation of each decoder 52n per one exchange cycle.

In this arbitration result decoding operation, first,
Processing for determining whether or not the broadcast priority request BCSEL has been returned from the broadcast request buffer arbitration circuit 53BC is performed (step S41).

Here, the broadcast priority request BCSEL is the output request buffer arbitration circuit 5 for each decoder 52n.
Broadcast request buffer arbitration circuit 5 based on arbitration result ACK of 3n
This is a request to prioritize the decoding of the ACK of the arbitration result 3BC. That is, it is a request to give priority to decoding the arbitration result ACK of the broadcast cell over the arbitration result ACK of the non-broadcast cell.

This is because all outgoing lines 220 to
This is because 223 is requested, and thus when the broadcast cell and the non-broadcast cell compete with each other, the arbitration result ACK of the non-broadcast cell becomes meaningless.

When the broadcast priority request BCSEL is returned, the process of decoding the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC is executed even if the cell header decoding result is transmitted to the outgoing line request buffer arbitration circuit 53n. This is done (step S42). When this decryption is completed, the decryption result RPT is returned to the corresponding input buffer 30n (step S43).

In this case, when the corresponding input buffer 30n is the broadcast request buffer and the arbitration wins, the win report WIN is returned. On the other hand, if the player loses in this arbitration, or if the corresponding input buffer 30n is not the broadcast request buffer, the losing report DEF is returned.

This decoding and reply processing (steps S42, S
43) is repeated until the final arbitration cycle ends.

On the other hand, when the broadcast priority request BCSEL is not returned, the process of decoding the arbitration result ACK of the outgoing line request buffer arbitration circuit 53n which has transmitted the cell header decoding result and the process of transmitting this decoding result RPT. (Steps S45, S46). This process is also continued until the final arbitration cycle ends (step S4).
7). However, since the cell is an invalid cell, if there is no outgoing line request buffer 53n that has transmitted the result of decoding the cell header, processing for returning the loss report DEF is performed.

As described above, when there is a broadcast cell, the decoder 52n decodes the arbitration result ACK of the broadcast cell,
If there is no broadcast cell, the arbitration result ACK of the non-broadcast cell is decoded.

Next, the arbitration operation of the outgoing line request buffer arbitration circuit 53n per one exchange cycle will be described with reference to FIGS.

The output line request buffer arbitration circuit 53n is
The output line request buffer is arbitrated on the basis of the priority P determined in advance for each input buffer 30n. In this case, the priority P is cyclically changed in the switching cycle of the switching network 40. This is because all the input buffers 300 to 303 are given equal cell output opportunities.

FIG. 8 is a diagram showing an example of changing the priority P. As shown in FIG. In the N × N switch, there are n priorities P set in each input buffer 30n. Therefore,
There are four in a 4x4 switch. In FIG. 8, this priority P is represented by 0, 1, 2, 3. Here, 0 indicates the highest priority P, and 3 indicates the lowest priority P.

The priority P set in each input buffer 3n in a certain exchange cycle is used in a plurality of arbitrations performed in this exchange cycle. For example, J-1st (J =
In the exchange cycle of 2, 3, ...), the input buffer 300
Priority levels of 303 to 0 are 0, 1, 2, and 3, respectively. This priority P is used in a plurality of arbitrations performed in this J-1th exchange cycle.

FIG. 9 is a flowchart showing the arbitration operation of the outgoing line request buffer arbitration circuit 53n per exchange cycle.

In this arbitration operation, first, a process for determining whether or not there is an outgoing line request buffer is performed (step S51). This determination is made by monitoring whether or not the output request REQ has been sent.

If there is no output line request buffer, all the decoders 520 to 5 until the final arbitration cycle is completed.
Processing for returning the loss report DEF to 23 is performed (steps S52, S65, S51).

If there is an outgoing line request buffer, a process for determining whether there is one outgoing line request buffer is performed. (Step S53). If there is only one outgoing line request buffer, the winning report WIN is returned to this outgoing line request buffer, and the loss report DEF is returned to the other buffers (steps S54, S55).

This process is continued until the final arbitration cycle ends (step S56). Thus, once the outgoing line request buffer is determined, even if there is an outgoing line request buffer with a higher priority P thereafter, the arbitration result is not changed. This is because the input buffer 30n that has once received the winning report WIN, then receives the losing report DEF.
This is to prevent being received.

When the final arbitration cycle is completed, processing for changing the priority P is performed (step S57). As a result, in this case, the processing ends.

If it is determined in the above step S53 that there is not one outgoing line request buffer, it is determined whether or not there is a buffer in a congestion state (step S5).
8). This is done by monitoring whether a congestion report OC has been sent.

If there is a congestion buffer, the highest priority P buffer wins among the congestion buffers and reports WIN.
Is returned, and the loss report DEF is returned to the other buffers (including buffers other than the congestion buffer) (steps S59 and S60).

This processing is also continued until the final arbitration cycle is completed for the same reason as above (step S6).
1). Then, when the final arbitration cycle ends, the priority P is changed and the processing ends (step S57).

On the other hand, if there is no congestion buffer, the winning report WIN is returned to the buffer having the highest priority P among the outgoing line request buffers (step S6).
2). Other than that, it is the same as when there is a congestion buffer (steps S63, S64, S57).

In any of steps S59 and S62, once the output request buffer is determined, even if there is an output request buffer with a higher priority P, the arbitration result is not changed.

When it is determined in step S52 that the final arbitration cycle has ended, only the priority P is changed and the processing ends (step S57).

As described above, if there is a congestion buffer, each outgoing line request buffer arbitration circuit 53n returns the winning report WIN to the buffer with the highest priority P among the congestion buffers, and returns the congestion buffer. If there is not, the winning report WIN is returned to the buffer having the highest priority P in the outgoing line request buffer. When the final arbitration cycle ends, the priority P is changed.

Next, the arbitration operation of the broadcast request buffer arbitration circuit 53BC will be described with reference to FIG.

This arbitration operation is performed except for the first arbitration cycle and the point that, if there is a broadcast request buffer, the process of transmitting the broadcast priority request BCSEL to all the decoders 520 to 523 is performed. This is almost the same as the arbitration operation of the line request buffer arbitration circuit 53n.

That is, also in this arbitration operation, first, processing for determining whether or not there is a broadcast request buffer is performed (step S71). This determination is based on the output request RE
This is done by monitoring whether a Q has been sent.

When the output request REQ is sent, the broadcast priority request BCSE is sent to all the decoders 520 to 523.
Processing for returning L is performed (step S72). Thus, in each decoder 52n, as described above, the arbitration result of this arbitration circuit 53BC is decoded regardless of whether the arbitration circuit to which the decoder 52n has sent the output request REQ is the broadcast request buffer arbitration circuit 53BC. Is done.

Upon completion of this processing, a predetermined arbitration processing is performed according to whether or not there is one broadcast request buffer and whether or not there is a congestion buffer, as in the arbitration operation of the outgoing line request buffer (step S73). ~ S83). When this process ends, the priority P is changed and the process ends (step S84).

On the other hand, when it is determined in step S71 that there is no broadcast request buffer, the loss report DEF is returned to all the decoders 520 to 523 until the final arbitration cycle is completed (( Step S
85, 86). Then, when the final arbitration cycle ends, the priority P is changed and the process ends (step S
84).

The above is the configuration of the embodiment. Next, the operation of the above configuration will be described.

First, for reference, the exchange operation by the exchange network will be briefly described.

The cells input from each input line 21n are accumulated in the corresponding input buffer 30n one after another. This cell is read one by one based on the arbitration result of the routing network 50 in each exchange cycle, and the corresponding input register 41 is read.
Convert to a timing that can be processed by n.

The cell held in each input register 41n is supplied to the switch unit 42 and exchanged based on the destination information (outline number designation data S3 to S0, broadcast cell display flag BC). This exchanged cell is output through the output register 43n corresponding to the destination.

When the cell is a non-broadcast cell, it is output through the output register 43n corresponding to the outgoing line 22n specified by the outgoing line number specifying data S3 to S0. On the other hand, in the case of a broadcast cell, all output registers 250-
A cell is transmitted to 253.

The cell that has passed through each output register 25n is
It is output to the corresponding outgoing line 22n. At this time, if there is an erroneous destination cell, the erroneous routing detection circuit 45 detects it.

The above is the switching operation by the switching network 40. Next, the arbitration operation by the routing network 50, which is a feature of the present invention, will be described with a specific example.

(1) First, the case where only the non-broadcast cell is stored at the head of each input buffer 30n and the broadcast cell is not stored will be described.

As shown in FIG. 11, the priority P of each input buffer 30n is 303 → 302 in descending order.
It is assumed that the settings are such that → 301 → 300. Further, among the input buffers 30n, it is assumed that only the input buffers 303 and 302 are in the congestion state. Further, the leading cells of the input buffers 303, 302, 301 all request the outgoing line 223 (outgoing line number # 3),
It is assumed that the leading cell of the input buffer 300 requests the outgoing line 222 (outgoing line number # 2).

In this case, the output request REQ is sent to the decoder 5
Outgoing line request buffer arbitration circuit 5 from 23,522,521
It is also supplied to the output line request buffer arbitration circuit 532 from the decoder 520. Further, the congestion report OC is supplied from the decoders 523 and 522 to the outgoing line request buffer arbitration circuit 533.

As a result, the output line request buffer arbitration circuit 5
At 33, any one of the outgoing line request buffers 303, 302, 301 is selected. In the present example, 30 of the outgoing line request buffers 303, 302, 301
3, 302 is a congestion buffer, and this congestion buffer 3
Since the priority P of the buffer 303 of 03 and 302 is high, this buffer 303 is selected.

Thus, in this case, the decoder 523
Win report WIN is returned and decoders 522, 52
The loss report DEF is returned to 1,520.

In the output line request buffer arbitration circuit 522, since there is only one output line request buffer, the input line buffer 300 which is the output line request buffer is selected. Accordingly, in this case, the decoder 520 wins the report WI.
N is returned and the loss report DEF is returned to the decoders 523, 522 and 521.

Further, the output line request buffer arbitration circuit 53.
In Nos. 1 and 530, since there is no outgoing line request buffer, the process of returning the loss report DEF to all the decoders 520 to 523 is performed. Similarly, the broadcast request buffer arbitration circuit 5
In 3BC, since there is no broadcast request buffer, processing for returning the loss report DEF to all the decoders 520 to 523 is performed.

Note that FIG. 11 shows only the reply of the loss report DEF to the decoder 52n which has sent the output request REQ. This also applies to the following figures.

Since the decoders 523, 522 and 521 have sent the output request REQ to the output line request buffer arbitration circuit 533, the arbitration result ACK of this arbitration circuit 533 is decoded,
This decryption result RPT corresponds to the corresponding input buffer 303, 3
Reply to 02,301. This allows the input buffer 3
03 receives the winning report WIN and receives the input buffers 302, 3
01 receives the loss report DEF.

Since the decoder 520 has sent the output request REQ to the output line request buffer arbitration circuit 532, it decodes the arbitration result ACK of this arbitration circuit 532 and returns it to the corresponding input buffer 300. As a result, the input buffer 300 receives the winning report WIN.

In the next arbitration cycle, as shown in FIG. 12, the input buffers 303 and 30 which received the winning report WIN are received.
From 0, the header of the first cell is read again. On the other hand, the input buffers 302 and 3 which received the loss report DEF
From 01, the header of the second cell is read.

Now, the second cells of the input buffers 302 and 301 are output lines 222 (outline number # 2) and 22 respectively.
It is assumed that 1 (outgoing line number # 1) is requested.

In this case, since there is no conflicting buffer for the outgoing line 221, the winning report WIN is returned to the input buffer 301.

On the other hand, for the output line 222, the input buffers 302 and 300 compete with each other. In this case, since the input buffer 302 is in a congestion state, this buffer 302 is normally selected.

However, the input buffer 300 is fixed as the outgoing line request buffer for the outgoing line 222 at the first arbitration. Therefore, in this case, the input buffer 300
To the input buffer 302, and a loss report DEF is returned to the input buffer 302.

Since the buffer 303 is determined as the outgoing line request buffer in the first arbitration, the winning report WIN is returned to the input buffer 303 again.

In the next arbitration cycle, in the first arbitration, the input buffers 303 and 300 which have received the winning report WIN are received.
From the input buffer 301 which has received the winning report WIN in the second arbitration, and the second cell is read. On the other hand, still
Input buffer 302 that has not received the winning report WIN
From, the header of the third cell is read.

This cell is connected to the output line 2 as shown in FIG.
If it requests 20 (outline number # 0), the outbound request buffer arbitration circuit 300 returns a win report WIN to the input buffer 502. On the other hand, if the request is for an outgoing line 22n other than the outgoing line 220, the loss report DE
F is returned.

Similarly, the above-described operation is repeated until the final arbitration cycle ends.

When the final arbitration cycle ends, the input buffer 30 which has received the winning report WIN in the first arbitration
The head cell is read out from 3,300 and supplied to the corresponding input registers 413, 410. After that, the top cell is erased.

The second cell is read from the input buffer 301 which has received the winning report WIN in the second arbitration and is supplied to the corresponding input register 411.
After this, the second cell is erased.

Further, when the winning report WIN is received from the input buffer 302, the cell at that time is read out and erased. The read cell is the input register 412.
Is supplied to. On the other hand, until the end, win report WIN
If not received, the cell is read and erased.

(2) Next, the operation when the head cell includes a broadcast cell will be described.

Now, as shown in FIG. 14, the input buffer 3
It is assumed that a non-broadcast cell is stored at the beginning of 03 and a broadcast cell is stored at the beginning of the input buffers 302, 301 and 300.

The priority P and the congestion state are the same as in the case of FIG. Also, lose report DEF
Regarding the decoder 52 which has sent the output request REQ
Only those for n are shown.

In this case, the output request REQ is sent to the decoder 5
23 is supplied to the outgoing line request buffer arbitration circuit 533, and is also supplied from the decoders 522, 521 and 520 to the broadcast request buffer arbitration circuit 53BC.

Also, the congestion report OC is supplied from the decoder 523 to the outgoing line request buffer arbitration circuit 533, and from the decoder 522 the broadcast request buffer arbitration circuit 53.
Supplied to BC.

As a result, the output line request buffer arbitration circuit 5
From 33, the win report WIN is returned to the decoder 523, and the loss report DE is sent to the decoders 522, 521, 520.
F is returned. This state is maintained until the end of the final arbitration cycle.

The broadcast request buffer arbitration circuit 53BC
From, the winning report WIN is returned to the decoder 522,
The loss report DEF is returned to the decoders 523, 521 and 520. This state is maintained until the end of the final arbitration cycle.

Further, the output line request buffer arbitration circuit 53.
From 2,531,530 all decoders 520-520
The loss report DEF is returned to 523.

At this time, all the decoders 520 to 523 are sent from the broadcast request buffer arbitration circuit 53BC.
To the broadcast priority request BCSEL.

As a result, the decoders 522, 521, 5
At 20, the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC is decoded until the final arbitration cycle ends.

Similarly, the decoder 523 sends the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC until the final arbitration cycle ends even though the output request REQ is sent to the output line request buffer arbitration circuit 533. Decoding is done.

As a result, the input buffer 302 receives the winning report WIN until the final arbitration cycle ends, and the other input buffers 303, 301, 300 output the loss report DEF until the final arbitration cycle ends. receive. As a result, in the next exchange cycle, the broadcast cell read from the beginning of the input buffer 302 is exchanged.

(3) Finally, all input buffers 30
The operation when no cells are stored in 0 to 303 will be described.

In this case, since the output request REQ is not output at all, each input buffer 30n receives the loss report DEF in every arbitration cycle. As a result, no cell is read or erased in any of the input buffers 30n.

The above is the arbitration operation of the Negamare net 50.
This arbitration operation can be equivalently expressed as in the flowchart of FIG.

That is, this arbitration operation is divided depending on whether it is the first arbitration (step S81). If it is the first time arbitration, it is determined whether or not there is an input buffer 30n in which valid cells are accumulated (step S82).

Input buffer 3 storing valid cells
If there is not 0n, the arbitration operation is substantially finished. In this case, the loss report DEF is returned to all the input buffers 300 to 303.

On the other hand, if there is at least one input buffer 30n in which valid cells are stored, it is determined whether or not a broadcast cell is included therein (step S83). If the broadcast cell is included, mediation processing of the broadcast cell is performed (step S84). As a result, in this case, the arbitration operation is substantially finished, and the arbitration result of the broadcast cell causes the arbitration of the conflicting cell.

On the other hand, if the broadcast cell is not included, the arbitration process of the non-broadcast cell is performed for each outgoing line 22n (step S85). This arbitration is performed in each arbitration cycle.

In this arbitration, non-broadcast cells are independently determined for each outgoing line 22n (step S86).
For the outgoing line 22n for which the non-broadcast cell is determined, the arbitration process is substantially finished at that point. On the other hand, with respect to the outgoing line 22n for which the non-broadcast cell is not determined, the arbitration process is continued until the final arbitration cycle ends (step S87).

The above is the configuration and operation of one embodiment.

By the way, in the above description, the decoder 52
n, the output line request buffer arbitration circuit 53n, and the broadcast request buffer arbitration circuit 53BC have been described with reference to the flowcharts.

Therefore, these circuits may be realized by either hardware or software as long as they have the functions shown in the above-mentioned flowcharts.

However, the ATM switch is usually required to have high speed. Therefore, when implementing these circuits, it is preferable to implement them by hardware.

FIG. 16 and FIG. 17 are block diagrams showing an example of a concrete configuration when these circuits are realized by hardware.

First, referring to FIG. 16, the decoder 5
The 2n hardware configuration will be described. As illustrated, the decoder 52n includes a CEF decoder 1A, an SIU decoder 2A, a BC decoder 3A, a PRI decoder 4A, and
It has an ACK decoder 5A.

Here, the CEF decoder 1A determines whether or not the cell is a valid cell based on the cell valid flag CEF. The result of this determination is used to control the decoders 2A, 3A, 4A. That is, the decoders 2A, 3A, 4A
Operates only when the cell is determined to be a valid cell, and does not operate when it is determined to be an invalid cell.

SIU decoder 2A decodes outgoing line number #n based on outgoing line number designating data S3 to S0. When the output line number n is determined by this decoding, the SIU decoder 2A sends an output request REQ to the output line request buffer arbitration circuit 53n corresponding to the output line number #n.

The BC decoder 3A determines whether or not the cell is a broadcast cell based on the broadcast cell display flag BC. When it is determined that the cell is a broadcast cell by this determination, the output request REQ is transmitted from the decoder 3A to the broadcast request buffer arbitration circuit 53BC.

The PRI decoder 4A determines whether or not the input buffer 30n is in the congestion state based on the buffer congestion display flag BAF. When it is determined by this determination that the congestion state is present, the decoder 4A is sent to the arbitration circuit 53n or 53BC to which the output request REQ is transmitted.
Sends a congestion report OC.

The ACK decoder 5A has its own decoder 52n.
Arbitration circuit 53n or 53 which sent the output request REQ
Decode the arbitration result ACK from BC. This decryption result R
The PT is supplied to the corresponding input buffer 30n.

Upon receiving the broadcast priority request BCSEL, the ACK decoder 5A decodes the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC regardless of the destination of the output request REQ. This state is maintained until the end of the final arbitration cycle.

In FIG. 16, REQ, OC, A
The reference numerals in parentheses attached to CK indicate these transmission sources and transmission destinations. In this case, the code on the left side of the parentheses indicates the transmission source, and the code on the right side indicates the transmission destination.

For example, REQ (n, 3) is the decoder 5
The output request supplied from the 2n SIU decoder 2A to the output line request buffer arbitration circuit 533 is shown. This is the same also in FIG. 16 described later.

The above is an example of the hardware configuration of the decoder 52n. Next, the hardware configuration of the arbitration circuits 53n and 53BC will be described with reference to FIG. First, the hardware configuration of the outgoing line request buffer arbitration circuit 53n will be described.

As shown in the figure, the arbitration circuit 53n includes a priority setting circuit 1B, an output request buffer selection circuit 2B, and
Congestion buffer selection circuit 3B and winning buffer selection circuit 4
B, and an arbitration result output circuit 5B.

Here, the priority setting circuit 1B rearranges the decoding results of each decoder 52n based on the priority P predetermined for each input buffer 30n. This priority P
Is cyclically changed in the cell replacement cycle based on the control signal ROT supplied from the control unit 44.

Among the decoding results rearranged based on the priority P, the output request REQ is supplied to the output request buffer selection circuit 2B, and the congestion report OC is supplied to the congestion buffer selection circuit 3B.

The output request buffer selection circuit 2B outputs the loss report DEF to all four output terminals when there is no output request REQ at the input. On the other hand, when one output request REQ is included, the win report WIN is output to the output terminal corresponding to this output request REQ, and the loss report DEF is output to the other three output terminals.

When a plurality of output requests REQ are included, the winning report W is output to the output terminal corresponding to the output request REQ having the highest priority P among the plurality of output requests REQ.
IN is output, and the loss report DEF is output to the other three output terminals.

Similarly, if no congestion report OC is included in the input, the congestion buffer selection circuit 3B outputs the loss report DEF to all four output terminals. On the other hand, when one congestion report OC is included, the win report WIN is output to the output terminal corresponding to this congestion report OC, and the loss report DEF is output to the other three output terminals.

When a plurality of congestion report OCs are included, the winning report WIN is output to the output terminal corresponding to the congestion report OC having the highest priority P among the plurality of congestion report OCs, and the other three are output. Output terminal DE
Output F.

If the winning report WIN is not supplied from the output request buffer selecting circuit 2B and the congestion buffer selecting circuit 3B, the winning buffer selecting circuit 4B outputs the losing report DEF to the four output terminals.

On the other hand, the output request buffer selection circuit 2
When the winning report WIN is supplied only from B, the winning report WIN is output to the output terminal corresponding to this winning report WIN, and the losing report DEF is output to the other three output terminals.
Is output.

On the other hand, when the win report WIN is also supplied from the congestion buffer selection circuit 3B, the win report WIN from the congestion buffer selection circuit 3B is sent regardless of the win report WIN from the output request buffer selection circuit 2B. The win report WIN is output to the corresponding output terminal, and the loss report DEF is output to the other three output terminals.

This control is performed by a control signal BAFS indicating whether or not the congestion report OC is included in the decoding result of the decoder 52n.
Made by EL. This control signal BAFSEL is generated by the priority setting circuit 1B.

The arbitration result output circuit 5B, when the winning report WIN is not supplied from the winning buffer selection circuit 4B,
The loss report DEF is output to the four output terminals. On the other hand, when the win report WIN is supplied, the win report WIN is output to the output terminal corresponding to the win report WIN,
The loss report DEF is output to the other three output terminals.

In this case, the arbitration result output circuit 5B rearranges the inputs in the reverse order of the priority setting circuit 1B and outputs the rearranged inputs. As a result, even if the priority P is changed,
Arbitration result ACK without causing hardware complexity
Can be reported.

In addition, the arbitration result output circuit 5B first
When the winning report WIN is output, the output state at that time is held until the final arbitration cycle ends. This is to prevent the input buffer 30n that has once received the winning report WIN from receiving the losing report DEF thereafter, as described above.

As a result, once the winning report WIN is output, the arbitration result will not be changed even if the output request buffer having a higher priority P is selected thereafter.

The above is the output line request buffer arbitration circuit 53n.
It is the structure of. Next, the broadcast request buffer arbitration circuit 53B
The configuration of C will be described.

The structure of the broadcast request buffer arbitration circuit 53BC is also substantially the same as the structure of the outgoing line request buffer arbitration circuit 53n.

The difference lies in the arbitration result output circuit 5B.
However, at the end of the first arbitration cycle, the winning report W
That is, the output state is maintained regardless of whether or not IN is output. This is because, as described above, the arbitration of the broadcast cell is performed only in the first arbitration cycle.

Next, the winning buffer selection circuit 4B outputs a broadcast priority request BCSEL when there is a broadcast cell in the first arbitration cycle. This is to prioritize the arbitration of broadcast cells, as described above.

The above is the description of the decoder 52n and the arbitration circuit 53.
It is an example of a specific hardware configuration of n, 53BC.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, the priority P is set in each input buffer 30n, the input buffer 30n in the congestion state is detected, and the buffer with the highest priority P is selected as the winning buffer from the congestion buffers. Since the selection is made, the cell discard due to the overflow of the input buffer 30n can be reduced.

(2) Further, since the priority P of each input buffer 30n is cyclically changed in the exchange cycle, the read opportunities can be evenly given to each input buffer 30n. This allows the same input buffer 30
You can keep n from losing.

(3) Furthermore, when a broadcast cell and a non-broadcast cell compete with each other, the broadcast cell is made to win first, so that the broadcast cell can be prevented from losing.

(4) Since the arbitration of the broadcast cell is performed only in the first arbitration cycle, even if the broadcast cell appears in the arbitration cycle in the middle, the arbitration result of the non-broadcast cell up to that point is wasted. You can choose not to.

(5) Further, when the route routing network 50 is configured by hardware, it can be configured by the decoder 52n and the like, so that a hardware configuration which does not burden the device can be adopted.

In other words, conventionally, as shown in FIG. 2, since the routing circuit 13 is constructed by using the binary elements, high speed operation is required for the circuit operation, and some devices constituting the circuit can operate at high speed. There was a problem of being requested.

On the other hand, in this embodiment, since the rooting network 50 can be constructed by using a decoder or the like which can operate at a lower speed, such a problem does not occur.

(6) Further, when the arbitration circuits 53n and 53BC are configured by hardware, the arbitration result output circuit 5B for performing rearrangement opposite to the priority setting circuit 1B is provided in the output stage. The priority P can be changed without causing the hardware to be complicated.

Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment.

(1) For example, in the previous embodiment, the input buffer 30n that once received the winning report WIN by holding the output states of the arbitration circuits 53n and 53BC.
Explained how to prevent later receiving a loss report DEF. However, in the present invention, for example, the decoder 5
The above function may be obtained by holding the decoding state of the arbitration result ACK in 2n.

(2) In the above embodiment, the arbitration result A
Even after CK is confirmed, the input buffer 30n and the decoder 5
The case where 2n and the arbitration circuits 53n and 53BC are operated has been described. However, in the present invention, these may not be operated after the arbitration result ACK is confirmed.

(3) Further, in the above embodiment, the priority P
The case of changing to cyclic was explained. However, according to the present invention, when cells are accumulated in a specific input buffer 30n in a biased manner, the input buffer 30n may always be given a high priority P and the priority P may not be changed.

(4) Further, in the above embodiment, the case where the present invention is applied to the arbitration of the cell which is a kind of packet has been described, but the present invention can be applied to the arbitration of general packets.

(5) In addition to this, it goes without saying that the present invention can be variously modified without departing from the scope of the invention.

[0197]

As described above, according to the present invention,
It is possible to provide a contention packet arbitration device capable of reducing the discard of packets due to the overflow of the input buffer.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional contention packet arbitration device.

FIG. 3 is a flowchart showing an operation of an input buffer 30n.

FIG. 4 is a diagram showing the structure of a cell.

FIG. 5 is a diagram showing a structure of a cell header.

FIG. 6 is a flowchart showing a cell header decoding operation of a decoder 52n.

FIG. 7 is a flowchart showing an arbitration result decoding operation of a decoder 52n.

FIG. 8 is a diagram showing a change in priority P.

FIG. 9 is a flowchart showing an operation of an output line request buffer arbitration circuit 53n.

FIG. 10 is a flowchart showing an operation of a broadcast request buffer arbitration circuit 53BC.

FIG. 11 is a diagram showing an example of an arbitration operation of a non-broadcast cell.

FIG. 12 is a diagram showing an example of an arbitration operation of a non-broadcast cell.

FIG. 13 is a diagram showing an example of an arbitration operation of a non-broadcast cell.

FIG. 14 is a diagram showing an example of an arbitration operation of a broadcast cell.

FIG. 15 is a flowchart equivalently showing an arbitration operation of the routing network 50.

FIG. 16 is a block diagram showing an example of a specific configuration of a decoder 52n.

FIG. 17 is a block diagram showing an example of a specific configuration of arbitration circuits 53n and 53BC.

[Explanation of symbols]

210-213 ... incoming line, 220-223 ... outgoing line, 30 ...
Input buffer unit, 300 to 303 ... Input buffer, 40
... switching network, 41 ... input register section, 410-413 ... input register, 42 ... switch section, 43 ... output register section, 430-433 ... output register, 44 ... control section, 4
5 ... False routing detection unit, 50 ... Negate network, 51 ... Input register unit, 510-513 ... Input register, 52 ...
Decoder section, 520-523 ... Decoder, 53 ... Competitive cell arbitration section, 530-533 ... Outgoing line request buffer arbitration circuit, 53BC ... Broadcast request buffer arbitration circuit, 1A ... CE
F decoder, 2A ... SIU decoder, 3A ... BC decoder, 4A ... PRI decoder, 5A ... ACK decoder, 1
B ... Priority setting circuit, 2B ... Output request buffer selection circuit, 3B ... Congestion buffer selection circuit, 4B ... Winning buffer selection circuit, 5B ... Arbitration result output circuit.

Claims (2)

[Claims] 1. A contention packet arbitration apparatus for providing an input buffer for temporarily accumulating packets for each incoming line and arbitrating packets having the same destination prior to packet exchange. Priority setting means for setting priority for performing, output request buffer detection means for detecting a buffer having an output request to the same destination from the input buffer, and output detected by the output request buffer detection means Congestion buffer detection means for detecting a buffer in a congestion state from among the request buffers, and if no congestion buffer is detected by this congestion buffer detection means, in the output request buffer detected by the output request buffer detection means From the highest priority set by the priority setting means, When the congestion buffer is detected by the first winning buffer selection means and the congestion buffer detection means, the priority set by the priority setting means is the highest among the detected congestion buffers. A competing packet arbitration device comprising: a second winning buffer selecting means for selecting a high buffer as a winning buffer. 2. The contention packet arbitration device, wherein the priority setting means is configured to cyclically change the priority in accordance with the packet exchange cycle.