JP2977402B2 - Contention packet arbiter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a competing packet arbitration apparatus for preventing packets having the same destination from being simultaneously input to a switching network in a self-routing switch of a packet switch.

[0002]

2. Description of the Related Art Generally, in a packet switching system,
Packets are exchanged based on the destination information inserted in the packet header.

In this case, the destination of a packet changes randomly. Therefore, a plurality of packets having the same destination may be simultaneously input to the switching network.

[0004] When such packet contention occurs,
Packets cannot be exchanged. Therefore,
In a packet switch, a device for arbitrating competing packets is required.

[0005] As such a competing packet arbitration apparatus, conventionally, "" Study of high-speed switching switch "" IEICE technical report SE87-132 1987/1
There is a device described in "February 18".

In this apparatus, a buffer is provided at an input stage of a switching network, and arbitration of competing packets is performed prior to packet exchange.

FIG. 2 is a block diagram showing a configuration of a self-routing switch of a packet switch provided with the competing packet arbitration device.

In FIG. 1, reference numeral 11 denotes an input buffer for temporarily storing packets input from a corresponding input line. A switching network 12 switches packets stored in each input buffer 11 and outputs the packets to an output line. Reference numeral 13 denotes a negotiation network for arbitrating competing packets having the same destination.

The root network 13 is composed of a batcher network 131 with a residual report function and a residual report circuit 132.

[0012] The batcher network 131 with the residual report function is:
The headers of the packets stored in each input buffer 11 are exchanged and supplied to the winning report circuit 132.

[0011] The winning residual report circuit 132 compares the destination of the packet with one of the adjacent terminals for each header arrival terminal, and outputs a winning report if the destination is different and a loss report if the destination is the same. I do. This report is returned to the corresponding input buffer 11 tracing the transmission route of the packet header.

This arbitration is repeated a plurality of times for each exchange cycle. In this case, the same packet header is thereafter output from the input buffer 11 that has received the winning report in a certain arbitration cycle. On the other hand, from the input buffer 11 receiving the loss report, the next packet header is output until the winning report is received.

When the final arbitration cycle is completed, the input buffer receiving the win report reads and deletes the packet for which the win report has been made. The read packets are exchanged by the exchange network 12 in the next exchange cycle. On the other hand, the input buffer 11 receiving the loss report does not read or delete the packet.

[0014]

However, in the case of the above configuration, when a packet in the input buffer 11 in which a large number of packets are stored and a packet in the input buffer 11 in which the packet does not compete with each other, a winning report is given to one of the input buffers 11. I don't know

Therefore, the input buffer 11 in which a large number of packets are stored overflows, and the packet is not stored in the input buffer 11 and is often discarded.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a contention packet arbitration apparatus which can reduce packet discards caused by overflow of an input buffer.

[0017]

In order to achieve the above object, the present invention provides (1) one input buffer for each input buffer ;
If you set a priority for contention arbitration that is in effect during the
In each case, each input battery is linked with the switching of the exchange cycle.
Priority setting means for cyclically changing the priority of the file , (2) output request buffer detection means for detecting a buffer having an output request of the same destination from the input buffers,
(3) When the congestion buffer is not detected by the congestion buffer detecting means, the priority in the switching cycle set by the priority setting means is the highest among the output request buffers detected by the output request buffer detecting means. A first winning buffer selecting means for selecting a high buffer as a winning buffer; and (4) when a congestion buffer is detected by the congestion buffer detecting means, the priority setting means selects the congestion buffer from the detected congestion buffers. Set
A second winning buffer selecting means for selecting a buffer having the highest priority in the exchange cycle as a winning buffer is provided.

[0018]

According to the above configuration, when an input buffer that is not in a congestion state and an input buffer that is in a congestion state compete with each other, the congestion buffer is preferentially selected. As a result, it is possible to reduce packet discarding due to buffer overflow. Note that the input buffer is in the congested state.
Congestion, the congestion buffer with the highest priority
Selected preferentially. Moreover, the priority depends on the exchange cycle.
All input buffers are changed cyclically.
It is possible to evenly give a packet output opportunity to the client.

[0019]

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

In the following description, a case where the present invention is applied to contention arbitration in a self-routing switch of an asynchronous transfer mode (ATM) switch which is a kind of a packet switch will be described as a representative. FIG. 1 shows the overall configuration of this switch.

In the following description, a case where the present invention is applied to competitive arbitration of a 4 × 4 switch having four input lines 210 to 213 and four output lines 220 to 223 will be described as a representative.

First, the overall configuration of FIG. 1 will be described.

The illustrated self-routing switch has an input buffer unit 30, a switching network 40, and a routing network 50.

The input buffer unit 30 has input lines 210 to 21.
3 is temporarily stored, and the stored cells are supplied to the switching network 40 based on the arbitration result of the negotiation network 50. The switching network 40 exchanges the cells supplied from the input buffer unit 30 based on the destination information, and
20 to 223. The negotiation network 50 arbitrates for competing cells based on the header of the cell stored in the input buffer unit 30 and reports the arbitration result to the input buffer unit 30.

The arbitration of the negotiation network 50 is performed in a pipeline manner with the exchange of the exchange network 40, and the arbitration result in one exchange cycle is used for arbitration of competing cells in the next exchange cycle. This arbitration is repeated several times in each exchange cycle.

The input buffer unit 30 is connected to each input line 21n (n
= 0, 1, 2, 3).
0-303. Each input buffer 30n temporarily stores cells input from corresponding input line 21n.
The function of the input buffer 30n will be described later in detail.

The switching network 40 has an input register section (IRE
G) 41, a switch unit (SSW) 42, an output register unit (OREG) 43, a control unit (CONT) 44,
It has an erroneous routing detector (REER) 45.

Here, the input register section 41 has four input registers 410 to 4 corresponding to each input buffer 30n.
13. Each input register 41n holds a cell supplied from the corresponding input buffer 30n for each exchange cycle.

The switch section 42 is connected to each input register 41n.
Are exchanged based on the destination information.

The output register section 43 has four output registers 430 to 433 corresponding to the respective outgoing lines 22n. Each output register 430n holds the cell exchanged by the switch unit 42 and outputs it to the corresponding outgoing line 22n.

The control unit 44 controls the switching operation of the switching network 40 based on the reference clock signal CLK of the switch, the reset signal RST of the switch unit 42, and the like. Note that the control unit 44 is also used for controlling the network 50.

The erroneous routing detecting section 45 detects, when a cell having erroneous destination information has passed through the switch section 42, this.

The network 50 is provided with an input register section (IRE).
G) 51, a decoder unit (DEC) 52, and a competing cell arbitration unit (CAACK) 53.

Here, the input register section 51 has four input registers 510 to 5 corresponding to each input buffer 30n.
13. Each input register 51n holds a cell header supplied from the corresponding input buffer 21n for each arbitration cycle.

The decoder section 52 is provided with each input register 51n.
And four decoders 520 to 523 corresponding to. Each decoder 52n decodes the cell header supplied from the corresponding input register 51n, and supplies the decoding result to the competing cell arbitration unit 53, and decodes the arbitration result of the competition cell arbitration unit 53. To the corresponding input buffer 30n. The function of the decoder 52n will be described later in detail.

The competing cell arbitration unit 53 comprises four output request buffer arbitration circuits 530 to 533 corresponding to each output line 22n.
And a broadcast request buffer arbitration circuit 53BC.

Each of the outgoing line request buffer arbitration circuits 53n has a function of arbitrating a plurality of input buffers (hereinafter, referred to as "outgoing line request buffers") 30n which have an output request for the corresponding outgoing line n. The broadcast request buffer arbitration circuit 53BC includes a plurality of input buffers (hereinafter, referred to as “broadcast request buffers”) 30n that have output requests for all the outgoing lines 220 to 223.
It has a function to arbitrate. These arbitration circuits 53n, 53
The function of the BC will be described later in detail.

The decoders 520 to 523 and the arbitration circuits 530 to 533 and 53BC are mesh-connected. Thus, the decoding results of the decoders 520 to 523 can be transmitted to all the arbitration circuits 530 to 533 and 53BC. The arbitration circuits 530 to 533, 5
The arbitration result of 3BC indicates that all the decoders 520 to 523
You can reply to

The above is the overall configuration of the embodiment. Next, the function of the input buffer 30n will be described with reference to FIG.

FIG. 3 is a flowchart showing the operation of the input buffer 30n per exchange cycle.

As shown, in this operation, first,
A process of supplying the header of the first cell to the corresponding input register 51n is performed (steps S11, S12, S1).
3). In this case, it is determined whether or not the own buffer is in a congestion state. If the buffer is in a congestion state, a process of setting a congestion display flag BAF at a predetermined position of the header is performed (step S).
11, S12).

When this supply is completed, the competing cell arbitration unit 5
A process is performed to determine whether or not a win report WIN has been returned from 3 (step S14). Here, the win report WIN is a report indicating that the own buffer has won the arbitration.

When the win report WIN is returned, a process for determining whether or not the final arbitration cycle has been completed is performed (step S15). If the final arbitration cycle has not ended, the processes of steps S13 and S14 are performed again.

Once the win report WIN is returned, the win report WIN is returned thereafter as described later. This is to prevent the input buffer 30n that has once received the win report WIN from subsequently receiving the loss report DEF. Therefore, in this case, the head cell header is output until the final arbitration cycle ends.

When the final arbitration cycle is completed, the head cell is supplied to the input register 41n of the switching network 50, and the cell is erased from the buffer (step S16). Thus, in this case, the process ends. The cells supplied to the input register 41 are exchanged by the exchange network 40 in the next exchange cycle.

On the other hand, if the win report WIN is not returned, processing for supplying the header of the second cell is performed (steps S17, S18, S19). Also in this case, a process of setting the congestion display flag BAF is performed as needed (steps S17 and S18).

When this process ends, the winning report W
Processing is performed to determine whether IN has been returned (step S20). If the win report WIN has not been returned, the process returns to step S17 via step S21, and processing for supplying the header of the third cell is performed.
Hereinafter, similarly, until the win report WIN is returned,
The next cell header is sequentially supplied.

When the win report WIN is returned, the process of outputting the cell header output in step S19 is repeated until the final arbitration cycle ends (steps S22, S23, S19). When the final arbitration cycle is completed, processing such as supplying the cell corresponding to the cell header to the corresponding input register 41n is performed (step S24).

On the other hand, if the win report WIN is not returned, the process ends when the final arbitration cycle ends (step S21).

As described above, each input buffer 30n
Has a function of setting a congestion display flag BAF as necessary, a function of continuously outputting a cell header at the time of receiving a win report WIN, and a function of outputting a next cell header when receiving a loss report DEF. Have.

Next, the function of the decoder 52n will be described with reference to FIGS. 4, 5, 6, and 7.

FIG. 4 is a diagram showing an example of the structure of cells stored in the input buffer 50n. The cell shown is 56
The first three bytes are allocated to a switching tag, and the remaining 53 bytes are allocated to an information field.

As shown in FIG. 5, the first byte of the switching tag is supplied to the decoder 52n as an arbitration cell header. In this cell header, a cell valid flag CEF, a broadcast cell display flag BC, outgoing line number designation data S3 to S0, and a congestion display flag BAF are inserted. Note that R is a spare bit.

The cell valid flag CEF is a flag indicating whether or not the cell is a valid cell. Broadcast cell display flag BC
Is a flag indicating whether or not the cell is a broadcast cell. The outgoing line number designation data S3 to S0 correspond to the outgoing line 22 to which a cell is to be output.
This is data for designating the number n of n. The buffer congestion display flag BAF is a flag indicating whether or not the input buffer 21n is in a congestion state.

The outgoing line number designation data S3 to S0 are represented by, for example, 4 bits, and can correspond to a 16 × 16 switch. As in the present example, in a 4 × 4 switch, the lower 2 bits S
1 and S0 are not used, and only the upper two bits S3 and S2 are used.

The cell valid flag CEF, the broadcast cell display flag BC, and the outgoing line number designation data S3 to S0 are
It is inserted in advance at the cell source. On the other hand, the congestion display flag BAF is inserted by the input buffer 30n as described above.

FIG. 6 is a flowchart showing a cell header decoding operation of each decoder 52n per exchange cycle.

In the cell header decoding operation, first, a process is performed to determine whether or not a cell is a valid cell based on the cell valid flag CEF (step S31).
If the cell is a valid cell, a process of determining whether or not the cell is a broadcast cell is performed based on the broadcast cell display flag BC (step S32).

In the case of a non-broadcast cell, a process of decoding the outgoing line number #n is performed based on the outgoing line number designation data S0 to S3 (step S33). After this decryption,
Based on the congestion display flag BAF, a process is performed to determine whether or not the corresponding input buffer 30n is in a congestion state (step S34).

If it is in the congestion state, the output request REQ and the congestion report OC are transmitted to the output request buffer arbitration circuit 53n corresponding to the output line number #n decoded in step S33 (step S35). ). In contrast,
If it is not in the congestion state, a process of transmitting only the output request REQ is performed (step S36).

If it is determined in step S32 that the cell is a broadcast cell, a process of transmitting an output request REQ to the broadcast request buffer arbitration circuit 53BC is performed (step S39).
S40) . Also in this case, processing for transmitting the congestion report OC is performed as necessary.

The above processing is continued until the final arbitration cycle ends (step S40 ). Then, when the final arbitration cycle ends, the processing ends.

If it is determined in step S31 that the cell is invalid, the processes in steps S40 and S31 are repeated. As a result, the arrival of a valid cell is awaited. However, in this case, since no cells are stored in the input buffer 30n, there is no possibility that valid cells will be sent.

As described above, each decoder 52 n
It has a function of decoding the destination and the congestion state of the corresponding input buffer 30n and transmitting the decoding result to the competing cell arbitration unit 53.

FIG. 7 is a flowchart showing the arbitration result decoding operation of each decoder 52n per exchange cycle.

In this arbitration result decoding operation, first,
A process is performed to determine whether or not a broadcast priority request BCSEL has been returned from the broadcast request buffer arbitration circuit 53BC (step S41).

Here, the broadcast priority request BCSEL is an output request buffer arbitration circuit 5 for each decoder 52n.
Broadcast request buffer arbitration circuit 5 from 3n arbitration result ACK
This is a request for giving priority to the decoding of the acknowledgment result ACK of 3BC. In other words, the request is to give priority to decoding of the arbitration result ACK of the broadcast cell over the arbitration result ACK of the non-broadcast cell.

This is because the broadcast cell is connected to all outgoing lines 220 to
This is because, since the broadcast cell and the non-broadcast cell compete for each other, the arbitration result ACK of the non-broadcast cell becomes meaningless.

When the broadcast priority request BCSEL is returned, even if the decoding result of the cell header is transmitted to the outgoing request buffer arbitration circuit 53n, the process of decoding the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC is performed. This is performed (step S42). When the decryption is completed, a process of returning the decryption result RPT to the corresponding input buffer 30n is performed (step S43).

In this case, if the corresponding input buffer 30n is the broadcast request buffer and the arbitration has been won, a win report WIN is returned. On the other hand, if the user loses in the arbitration or if the corresponding input buffer 30n is not the broadcast request buffer, a loss report DEF is returned.

The decryption and reply processing (steps S42 and S42)
Step 43) is repeated until the final arbitration cycle ends.

On the other hand, if the broadcast priority request BCSEL is not returned, the process of decoding the arbitration result ACK of the output request buffer arbitration circuit 53n that has transmitted the decoding result of the cell header and the process of transmitting the decoding result RPT are performed. This is performed (steps S45 and S46). This process is continued until the final arbitration cycle is completed (step S4).
7). However, if there is no outgoing request buffer 53n that has transmitted the decoding result of the cell header because the cell is an invalid cell, a process of returning a loss report DEF is performed.

As described above, when there is a broadcast cell, the decoder 52n decodes the arbitration result ACK of the broadcast cell,
If there is no broadcast cell, the arbitration result ACK of the non-broadcast cell is decrypted.

Next, the arbitration operation of the outgoing request buffer arbitration circuit 53n per exchange cycle will be described with reference to FIGS.

The outgoing line request buffer arbitration circuit 53n
The arbitration of the outgoing request buffer is performed based on the priority P determined for each input buffer 30n in advance. In this case, the priority P is cyclically changed in the switching cycle of the switching network 40. This is in order to equally provide all input buffers 300 to 303 with cell output opportunities.

FIG. 8 is a diagram showing an example of the change of the priority P. In the N × N switch, there are n priority levels P set for each input buffer 30n. Therefore,
In a 4 × 4 switch, there are four switches. In FIG. 8, this priority P is represented by 0, 1, 2, and 3. Here, 0 indicates the highest priority P, and 3 indicates the lowest priority P.

The priority P set for each input buffer 3n in a certain exchange cycle is used in a plurality of arbitrations performed in this exchange cycle. For example, J-1st (J =
2, 3,...), The input buffer 300
The priority levels P to # 303 are 0, 1, 2, and 3, respectively. This priority P is used in a plurality of arbitrations performed in the J-1st exchange cycle.

FIG. 9 is a flowchart showing the arbitration operation of the outgoing request buffer arbitration circuit 53n per exchange cycle.

In this arbitration operation, first, processing is performed to determine whether or not there is an outgoing request buffer (step S51). This determination is made by monitoring whether the output request REQ has been sent.

If there is no outgoing request buffer, all the decoders 520 to -5 are output until the final arbitration cycle is completed.
The process of returning the losing report DEF to 23 is performed (steps S52, S65, S51).

If there is an outgoing request buffer, a process is performed to determine whether there is one outgoing request buffer. (Step S53). If there is only one outgoing line request buffer, a process of returning a win report WIN to this outgoing line request buffer and returning a loss report DEF to the other buffers is performed (steps S54 and S55).

This processing is continued until the final arbitration cycle ends (step S56). Thus, once the outgoing request buffer is determined, the arbitration result is not changed even if there is an outgoing request buffer with a higher priority P thereafter. This is because the input buffer 30n that has received the win report WIN once, and then loses the report DEF
This is to prevent receiving.

When the final arbitration cycle is completed, a process for changing the priority P is performed (step S57). Thus, in this case, the process ends.

If it is determined in step S53 that there is not one outgoing line request buffer, a process is performed to determine whether or not there is a congested buffer (step S5).
8). This is done by monitoring whether a congestion report OC has been sent.

When there is a congestion buffer, the buffer having the highest priority P among the congestion buffers wins the report WIN.
Is returned, and a loss report DEF is returned to other buffers (including buffers other than the congestion buffer) (steps S59 and S60).

This process is continued until the final arbitration cycle ends for the same reason as above (step S6).
1). When the final arbitration cycle ends, the priority P is changed, and the process ends (step S57).

On the other hand, if there is no congestion buffer, a process of returning the win report WIN to the buffer having the highest priority P among the outgoing line request buffers is performed (step S6).
2). Otherwise, it is the same as when there is a congestion buffer (steps S63, S64, S57).

In both cases of steps S59 and S62, once the outgoing request buffer is determined, even if there is an outgoing request buffer having a higher priority P, the arbitration result is not changed.

If it is determined in step S52 that the final arbitration cycle has ended, only the priority P is changed, and the process ends (step S57).

As described above, when there is a congestion buffer, each outgoing line request buffer arbitration circuit 53n returns the win WIN to the buffer having the highest priority P among the congestion buffers, and returns the congestion buffer. If there is no, the win report WIN is returned to the buffer with the highest priority P among the outgoing request buffers. When the final arbitration cycle is completed, the priority P is changed.

Next, the arbitration operation of the broadcast request buffer arbitration circuit 53BC will be described with reference to FIG.

The arbitration operation is performed only in the first arbitration cycle, and when there is a broadcast request buffer, a process of transmitting a broadcast priority request BCSEL to all decoders 520 to 523 is performed. This is almost the same as the arbitration operation of the line request buffer arbitration circuit 53n.

That is, also in this arbitration operation, first, processing for determining whether or not there is a broadcast request buffer is performed (step S71). This determination is based on the output request RE.
This is done by monitoring whether Q has been sent.

When the output request REQ is sent, the broadcast priority request BCSE is sent to all the decoders 520 to 523.
A process of returning L is performed (step S72). Thus, in each decoder 52n, as described above, regardless of whether or not the arbitration circuit to which the decoder 52n has transmitted the output request REQ is the broadcast request buffer arbitration circuit 53BC, the decoding of the arbitration result of the arbitration circuit 53BC is performed. Is made.

When this process is completed, a predetermined arbitration process is performed according to whether or not there is one broadcast request buffer and whether or not there is a congestion buffer, similarly to the arbitration operation of the outgoing line request buffer (step S73). To S83). When this process ends, the priority P is changed, and the process ends (step S84).

On the other hand, if it is determined in step S71 that there is no broadcast request buffer, a process of returning a loss report DEF to all the decoders 520 to 523 is performed until the final arbitration cycle is completed (step S71). Step S
85, 86). Then, when the final arbitration cycle ends, the priority P is changed, and the processing ends (step S).
84).

The above is the configuration of one embodiment. Next, the operation of the above configuration will be described.

First, for reference, a simple description will be given of the switching operation by the switching network.

Cells input from each input line 21n are sequentially stored in the corresponding input buffer 30n. The cells are read out one by one in each switching cycle based on the arbitration result of the negotiation network 50, and the corresponding input register 41 is read out.
is converted to a timing that can be processed by n.

The cells held in each input register 41n are supplied to the switch section 42 and exchanged based on the destination information (outgoing line number designation data S3 to S0, broadcast cell display flag BC). The exchanged cell is output through the output register 43n corresponding to the destination.

If the cell is a non-broadcast cell, the cell is output through the output register 43n corresponding to the outgoing line 22n specified by the outgoing line number specifying data S3 to S0. On the other hand, in the case of a broadcast cell, all output registers 250 to
At 253, the cell is transmitted.

The cells that have passed through each output register 25n are:
Output to the corresponding outgoing line 22n. At this time, if there is a cell having a wrong destination, the wrong routing detection circuit 45 detects the cell.

The switching operation by the switching network 40 has been described above. Next, the arbitration operation performed by the negotiation network 50, which is a feature of the present invention, will be described with a specific example.

(1) First, a case where only non-broadcast cells are stored at the head of each input buffer 30n and no broadcast cells are stored will be described.

Now, as shown in FIG. 11, the priority P of each input buffer 30n is from 303 to 302 in descending order of priority.
It is assumed that the setting is made such that → 301 → 300. It is also assumed that, of the input buffers 30n, only the input buffers 303 and 302 are in a congested state. Further, the first cells of the input buffers 303, 302 and 301 all require the outgoing line 223 (outgoing line number # 3),
It is assumed that the head cell of the input buffer 300 requests the outgoing line 222 (outgoing line number # 2).

In this case, the output request REQ is transmitted to the decoder 5
23, 522, 521 to the outgoing request buffer arbitration circuit 5
33, and from the decoder 520 to the outgoing request buffer arbitration circuit 532. The congestion report OC is supplied from the decoders 523 and 522 to the outgoing request buffer arbitration circuit 533.

Thus, the outgoing line request buffer arbitration circuit 5
At 33, any one of the outgoing request buffers 303, 302 and 301 is selected. In the present example, 30 out of the outgoing line request buffers 303, 302, 301
Reference numeral 3,302 denotes a congestion buffer.
Since the priority P of the buffer 303 is higher among 03 and 302, this buffer 303 is selected.

Thus, in this case, the decoder 523
Is returned, and the decoders 522 and 52
A loss report DEF is returned to 1,520.

In the outgoing line request buffer arbitration circuit 522, since there is only one outgoing line request buffer, the input buffer 300 which is the outgoing line request buffer is selected. Thus, in this case, the report WI
N is returned, and a loss report DEF is returned to the decoders 523, 522, and 521.

Further, the output line request buffer arbitration circuit 53
At 1,530, since there is no outgoing line request buffer, a process of returning a loss report DEF to all the decoders 520 to 523 is performed. Similarly, the broadcast request buffer arbitration circuit 5
In 3BC, since there is no broadcast request buffer, a process of returning a loss report DEF to all decoders 520 to 523 is performed.

In FIG. 11, the return of the loss report DEF is shown only to the decoder 52n that has transmitted the output request REQ. This is the same in the following drawings.

Since the decoders 523, 522, and 521 have sent the output request REQ to the outgoing line request buffer arbitration circuit 533, they decode the arbitration result ACK of this arbitration circuit 533,
This decryption result RPT is stored in the corresponding input buffer 303,3.
02, 301. Thereby, the input buffer 3
03 receives the win report WIN and receives input buffers 302 and 3
01 receives the loss report DEF.

Further, since the decoder 520 has sent the output request REQ to the outgoing line request buffer arbitration circuit 532, it decodes the arbitration result ACK of this arbitration circuit 532 and returns it to the corresponding input buffer 300. Thus, the input buffer 300 receives the win report WIN.

In the next arbitration cycle, as shown in FIG. 12, the input buffers 303, 30 having received the win report WIN.
From 0, the header of the first cell is read again. On the other hand, the input buffers 302 and 3 receiving the loss report DEF
From 01, the header of the second cell is read.

Now, the second cells of the input buffers 302 and 301 are output lines 222 (output number # 2) and 22 respectively.
1 (outgoing line number # 1).

In this case, the winning report WIN is returned to the input buffer 301 since there is no conflicting buffer for the outgoing line 221.

On the other hand, the input buffers 302 and 300 compete for the outgoing line 222. In this case, since the input buffer 302 is in a congested state, the buffer 302 is normally selected.

However, the input buffer 300 is determined as an outgoing request buffer for the outgoing line 222 in the first arbitration. Therefore, in this case, the input buffer 300
, A win report WIN is returned, and to the input buffer 302, a loss report DEF is returned.

Since the buffer 303 has been determined as an outgoing request buffer in the first arbitration, a win report WIN is returned to the input buffer 303 again.

In the next arbitration cycle, in the first arbitration, the input buffers 303 and 300 that have received the win report WIN.
, The header of the first cell is read, and the second cell is read from the input buffer 301 that has received the win report WIN in the second arbitration. In contrast,
Input buffer 302 not receiving the win report WIN
, The header of the third cell is read.

This cell is connected to outgoing line 2 as shown in FIG.
20 (outgoing line number # 0), a winning report WIN is returned from the outgoing line request buffer arbitration circuit 300 to the input buffer 502. On the other hand, if the request is for the outgoing line 22n other than the outgoing line 220, the loss report DE
F is returned.

Hereinafter, similarly, the above-described operation is repeated until the final arbitration cycle is completed.

When the final arbitration cycle is completed, in the first arbitration, the input buffer 30 receiving the win report WIN
From 3,300, the head cell is read and supplied to the corresponding input registers 413, 410, respectively. Thereafter, the first cell is erased.

The second cell is read from the input buffer 301 which has received the win report WIN in the second arbitration, and is supplied to the corresponding input register 411.
Thereafter, the second cell is erased.

Further, when the win report WIN is received from the input buffer 302, the cell at that time is read and erased. The read cell is stored in the input register 412.
Supplied to On the other hand, until the end, win report WIN
If no cell is received, the cell is read out and not erased.

(2) Next, the operation when a broadcast cell is included in the head cell will be described.

Now, as shown in FIG.
It is assumed that a non-broadcast cell is stored at the head of 03, and a broadcast cell is stored at the head of the input buffers 302, 301, and 300.

Note that the priority P and the congestion state are the same as in FIG. In addition, loss report DEF
, The decoder 52 that sent the output request REQ
Only those for n are shown.

In this case, the output request REQ is transmitted to the decoder 5
23 to the outgoing line request buffer arbitration circuit 533 and the decoders 522, 521, 520 to the broadcast request buffer arbitration circuit 53BC.

The congestion report OC is supplied from the decoder 523 to the outgoing request buffer arbitration circuit 533, and the decoder 522 sends the broadcast request buffer arbitration circuit 53.
It is supplied to BC.

As a result, the output request buffer arbitration circuit 5
33, a win report WIN is returned to the decoder 523, and a loss report DE is sent to the decoders 522, 521, and 520.
F is returned. This state is maintained until the last arbitration cycle ends.

A broadcast request buffer arbitration circuit 53BC
Returns a win report WIN to the decoder 522,
A loss report DEF is returned to the decoders 523, 521, and 520. This state is maintained until the last arbitration cycle ends.

Further, the outgoing line request buffer arbitration circuit 53
From 2,531,530, all decoders 520-520
A loss report DEF is returned to 523.

At this time, all decoders 520 to 523 are output from broadcast request buffer arbitration circuit 53BC.
Is supplied with a broadcast priority request BCSEL.

As a result, the decoders 522, 521, 5
At 20, the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC is decoded until the final arbitration cycle ends.

Similarly, in the decoder 523, although the output request REQ has been sent to the outgoing line request buffer arbitration circuit 533, the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC is maintained until the final arbitration cycle is completed. Decryption is made.

Thus, the input buffer 302 receives the win report WIN until the last arbitration cycle ends, and the other input buffers 303, 301, and 300 receive the loss report DEF until the last arbitration cycle ends. receive. As a result, in the next exchange cycle, the broadcast cells read from the head of the input buffer 302 are exchanged.

(3) Finally, all input buffers 30
The operation in the case where no cells are stored in 0 to 303 will be described.

In this case, since no output request REQ is output, each input buffer 30n receives the loss report DEF in every arbitration cycle. Thus, no cell is read or erased in any of the input buffers 30n.

The arbitration operation of the negotiation network 50 has been described above.
This arbitration operation can be equivalently represented as a flowchart in FIG.

That is, this arbitration operation is divided depending on whether it is the first arbitration (step S81). If it is the first arbitration, it is determined whether there is an input buffer 30n in which valid cells are stored (step S82).

Input buffer 3 in which valid cells are stored
If there is no 0n, the arbitration operation ends substantially. In this case, a loss report DEF is returned to all the input buffers 300 to 303.

On the other hand, if there is at least one input buffer 30n in which valid cells are stored, it is determined whether or not a broadcast cell is included in the input buffer 30n (step S83). If a broadcast cell is included, a broadcast cell arbitration process is performed (step S84). Thereby, in this case, the arbitration operation is substantially ended, and the arbitration of the competing cell is performed according to the arbitration result of the broadcast cell.

On the other hand, if no broadcast cell is included, non-broadcast cell arbitration processing is performed for each outgoing line 22n (step S85). This arbitration is performed for each arbitration cycle.

In this arbitration, a non-broadcast cell is determined independently for each outgoing line 22n (step S86).
For the outgoing line 22n for which the non-broadcast cell has been determined, the arbitration process is substantially ended at that time. On the other hand, the arbitration process is continued for the outgoing line 22n for which the non-broadcast cell is not determined until the final arbitration cycle ends (step S87).

The above is the configuration and operation of one embodiment.

In the above description, the decoder 52
n, the functions of the outgoing line request buffer arbitration circuit 53n and the broadcast request buffer arbitration circuit 53BC have been described using flowcharts.

Therefore, these circuits may be realized by either hardware or software as long as they have the functions shown in the above-mentioned flowchart.

However, an ATM exchange usually requires high speed. Therefore, when implementing these circuits, it is preferable to implement them by hardware.

FIGS. 16 and 17 are block diagrams showing an example of a specific configuration when these circuits are realized by hardware.

First, the decoder 5 will be described with reference to FIG.
The 2n hardware configuration will be described. As illustrated, the decoder 52n includes a CEF decoder 1A, an SIU decoder 2A, a BC decoder 3A, a PRI decoder 4A,
It has an ACK decoder 5A.

Here, CEF decoder 1A determines whether or not the cell is a valid cell based on cell valid flag CEF. This determination result is used for controlling the decoders 2A, 3A, and 4A. That is, the decoders 2A, 3A, 4A
Operates only when the cell is determined to be a valid cell, and does not operate when the cell is determined to be an invalid cell.

SIU decoder 2A decodes outgoing line number #n based on outgoing line number designation data S3 to S0. When the output line number n is determined by the decoding, the output request REQ is transmitted from the SIU decoder 2A to the output line request buffer arbitration circuit 53n corresponding to the output line number #n.

The BC decoder 3A determines whether the cell is a broadcast cell based on the broadcast cell display flag BC. If it is determined that the cell is a broadcast cell, an output request REQ is transmitted from the decoder 3A to the broadcast request buffer arbitration circuit 53BC.

The PRI decoder 4A determines whether or not the input buffer 30n is in a congestion state based on the buffer congestion display flag BAF. If it is determined that the congestion state is present, the arbitration circuit 53n or 53BC to which the output request REQ is transmitted is supplied to the decoder 4A.
Sends a congestion report OC.

The ACK decoder 5A has its own decoder 52n.
Arbitration circuit 53n or 53 that has sent the output request REQ
The arbitration result ACK from the BC is decrypted. This decryption result R
PT is supplied to the corresponding input buffer 30n.

When receiving the broadcast priority request BCSEL, the ACK decoder 5A decodes the arbitration result ACK of the broadcast request buffer arbitration circuit 53BC regardless of the destination of the output request REQ. This state is maintained until the last arbitration cycle ends.

In FIG. 16, REQ, OC, A
The codes attached to the CK in parentheses indicate the transmission source and the transmission destination. In this case, the code on the left side in parentheses indicates the transmission source, and the code on the right side indicates the transmission destination.

For example, REQ (n, 3) is
The output request supplied from the 2n SIU decoder 2A to the output request buffer arbitration circuit 533 is shown. This is the same in FIG. 16 described later.

The above is an example of the hardware configuration of the decoder 52n. Next, the hardware configuration of the arbitration circuits 53n and 53BC will be described with reference to FIG. First, the hardware configuration of the output request buffer arbitration circuit 53n will be described.

As shown, the arbitration circuit 53n includes a priority setting circuit 1B, an output request buffer selection circuit 2B,
Congestion buffer selection circuit 3B and winning buffer selection circuit 4
B and an arbitration result output circuit 5B.

Here, the priority setting circuit 1B rearranges the decoding result of each decoder 52n based on the priority P predetermined for each input buffer 30n. This priority P
Is cyclically changed in the cell exchange cycle based on the control signal ROT supplied from the control unit 44.

Out of the decoding results rearranged based on the priority P, the output request REQ is supplied to the output request buffer selection circuit 2B, and the congestion report OC is supplied to the congestion buffer selection circuit 3B.

When there is no output request REQ at the input, the output request buffer selection circuit 2B outputs a loss report DEF to all four output terminals. On the other hand, when one output request REQ is included, a win report WIN is output to an output terminal corresponding to the output request REQ, and a loss report DEF is output to the other three output terminals.

When a plurality of output requests REQ are included, the winning report W is sent to the output terminal corresponding to the output request REQ having the highest priority P among the plurality of output requests REQ.
IN, and a loss report DEF is output to the other three output terminals.

Similarly, when no congestion report OC is included in the input, the congestion buffer selection circuit 3B outputs a loss report DEF to all four output terminals. On the other hand, when one congestion report OC is included, a win report WIN is output to an output terminal corresponding to the congestion report OC, and a loss report DEF is output to the other three output terminals.

When a plurality of congestion report OCs are included, a win report WIN is output to the output terminal corresponding to the congestion report OC having the highest priority P among the plurality of congestion report OCs. At the output terminal, lose report DE
Output F.

When the win report WIN is not supplied from the output request buffer selection circuit 2B and the congestion buffer selection circuit 3B, the win buffer selection circuit 4B outputs a loss report DEF to four output terminals.

On the other hand, output request buffer selecting circuit 2
If the win report WIN is supplied only from B, the win report WIN is output to the output terminal corresponding to the win report WIN, and the loss report DEF is output to the other three output terminals.
Is output.

On the other hand, when the win report WIN is also supplied from the congestion buffer selection circuit 3B, the win report WIN from the congestion buffer selection circuit 3B is applied regardless of the win report WIN from the output request buffer selection circuit 2B. A win report WIN is output to the corresponding output terminal, and a loss report DEF is output to the other three output terminals.

This control is based on a control signal BAFS indicating whether or not the congestion report OC is included in the decoding result of the decoder 52n.
This is done by EL. This control signal BAFSEL is generated by the priority setting circuit 1B.

If the winning report WIN is not supplied from the winning buffer selecting circuit 4B, the arbitration result output circuit 5B
A loss report DEF is output to four output terminals. On the other hand, when the win report WIN is supplied, the win report WIN is output to an output terminal corresponding to the win report WIN,
A loss report DEF is output to the other three output terminals.

In this case, the arbitration result output circuit 5B rearranges the input and outputs the rearranged input to the priority setting circuit 1B. Thus, even if the priority P is changed,
Arbitration result ACK without complicating hardware
Can be reported.

In addition, the arbitration result output circuit 5B first
When the win report WIN is output, the output state at that time is held until the final arbitration cycle ends. This is to prevent the input buffer 30n that has once received the win report WIN from subsequently receiving the loss report DEF, as described above.

Thus, once the winning report WIN is output, the arbitration result is not changed even if an outgoing request buffer having a higher priority P is selected thereafter.

The above is the output request buffer arbitration circuit 53n.
It is a structure of. Next, the broadcast request buffer arbitration circuit 53B
The configuration of C will be described.

The configuration of the broadcast request buffer arbitration circuit 53BC is substantially the same as the configuration of the outgoing request buffer arbitration circuit 53n.

The difference is that the arbitration result output circuit 5B
At the end of the first arbitration cycle,
The point is that the output state is maintained regardless of whether or not IN is output. This is because, as described above, arbitration of a broadcast cell is performed only in the first arbitration cycle.

Next, the winning buffer selection circuit 4B outputs a broadcast priority request BCSEL when there is a broadcast cell in the first arbitration cycle. This is for giving priority to arbitration of broadcast cells as described above.

The above is the description of the decoder 52n and the arbitration circuit 53.
It is an example of a specific hardware configuration of n, 53BC.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, the priority P is set to each input buffer 30n, and at the same time, the input buffer 30n in the congested state is detected, and the buffer having the highest priority P among the congested buffers is set as the winning buffer. Since the selection is made, it is possible to reduce cell discarding due to the overflow of the input buffer 30n.

(2) Since the priority P of each input buffer 30n is cyclically changed in the exchange cycle, a read opportunity can be equally given to each input buffer 30n. Thereby, the same input buffer 30
n can be kept from losing.

(3) Further, when a broadcast cell and a non-broadcast cell compete with each other, the broadcast cell is preferentially won, so that the broadcast cell can be kept from losing.

(4) Since the arbitration of the broadcast cell is performed only in the first arbitration cycle, even if a broadcast cell appears in the middle arbitration cycle, the arbitration result of the non-broadcast cell up to that point is wasted. Can not be.

(5) Further, when the negotiation network 50 is configured by hardware, it can be configured by the decoder 52n and the like, so that a hardware configuration that does not burden the device can be adopted.

That is, conventionally, as shown in FIG. 2, since the root network 13 is constituted by using binary elements, a high-speed operation is required for the circuit operation, and a device constituting the circuit can operate at a high speed. There was a problem that was required.

On the other hand, in this embodiment, such a problem does not occur because the Rooting Network 50 can be constituted by using a decoder which can operate at a lower speed.

(6) When the arbitration circuits 53n and 53BC are configured by hardware, the output stage is provided with the arbitration result output circuit 5B that performs reverse rearrangement with respect to the priority setting circuit 1B. In addition, the priority P can be changed without complicating the hardware.

As described above, one embodiment of the present invention has been described in detail, but the present invention is not limited to the above-described embodiment.

(1) For example, in the above embodiment, by holding the output states of the arbitration circuits 53n and 53BC, the input buffer 30n that has once received the win report WIN
Has described the case of preventing the loss report DEF from being received later. However, in the present invention, for example, the decoder 5
The above function may be obtained by holding the decoding state of the arbitration result ACK in 2n.

(2) In the above embodiment, the arbitration result A
After CK is determined, the input buffer 30n and the decoder 5
2n, the case where the arbitration circuits 53n and 53BC are operated has been described. However, in the present invention, after the arbitration results ACK are determined, they may not be operated.

(3) Further, in the above embodiment, the priority P
Has been described in the case where is changed cyclically. However, according to the present invention, when cells are accumulated in one specific input buffer 30n, the input buffer 30n may always be given a high priority P and the priority P may not be changed.

(4) In the above embodiment, the case where the present invention is applied to arbitration of a cell which is a kind of packet has been described. However, the present invention can be applied to general arbitration of packets.

(5) In addition, it goes without saying that the present invention can be variously modified without departing from the scope of the invention.

[0197]

As described above, according to the present invention,
It is possible to provide a competitive packet arbitration device capable of reducing discarding of packets due to overflow of an input buffer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional contention packet arbitration device.

FIG. 3 is a flowchart showing an operation of the input buffer 30n.

FIG. 4 is a diagram showing a structure of a cell.

FIG. 5 is a diagram showing a structure of a cell header.

FIG. 6 is a flowchart showing a cell header decoding operation of the decoder 52n.

FIG. 7 is a flowchart showing an arbitration result decoding operation of the decoder 52n.

FIG. 8 is a diagram showing a change of a priority P;

FIG. 9 is a flowchart showing the operation of the output request buffer arbitration circuit 53n.

FIG. 10 is a flowchart showing an operation of a broadcast request buffer arbitration circuit 53BC.

FIG. 11 is a diagram illustrating an example of an arbitration operation of a non-broadcast cell.

FIG. 12 is a diagram illustrating an example of an arbitration operation of a non-broadcast cell.

FIG. 13 is a diagram illustrating an example of an arbitration operation of a non-broadcast cell.

FIG. 14 is a diagram illustrating an example of an arbitration operation of a broadcast cell.

FIG. 15 is a flowchart equivalently showing an arbitration operation of the negotiation network 50;

FIG. 16 is a block diagram illustrating an example of a specific configuration of a decoder 52n.

FIG. 17 is a block diagram illustrating an example of a specific configuration of arbitration circuits 53n and 53BC.

[Explanation of symbols]

210-213 ... incoming line, 220-223 ... outgoing line, 30 ...
Input buffer section, 300 to 303 ... input buffer, 40
... exchange network, 41 ... input register section, 410-413 ... input register, 42 ... switch section, 43 ... output register section, 430-433 ... output register, 44 ... control section, 4
5 erroneous routing detection unit, 50 negotiation network, 51 input register unit, 510 to 513 input register, 52
Decoder unit, 520 to 523 Decoder, 53 Competing cell arbitration unit, 530 to 533 Outgoing request buffer arbitration circuit, 53BC Broadcast request buffer arbitration circuit, 1A CE
F decoder, 2A SIU decoder, 3A BC decoder, 4A PRI decoder, 5A ACK decoder, 1
B: priority setting circuit, 2B: output request buffer selection circuit, 3B: congestion buffer selection circuit, 4B: winning buffer selection circuit, 5B: arbitration result output circuit.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-838 (JP, A) JP-A-2-237337 (JP, A) JP-A-1-125550 (JP, A) JP-A-2- 206257 (JP, A) JP-A-1-123550 (JP, A) JP-A-2-170746 (JP, A) JP-A-5-167605 (JP, A) JP-A-4-316241 (JP, A) JP-A-3-26129 (JP, A) JP-A-2-142240 (JP, A) JP-A-6-197128 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/56 H04L 12/28

Claims (1)

(57) [Claims] 1. A provided an input buffer for temporarily storing packets for each incoming line, prior to the exchange of packets in a competition packet arbiter for arbitrating same packet destination, to each of the input buffer, 1 Available during exchange cycle
Priorities for effective contention arbitration and exchange cycles
The priority of each input buffer is supported in conjunction with the
Priority setting means for changing to an click, output request buffer detecting means for detecting a buffer having an output request of the same destination from among the input buffers, and an output request buffer detected by the output request buffer detecting means. From inside, a congestion buffer detecting means for detecting a buffer in a congestion state, and if no congestion buffer is detected by the congestion buffer detecting means, from among the output request buffers detected by the output request buffer detecting means, When the congestion buffer is detected by the congestion buffer detecting means, the first winning buffer selecting means for selecting the buffer having the highest priority in the exchange cycle set by the priority setting means as the winning buffer; Out of the congestion buffers set by the priority setting means. A contention packet arbitration device comprising: a second winning buffer selecting means for selecting a buffer having the highest priority in the switching cycle as a winning buffer.