JPH06175956A - Scsi controller - Google Patents

Abstract

PURPOSE:To reduce a power consumption by monitoring the state of an SCSI bus, and supplying a low power source or a low frequency clock signal to an inside circuit which is not in an actual operation state. CONSTITUTION:At the time of detecting that an inside circuit 19 is not in the actual operation state, a low speed clock signal or a fixed level signal, and a decreased power supply voltage are supplied to the inside circuit, and a sleep mode can be obtained. A clock frequency-dividing circuit 12 which frequency- divides an outside clock, clock selecting circuit 13 which switches the frequency- divided clock and the outside clock by a control signal, bus free detecting circuit 14 of an SCSI bus, select/reselect detecting circuit 15 from the SCSI bus, RS flip flop circuit 17 which is driven by those detecting circuits, and voltage decreasing circuit 21 which is controlled by the flip flop circuit, are added. Thus, when an SCSI controller is not in the actual operation state, a power consumed in a controller inside circuit can be sharply reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a small computer system interface (hereinafter referred to as SCSI) which is a general purpose input / output interface for small and medium computer systems standardized by ANSI (American National Standards Institute).
SCSI controller for controlling the above protocol.

[0002]

2. Description of the Related Art An example of the configuration of a conventional SCSI system is shown in the block diagram of FIG. In the figure, 11a is SCSI
Controller, 22 is clock generator, 18 is other SCSI controller internal circuit, 19 is SCS
I bus driver / receiver circuit, 20 is SCSI bus,
The signal f is a clock signal supplied from the outside of the SCSI controller 11a, and the signal h is a clock signal used inside the SCSI controller.

As shown in the figure, in a conventional SCSI controller, an externally supplied clock signal f is input to a clock generator 22, where it is divided if necessary to perform waveform shaping and the like. The internal clock signal h was supplied to the internal circuit 18 of the SCSI controller.

The operation modes of the SCSI device will be classified into the following two types. This is because the SCSI bus 2 in the sleep mode is not involved in control and data transfer and is not actually operating, and the SCS in the active mode.
This is a state in which the I bus 20 is involved in control and data transfer and is actually operating.

In this SCSI system, the SCS
Since a plurality of SCSI devices are connected in a daisy chain to the I-bus 20 and one SCSI device may be selected or reselected by another SCSI device even when the SCSI device is in the sleep mode, the SCS is always performed.
The state of the I bus 20 must be monitored. Therefore, it is necessary to supply a power supply, a clock signal, and the like to the SCSI controller 11a that controls the SCSI device and always operate a block or the like that monitors the state of the SCSI bus.

This conventional SCSI controller 11a
Is consumed by supplying the internal clock signal h of the same frequency to the internal circuit 18 regardless of the sleep mode / active mode, or by determining the sleep mode by the host CPU at a higher level and dropping the frequency of the external clock signal f. Controls such as suppressing the power were being performed.

[0007]

The above-mentioned conventional SCS.
In the I controller 11a, when the internal clock signal h of the same frequency is supplied to the internal circuit 18 of the SCSI controller irrespective of the difference between the sleep mode and the active mode, unnecessary power consumption is required even in the sleep mode where power consumption is originally desired to be suppressed. There was a problem that was consumed.

Even when the host CPU or the like has a mechanism for judging the sleep mode at a higher level and dropping the frequency of the external clock signal f, the SCSI controller 11a enters the sleep mode by itself by an instruction from the host CPU or the like. At this time, the frequency of the external clock signal f can be controlled so as to immediately drop. But SCS
When the SCSI device in which the I controller 11a is incorporated is selected or reselected from another SCSI device, the SCSI controller 11a operating with a clock signal having a low frequency because it is in the sleep mode.
Has been transmitted to the host CPU or the like once, and then the host CPU must determine the sleep mode and return the frequency of the external clock signal f to a predetermined frequency. There was a problem that the time was large.

The object of the present invention is to solve these problems,
The object is to provide a SCSI controller with significantly reduced power consumption.

[0010]

According to the present invention, an SCS in which an internal circuit driven by an external clock signal is connected to a small computer system interface (SCSI) bus via a driver / receiver circuit.
In a SCSI controller for controlling the I protocol, a bus-free detection circuit that detects that the internal circuit is in a bus-free phase in which the internal circuit is not connected to the SCSI bus, and the internal circuit is selected or reselected from another circuit. A select / reselect detection circuit for detecting that the internal circuit is reset by an output signal of the select / reselect detection circuit or a bus request signal from the internal circuit and reset by an output signal of the bus free detection circuit. A flip-flop circuit that determines an actual operation state, a frequency dividing circuit that divides the external clock signal into a predetermined frequency, and a divided clock from the frequency dividing circuit and the external clock signal by an output signal of the flip-flop. A clock selection circuit for switching and supplying to the internal circuit; A step-down circuit for outputting a low voltage obtained by stepping down the power supply voltage by a certain level by the output signal of the lip-flop circuit, and if the internal circuit is not in the actual operating state, step-down with the divided low-speed clock signal or fixed level signal It is characterized in that the power supply voltage after that is supplied to save power consumption when not in the actual operation state.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an SCS in the first embodiment of the present invention.
It is a block diagram of I system. This embodiment uses SCSI
The controller 11 and the frequency dividing circuit 12 for dividing the frequency of the clock signal line f from the outside by 1/8 and outputting the signal g.
And a clock selection circuit 13 that selects the signal line f when the signal c is at the high level and outputs the internal clock signal h by selecting the signal g when the signal is at the low level, and detects that the SCSI bus 20 is in the bus free face. Then, the bus-free detection circuit 14 that keeps the signal d high for a certain period of time,
A select / reselect detection circuit 15 that raises the signal e to a high level for a certain time when it detects that the SCSI device equipped with the SCSI controller 11 is selected or reselected from another SCSI device;
When the controller 11 requests the use of the SCSI bus, it becomes a high level for a certain period of time. An OR element 16 which inputs the bus request signal a and the detection signal e and outputs the signal b, and a set input of the signal b and a reset input of the signal d An RS flip-flop circuit 17 that outputs the signal c as a Q output, a SCSI bus driver and receiver circuit 19, an internal circuit 19 of the constituent circuits of the SCSI controller 11 excluding the bus driver / receiver circuit 19, a SCSI bus 20,
SCSI controller 11 when signal c is at low level
And a step-down circuit 21 that lowers the power supply voltage supplied from the outside by a certain level (from 5 V to 3 V in this embodiment).

In order to realize a quick detection function, the bus-free detection circuit 14 and the select / reselect detection circuit 15 are always input with the high-speed clock signal f before frequency division.

Next, the operation of the SCSI controller of this embodiment will be described. FIG. 2 is a timing chart showing the operation of the SCSI controller 11 of FIG. In the figure, at the timing of t0 immediately after the reset, the signals a to
The signals e are reset to the low level, respectively, and the internal circuit 19 is supplied with the low-speed clock divided by ⅛ and the power supply voltage of 3 V to enter the sleep mode.

Next, at the timing of t1, bus-free
When it is detected that the signal is a phase signal, the signal d becomes high level for a certain period of time, but since the RS flip-flop circuit 17 is already in the reset state, the signal c is fixed at low level and the internal circuit 19 has a low-speed clock and low level. Power is supplied and remains in sleep mode.

At the timing of t2, the internal circuit 19 becomes SC
Since the use of the SI bus 20 is requested, the signals a and b are set to the high level for a certain period of time, the RS flip-flop circuit 17 is set and the signal c is changed to the high level, so that the internal circuit 19 is not divided by 1/8 at a high speed. The clock and the normal voltage of 5V are supplied to shift to the active mode. afterwards,
The SCSI controller 11 becomes an initiator, and after performing a series of processing with the target, the target performs disconnection processing at the timing of t3.
The I-bus 20 is in the bus free phase. When this is detected by the bus-free detection circuit 14, the RS flip-flop circuit 17 is reset and the internal circuit 19
Enters sleep mode.

Further, at the timing of t4, when the SCSI device equipped with the SCSI controller 11 is reselected from the target, the output signal e of the select / reselect detection circuit 15 becomes high level for a certain period of time. Circuit 17 is set and internal circuit 19 enters the active mode. After entering the sleep mode in the bus free phase at the timing of t5, the SCSI device equipped with the SCSI controller 11 is selected from another initiator at the timing of t6, and when the target becomes the target, the signal e is output. Since the output of the flip-flop circuit 17 changes to the high level for a certain period of time, the high-speed clock is switched to the normal voltage, and the internal circuit 19 enters the active mode.

In the CMOS static circuit, LS is used.
When I is configured, its power consumption is almost proportional to the clock frequency and becomes smaller as the power supply voltage becomes lower. Therefore, in the SCSI controller of this embodiment, the internal circuit 19 occupies most of the circuit. The power consumption can be reduced to 1/8 or less of the conventional value in the sleep mode.

In this embodiment, the frequency division ratio of the frequency divider circuit 12 is 1/8 and the power supply voltage after the step-down is 3 V. However, the frequency of the internal clock signal h and the power supply voltage after the step-down are determined by the internal circuit 19. Since it is possible to reduce to the lowest frequency and lowest voltage for normal operation, it is possible to further reduce the power consumption in the sleep mode by setting different values for the division ratio and the power supply voltage after step-down. it can.

FIG. 3 shows an SC according to the second embodiment of the present invention.
It is a block diagram of SI system. In the figure, when the signal c is at a low level, the block selection circuit 13a selects the signal g, outputs it as the signal h, and fixes it to the signal i. The select / reselect detection circuit 15 uses the SCSI controller 301 mounted on the SCSI. When it is detected that the device has been selected from the initiator or reselected from the target, the signal e is set to the high level for a certain period of time. The internal circuit 19 is required to supply a clock signal in the sleep mode in the internal circuits of the SCSI controller 11 except the above-mentioned circuits 11 to 18, and the internal circuit 23 is one of the constituent circuits of the SCSI controller 11. This is a circuit capable of completely stopping the clock signal in the sleep mode in the internal circuits except the circuits 11 to 18 described above.

In this embodiment, the internal circuit of the SCSI controller 11 is divided into an internal circuit 19 which needs to supply a clock signal in the sleep mode and an internal circuit 23 which does not need to supply a clock signal. In the active mode, however, the high-speed clock signal before frequency division and the normal power supply voltage before voltage reduction are supplied to both the internal circuit 19 and the internal circuit 23, and the internal circuit 19 receives the low-speed clock signal after frequency division in the sleep mode. By supplying a fixed level signal to the internal circuit 23 and the reduced power supply voltage to the internal circuit 23, the power consumption in the internal circuit in the sleep mode is further reduced as compared with the first embodiment. It has a feature that it can be done.

[0021]

As described above, the SCSI of the present invention
In the controller, a bus-free detection circuit, a select / reselect detection circuit, a clock frequency dividing circuit, a clock selection circuit, a flip-flop circuit, a step-down circuit, etc. are added to the conventional SCSI controller, and the internal circuit of the SCSI controller in the sleep mode. SC by reducing the frequency of the clock signal supplied to, or partially stopping the clock signal and lowering the power supply voltage (however, to a level where operation at low frequencies can be guaranteed).
There is an effect that the power consumed by the internal circuit of the SI controller can be significantly reduced as compared with the active mode. In particular, when a disk device or the like that is only temporarily accessed in the system is used as the SCSI device, there is a great effect in reducing power consumption.

Further, the load on the host CPU and the like can be reduced as compared with the case where the host CPU and the like judge the sleep mode at a higher level and reduce the frequency of the clock signal.
When selected or reselected from another SCSI device, there is an effect that the clock signal before frequency division can be supplied more quickly to shift to the active mode.

[Brief description of drawings]

FIG. 1 is a block diagram of a SCSI system according to a first embodiment of the present invention.

FIG. 2 is a timing chart of the SCSI controller in the embodiment of FIG.

FIG. 3 is a block diagram of a SCSI system according to a second embodiment of the present invention.

FIG. 4 is a block diagram of an example of a conventional SCSI system.

[Explanation of symbols]

 11, 11a SCSI controller 12 1/8 frequency divider circuit 13 Clock selection circuit 14 Bus free detection circuit 15 Select / reselect detection circuit 16 OR element 17 RS flip-flop circuit 18 SCSI bus driver / receiver circuit 19, 23 Internal circuit 20 SCSI bus 21 step-down circuit 22 clock generator

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location G06F 13/36 310 D 9072-5B H04L 12/40 29/00

Claims (1)

[Claims] 1. An SCS in which internal circuitry driven by an external clock signal controls a SCSI protocol connected to a small computer system interface (SCSI) bus via a driver receiver circuit.
In the I controller, the internal circuit is the SCS.
A bus-free detection circuit that detects a bus-free phase that is not connected to the I bus, a select-reselect detection circuit that detects that the internal circuit is selected or reselected from another circuit, and this select A flip-flop circuit that is set by the output signal of the reselection detection circuit or the bus request signal from the internal circuit and that is reset by the output signal of the bus free detection circuit that determines the actual operating state of the internal circuit, and the external clock signal A frequency dividing circuit for dividing the frequency to a predetermined frequency, a clock selecting circuit for switching the frequency-divided clock from the frequency dividing circuit and the external clock signal according to the output signal of the flip-flop and supplying the internal circuit, and the flip-flop. Outputs a low voltage by reducing the power supply voltage by a certain level by the output signal of the circuit. When the internal circuit is not in the actual operating state, it supplies a low-speed clock signal or a fixed level signal after frequency division and a power supply voltage after stepping down, and power consumption when not in the actual operating state. SCSI controller characterized by saving