JPH0616614B2 - Spread spectrum power line communication synchronization method and apparatus - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synchronization method and a synchronization device in spread spectrum power line communication in which a plurality of transmission / reception devices exchange information signals via a power line.

(Prior art and its problems) In the conventional synchronization method in spread spectrum communication, John Wiley Sons
Delay Locked Loops, such as those shown by RC Dixon, Sprea Spectrnm Systems, pages 210-212, are commonly used. To be Of course, this delay lock loop synchronization method works well if the transmission path is ideal. However, this delay lock loop uses the waveform characteristics of the signals received by correlation, and in the case of a system in which spread spectrum communication is performed using a commercial power line as the transmission line, the transmission line characteristics may change due to load characteristic fluctuations. Because of the drastic change in, the waveform of the signal after correlated reception also changed greatly, and there was a possibility that the synchronization was lost or an erroneous synchronization state occurred. Here, the operation of the conventional delay locked loop will be briefly described and its drawbacks will be described. A basic configuration diagram of this delay locked loop is shown in FIG. The input spread spectrum signal that has passed through the transmission line is input from the signal line 550, and the multipliers 500 and 501 multiply the product with the pseudo random sequence generated from the pseudo random sequence generator 506. Here, the pseudo random sequence of the signal line 551 and the signal line 552 is 2
It is a series with a bit shift. The output of each multiplier is 5
So-called correlated reception is performed through the low pass filters 02 and 503. Here, the output of the low-pass filter, that is, the signals of the signal line 553 and the signal line 554, which are correlation reception outputs, are as shown in FIGS. 6 (a) and 6 (b), respectively, if the transmission line is ideal. It has a nice waveform. Here, the horizontal axis of FIG. 6 indicates time, and when the input spread spectrum signal from the signal line 550 and the pseudo random sequence generation clock on the receiving side from the signal lines 551 and 552 are slightly deviated, Figure 6 (a) and (b) at the reciprocal period of the beat frequency
A periodic waveform such as is obtained on the signal lines 553 and 554. Since the signals on the signal lines 553 and 554 are subtracted by the subtractor 504, the signal on the signal line 555 has a waveform as shown in FIG. 6 (c). Therefore, for example, when the voltage controlled oscillator 505 moves so as to advance the phase when a voltage higher than the reference voltage arrives, and moves the frequency so as to delay the phase when the voltage lower than the reference voltage, The control shown by the dotted line in Fig. 6 (c) is applied, and the position of the black circle is the only stable point, and the pseudo-random sequence is synchronized. However, if the transmission line is distorted in a bad environment such as a power line, the correlation output is significantly different from the ideal state as shown in FIGS. 7 (a) and (b), and as a result, the voltage-controlled oscillator of the signal line 355 is generated. The control signal for is also as shown in FIG. 7 (c). As can be seen from FIG. 7 (c), when the control of the voltage controlled oscillator is considered as described above, there are two stable points indicated by the black and white circles in the figure. The stable point indicated by the white circle is a quasi-stable point, and it is not certain which one is stable, and there is a possibility that an erroneous synchronization state may occur. As described above, in the conventional synchronization method using the delay lock loop, it becomes impossible to secure stable synchronization in the presence of transmission line distortion. Also, when using a commercial power line as a transmission line, a signal is supplied to the commercial power line by a transformer coupling or a signal is received from the commercial power line, so the polarity of the signal changes depending on how the outlet plug is inserted, for example, by the conventional delay lock loop. In the method, there was a phenomenon that the stable point of the loop disappeared and synchronization was not applied at all. As described above, it is difficult for the conventional method to establish synchronization of spread spectrum communication under a poor transmission environment such as using a commercial power line as a transmission line.

(Object of the Invention) It is an object of the present invention to eliminate the drawbacks of the conventional method, and to provide a synchronizing method and a synchronizing device that operate stably even in a poor transmission line environment such as a commercial power line.

According to the present invention, in the synchronization method of spread spectrum power line communication, the input signal from the power line is separated into commercial power and input spread spectrum signal by the filter at the receiving side, and the separated input spectrum is used. Gain control is performed so that the signal level of the spread signal is constant, the gain-controlled spectrum confidence signal is correlated with the first pseudo-random sequence generated on the receiving side, and the correlation output is full-wave rectified. To obtain the detected correlation signal, detect the peak of the detected correlation signal while changing the phase of the reference clock signal generated independently on the receiving side to generate the clock for generating the first pseudo-random sequence, and thereafter, The detected correlation signal and the detected correlation signal are compared with an averaged correlation signal that has passed through a low-pass filter, and the detected correlation signal is the averaged correlation signal. If it is larger, the phase of the reference clock signal is changed in the same direction as the current phase change direction. If the averaged correlation signal is larger than the detected correlation signal, the phase of the reference clock signal is changed to the current phase. There is provided a method and apparatus for synchronizing spread spectrum power line communication characterized by changing the direction opposite to the direction.

(Embodiment) Here, the principle of the present invention and the embodiment will be described with reference to the signal waveforms of the respective parts in the embodiment and the drawings.

FIG. 1 is a block diagram showing an embodiment for realizing the present invention. In a receiving device in spread spectrum communication,
FIG. 3 is a block diagram of a synchronizer for extracting a clock signal and a frame synchronization signal from a received high frequency spread spectrum signal to generate a pseudo random sequence synchronized with the pseudo random sequence in the signal. In addition, FIG. 2 (a), (b),
(c) is a timing chart showing a synchronization process. However, in FIG. 2, the pseudo random sequences on the signal lines 150 and 151 are schematically shown, and t _{1 to} t ₂ and t _{3 to} t ₄ correspond to one period of the pseudo random sequence, respectively. First, the peak detection operation of the present invention will be described together with the description of the embodiments. In FIG. 1, the signal from the power line from the signal line 160 is divided into commercial power and a high frequency spread spectrum signal by the coupler 108, and the high frequency spread spectrum signal is output to the signal line 161. The signal on the signal line 161 is input to the automatic gain controller 109, becomes a signal of a certain constant level, and is output to the signal line 150. A high-frequency spread spectrum signal (FIG. 2 (a)) subjected to gain control from the signal line 150 and the pseudo-random sequence generator 1 supplied from the signal line 151.
The pseudo-random sequence signal generated in 01 (FIG. 2 (b)) is input to a multiplier 100, and multiplication is performed on the signal line 1
It is output to 52. The low-pass component of the signal on the signal line 152 is extracted by the reduction pass filter 102 and is output to the signal line 162. The signal on the signal line 162 is output to the signal line 153 through the full-wave rectifier 110. (Fig. 2
(c)) A peak is output to the signal line 153 when the phases of the two pseudo random sequences input to the multiplier 100 match due to the nature of the pseudo random sequence. Before the peak detection circuit 104 detects the peak, that is, at time t _{5 in} FIG.
Previously, the signal logic level “0” indicating that the synchronization was not achieved was output to the signal line 154, and the phase control circuit 103 of 103 was input while the logic level “0” was input from the signal line 154. Is set to delay (or advance) the phase to the signal line 156 regardless of the input from the signal line 153.
Signal for controlling the phase change circuit of 6, logic level "0"
(Or “1”) is output. 111 is an oscillator,
A clock signal having a constant frequency is output to the signal line 155.
FIGS. 3 (a) to 3 (f) are timing charts showing the operations of the components 105 to 107, and as an example, the counter 107 has a 1/3 frequency division operation (FIGS. 3 (a) and (b)), The counter of 105 is an operation of delaying the phase (logical level "0" of the signal line 156) and an operation of advancing (the signal line 156 of the signal line 156 in the case of performing the 1/3 frequency division operation (FIGS. 3C and 3D). The logic level "1") is shown. The signal of FIG. 3 (f) shows the output when the signal of the signal line 155 is directly input to the counter of 105, and it is easy to understand how the phase shift between the two is controlled as compared with the signal of the signal line 159. I chose

When the signal line 156 is at the logic level "0" in response to the control input (FIG. 3 (e)) from the signal line 156, the phase change circuit 106 has a signal on the signal line 155 and a signal line 157.
Exclusive-OR operation with the signal of
Output to 58. The signal waveform is as in the first half of FIG. 3 (c), the output obtained by dividing the signal by the counter 105 is as in the first half of FIG. 3 (d), and the signal operates as a clock. The output of the pseudo-random sequence generator 101 is
As shown in Fig. 2 (b), it becomes a pseudo-random sequence whose phase is gradually delayed. On the contrary, when the signal line 156 is at the logic level "1", an output like the latter half of FIG. 3 (c), in which a clock is added to the signal of the signal line 155, is output to the signal line 158. The output obtained by dividing the signal by the counter 105 is as shown in the latter half of FIG. 3 (d), and operates using the signal as a clock. The output of the pseudo random sequence generator 101 is a pseudo random sequence whose phase gradually advances.

Now, before the peak detection circuit 104 detects a peak, that is, when the logic level "0" is output to the signal line 154, the logic level "0" is output to the signal line 156 as described above. Therefore, the above 105 to 10
By the operation of No. 7, a pseudo-random sequence whose phase is gradually delayed (or advanced) is output to the signal line 151. At this time, the pseudo random sequence of the signal lines 150 and 151 becomes as shown in FIG.
A peak as shown in FIG. 2 is output to the signal line 153 at the speed of delaying the phase of the pseudo random sequence of 51). (FIG. 2 shows a situation where the phase of the pseudo random sequence of the signal line 151 is delayed.) In the peak detection circuit 104, as shown in FIG. 2 (c), from the signal line 153, When a peak is input, after detecting the first pulse (time t ₅ ) that exceeds the preset level 1 judgment level, wait until the predetermined time elapses, and then exceed level 1 When the peak is input, a signal logic level "1" indicating that the peak is detected on the signal line 154 is output,
At the same time, the judgment level is changed from level 1 to preset level 2. After that, the peak detection circuit 104 continues to output the logical level “1” to the signal line 154 until the signal level of the signal line 153 falls below level 2, and during this period, the signal on the signal line 154 is received because the synchronization is maintained. It can be used as a side synchronization flag. The above is the operation up to peak detection.

Next, the phase control operation will be described. Figure 3 (g) is the first
FIG. 3 is a detailed block diagram of the phase control circuit 103 in FIG.
(h) is the timing chart. The signal on the signal line 153 is input to the averaging circuit 301, and its output is output to the signal line 351. The signal on the signal line 351 and the signal on the signal line 153 are input to the 302 comparison circuit, and the signal line 3
When the signal of 51 is smaller than the signal of the signal line 153, the signal of the logic level "1" is output to the signal line 352. Conversely, when the signal of the signal line 153 is smaller than the signal of the signal line 351, the signal of the signal line 352 is output to the signal line 352. A signal of logic level "0" is output. The signal on the signal line 352 is input to the trigger circuit 303, and when the signal on the signal line 352 is at the logic level “0”, a pulse synchronized with the rising or falling of the signal on the signal line 157 is output to the signal line 353. The signal on the signal line 353 is input to the flip-flop 304 and inverts its state. The output of the 304 flip-flop is the signal line 156.
Is output to. Since the signal line 154 is input to the reset input of the flip-flop 304, the logic level “0” is output to the signal line 154 until the peak is detected by the peak detection circuit. Outputs a logic level "0" regardless of the signal on the signal line 353, and the peak detection operation described above is performed.

When the peak is detected by the peak detection circuit 104 and the hold operation is started, the signal on the signal line 154 becomes the logic level "1", so that the reset state of the flip-flop 304 is released. In FIG. 4, (a) shows signal lines 153 and 351
(b) shows the signal on the signal line 352, (c) shows the signal on the signal line 353, and (d) shows the signal on the signal line 156. When a peak is detected at time t ₆ in FIG. 2 and the phase control operation is started, the signal on the signal line 156 remains at the logic level “0”, so the pseudo random sequence generator 101 outputs pseudo random numbers. Since the phase of the sequence gradually lags, the synchronization begins to be lost.
Therefore, the level of the signal line 153 starts to drop, but the signal of the signal line 351 passes through the average value circuit of 301, and therefore starts to drop after a while. Therefore, the signal line 153
When the signal level of is below the signal level of the signal line 351,
The signal on the signal line 352 of the comparator output of 302 becomes the logical level “0”, the pulse is output from the trigger circuit of 303 to the signal line 353, the state of the flip-flop 304 is inverted, and the logical level of the signal line 156 becomes “0”. 1 ”is output (time t ₇ ).

When the signal on the signal line 156 becomes a logic level “1”, the pseudo random sequence output from the pseudo random sequence generator 101 at 101 becomes a pseudo random sequence in which the phase gradually advances due to the operation of the above-described phase change circuit. Since synchronization is achieved, the level of the signal line 153 rises, and when the level of the signal line 351 is exceeded, the output of the comparison circuit 302 becomes the logical level "1" and the pulse output to the signal line 353 is stopped. The signal level of the signal line 153 gradually rises, reaches its maximum when the synchronization is completely achieved, and thereafter, the phase further advances, so that the level decreases. Then, when the level of the signal line 153 becomes lower than the level of the signal line 351, the flip state of 304 is inverted and the logical level "0" is output to the signal line 156 by the same operation as before. Then 101
The phase of the pseudo-random sequence output from the pseudo-random sequence generator is delayed in phase. As described above, when the signal level of the signal line 153 is lowered, control is performed to delay the output phase of the pseudo random sequence 101,
It is controlled so that the synchronization phase is always maintained.

As described above, the present invention enables a stable and simple synchronization method in spread spectrum power line communication, which was not possible with the conventional method.

(Effect of the Invention) The present invention differs from the conventionally used synchronization method using a delay lock loop, in which the peak of the full-wave rectified correlation output is detected, and the clock is detected within an allowable range near the peak position. It uses the method of constantly moving the phase and is not easily affected by the distortion of the correlation output. In addition, stable peak detection is possible by applying automatic gain control independently of the synchronization section. From the above, even if a poor transmission line such as a power line is used, stable synchronization of the spread spectrum signal can be established without being out of synchronization or in an erroneous synchronization state, and the effect is very large.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment for realizing the present invention, FIGS. 2 (a), (b) and (c) are timing charts showing a synchronization process, and FIGS. 3 (a) to (g). Is a timing chart showing the operation of the phase control circuit, a configuration diagram of the phase control circuit, and FIG.
(a) to (d) are timing charts of the phase control circuit, Fig. 5 is a basic block diagram of the delay locked loop, Fig. 6 (a),
7 (b), (c) and FIGS. 7 (a), (b), (c) are diagrams showing control signal waveforms to the correlation exit of the delay locked loop and the voltage controlled oscillator. In the figure, 100 ... Multiplier, 101 ... Pseudo-random sequence generator 102 ... Low-pass filter, 103 ... Phase control circuit 104 ... Peak detection circuit, 105, 107 ... Counter 106 ... Phase change circuit, 108 …… Combiner 109 …… Automatic gain controller, 110 …… Full wave rectifier 111 …… Oscillator, 301 …… Averaging circuit 302 …… Comparison circuit, 303 …… Trigger circuit 304 …… Flip-flop, 500, 501 …… Multiplier 502, 503 ... Low-pass filter, 504 ... Subtractor, 505 ...
... Voltage controlled oscillator, 506 ... Pseudo random sequence generator, respectively.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kaoru Endo 1-8-17 Umeda, Kita-ku, Osaka-shi, Osaka Nihon Denki Home Electronics Co., Ltd. (56) References C. Dixon, translated by Satoshi Tateno and 2 others, "Latest Spread Spectrum Communication Method," 4th edition (October 25, 1988), Nihon Techno-Economic Center Co., Ltd. 220-225

Claims (2)

[Claims] 1. A synchronization system for spread spectrum power line communication, wherein an input signal from the power line is separated by a filter into commercial power and an input spread spectrum signal at a receiving side,
Gain control is performed so that the signal level of the separated input spread spectrum signal becomes constant, and the gain-controlled spread spectrum signal is correlated with the first pseudo-random sequence generated on the receiving side, and the correlation is calculated. The output is full-wave rectified to obtain a detected correlation signal, and the peak of the detected correlation signal is detected while changing the phase of the reference clock signal independently generated at the receiving side with the clock for generating the first pseudo-random sequence. Detected, after the peak is detected, the detected correlation signal and the detected correlation signal are compared with the averaged correlation signal passed through a low-pass filter, and the detected correlation signal is more than the averaged correlation signal. When it is larger, the phase of the reference clock signal is changed in the same direction as the current phase change direction, and when the averaged correlation signal is larger than the detected correlation signal, the reference clock signal is changed. Of the spread spectrum power line communication, wherein the phase and frequency of the input spectral spread signal and the first pseudo random sequence are synchronized by changing the phase of the signal in the direction opposite to the current phase change direction. Synchronization method. 2. A power line coupling means for receiving a signal from the power line and separating it into a commercial power and a high frequency input spread spectrum signal, and the level of the input spread spectrum signal to which the input spectrum signal output from the power line coupling means is inputted. Of gain control means for generating a pseudo-random sequence, multiplication means for multiplying the output of the gain control means by the output of the pseudo-random sequence generation means, and the multiplication means of the multiplication means. A low-pass filter for extracting a low-pass component of the output, a full-wave rectification means for obtaining an absolute value signal of the output of the low-pass filter, a peak detection means for detecting a peak from the output of the full-wave rectification means, Oscillation means for generating a reference clock, and a first counter for counting down the clock signal from the oscillation means,
When the output of the full-wave rectifying means, the output of the peak detecting means, and the output of the counter are input and the output of the peak detecting means indicates a state of being out of synchronization, the clock phase is delayed or advanced in one direction. A phase control signal to be controlled in synchronization with the output of the first counter, and when the output of the peak detecting means indicates a synchronized state, the output signal of the full-wave rectifying means and the time average of the output signal are calculated. The phase control signal indicating that the state of the control signal is changed and the phase control direction of the clock phase is changed from advance to delay or from delay to advance each time the difference signal with the taken average output signal becomes negative. The phase control signal generating means for outputting in synchronization with the counter output of No. 1 and the direction of phase control from the phase control signal generating means each time the clock from the first counter arrives. Phase change means for changing the phase of the reference clock by inserting or deleting a clock, and a second counter for counting down the output of the phase change means and supplying a clock to the pseudo random sequence generation means. A spread spectrum power line communication synchronizer characterized by.