JPH06164316A - Automatic equalizer - Google Patents

Abstract

PURPOSE:To provide an automatic equalizer capable of realizing stable equalization characteristics by controlling the fluctuation width of a variable multiplication coefficient corresponding to the conditions of errors. CONSTITUTION:The output of an automatic equalizing part 1 is decoded at a viterbi decoding part 3 and at the viterbi decoding part 3, a judged signal point is outputted to an output terminal 7 and at the same time, a pass metric value is outputted to a control part 2. Then, a temporary judging part 5 judges a point close to a reception point which is the output signal of the automatic equalizing part 1 as the signal point to be supplied to an error detection part 4 and at the error detection part 4, the differential signal of the reception point and the signal point is obtained to be inputted to the control part 2 and the variable multiplication coefficient of the automatic equalizing part 1 is controlled. The fluctuation of the variable multiplication coefficient by the differential signal is made larger when the pass metric value from the viterbi decoding part 4 is large and is made smaller when the pass metric value is small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer such as a transversal filter which is provided with equalization characteristics by a variable multiplication coefficient.

[0002]

2. Description of the Related Art An automatic equalizer is used to reduce distortion of a signal transmitted between a transmitter and a receiver. The basic structure is shown in FIG. In the figure, 21 is an automatic equalization unit, 22 is a control unit, 23 is a determination unit, 24 is an error detection unit, 25 is an input terminal, and 26 is an output terminal. The automatic equalization unit 21 uses a circuit having a delay characteristic such as a transversal filter or an N-bit shift register, and the variable multiplication coefficient is controlled by a control signal from the control unit 22 to determine the equalization characteristic. Therefore, the received signal from the input terminal 25 is equalized by the automatic equalization unit 21 and determined by the determination unit 23. The error detection unit 24 detects the difference between the determination result of the determination unit 23 and the output of the automatic equalization unit 21 as an error signal, and controls the control unit 22 accordingly to automatically control the equalization characteristic.

In such a conventional automatic equalizer,
Since the variable multiplication coefficient directly responds to the error signal, the variable multiplication coefficient immediately responds to an instantaneous error, and it takes a lot of time to restore the equalization characteristic or weight before the response of the instantaneous error. There was a problem to say.

Further, in the case of using the Viterbi decoding in the judging section, the identification error (error between the receiving point and the judged signal point) when the judgment result is obtained has already passed the delay time. Therefore, the variable multiplication coefficient is controlled with a time delay, and it is not possible to obtain an appropriate equalization characteristic.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and it is possible to realize stable equalization characteristics by controlling the change width of the variable multiplication coefficient according to the error condition. The purpose is to provide a chemical device.

[0006]

According to the present invention, in an automatic equalizer, an automatic equalizer, a Viterbi decoder for decoding the output of the automatic equalizer, and a temporary determination of the output of the automatic equalizer are provided. And a control unit that controls the variable multiplication coefficient of the automatic equalization unit according to the identification error of the temporary determination unit, the control unit performing the variable multiplication according to the path metric value of the Viterbi decoding unit. It is characterized by controlling the control width of the coefficient.

[0007]

According to the present invention, since the variable multiplication coefficient is controlled by the identification error of the provisional decision unit, the time delay is small, and
By controlling the control width of the variable multiplication coefficient according to the path metric value of the Viterbi decoding unit, the influence of the instantaneous error can be reduced and a stable equalization characteristic can be realized.

[0008]

1 is a block diagram of an embodiment of an automatic equalizer according to the present invention. In the figure, 1 is an automatic equalization unit, 2 is a control unit,
3 is a Viterbi decoding unit, 4 is an error detection unit, 5 is a tentative determination unit, 6
Is an input terminal, and 7 is an output terminal. The automatic equalization unit 1 is the same as the conventional example described above, and the variable multiplication coefficient is controlled by the control signal from the control unit 2 to determine the equalization characteristic. The signal equalized by the automatic equalization unit 1 is decoded by the Viterbi decoding unit 3. The Viterbi decoding unit 3 outputs the signal point identified from the minimum value of the path metric value to the output terminal 7 as the determination result, and also outputs the path metric value that is calculated and stored at the time of decoding. The path metric value is
It is the sum of the error for the optimal path from the past to the present, and is given by the integrated value of the Hamming distance and the Euclidean distance.

The tentative decision section 5 decides a point closest to the reception point, which is the output value of the automatic equalization section 1, as a signal point, and supplies this to the error detection section 4. The error detection unit 4 derives the difference between the reception point, which is the output signal of the automatic equalization unit 1, and the signal point determined by the temporary determination unit 5 as an error signal. The error signal is input to the control unit 2 and controls the variable multiplication coefficient of the automatic equalization unit 1, but the control width is controlled by the path metric value from the Viterbi decoding unit 4. That is, when the path metric value is large, the change in the variable multiplication coefficient due to the error signal is increased, and when the path metric value is small, the change in the variable multiplication coefficient due to the error signal is decreased.

As described above, since the change in updating the variable multiplication coefficient is made according to the path metric value, the convergence accuracy can be improved and the path metric value can be improved when the path metric value is large. If it is small, the convergence accuracy can be reduced. When an instantaneous error occurs, the path metric value does not increase by itself. Therefore, even if the error signal is large, the variable multiplication coefficient is not greatly changed by the small path metric value.

The control of the variable multiplication coefficient by the path metric value may be performed by multiplying the error signal by the path metric value, or by giving the change amount of the variable multiplication coefficient as a step value, the step value determined by the error signal. May be increased or decreased according to the path metric value.

FIG. 3 is a block diagram of an embodiment in which the automatic equalizer of the present invention is applied to a facsimile machine. This facsimile machine is based on CCITT Recommendation V.6. It is based on 17. In the figure, 31 is an AGC circuit, 32 is an A / D conversion unit, 33 is a feedback circuit, 34 is a demodulation unit, 35 is an automatic equalization unit, 36 is a reference signal unit, 37 and 38 are control units, and 39 is a phase correction unit. Part, 40 is a Viterbi decoding part, 41 is a tentative determination part, 42
Is an equalization error detector, 43 is a phase error detector, 44 is an input terminal, and 45 is an output terminal. The phase modulation signal is input to the input terminal 44, the gain is adjusted by the AGC circuit 31, and the digital signal is converted by the A / D converter 32. The feedback circuit 33 controls the AGC circuit 31 based on the amplitude value of the digital signal. The demodulation unit 34 uses the signal from the reference signal unit 36 to convert the digital signal to I
Discriminate between component and Q component. The discriminated output signals are subjected to signal distortion generated on the line by the automatic equalizer 35. The signal equalized by the automatic equalization unit 35 is decoded by the Viterbi decoding unit 40. The Viterbi decoding unit 40 outputs the signal point to the output terminal 45 as a determination result and stores the operation at the time of decoding. Control unit 37
Output to. A differential code of the signal output to the output terminal 45 is decoded, a descrambler is performed, and the original data string is returned.

The tentative decision section 41 decides a point near the reception point, which is an output value of the automatic equalization section 35, as a signal point. The difference between the reception point and the signal point is detected by the equalization error detection unit 42 and given to the control unit 37 to control the variable multiplication coefficient of the automatic equalization unit 35. At the same time, the control unit 37 is controlled by the path metric value from the Viterbi decoding unit 40. When the path metric value is large, the change amount of the variable multiplication coefficient due to the error signal is increased, and when the path metric value is small, , The amount of change in the variable multiplication coefficient due to the error signal is reduced.

The phase error detection unit 43 detects a phase error between the reception point in the output of the automatic equalization unit 35 and the signal point by the provisional determination unit 41, and the phase correction unit 3 via the control unit 38.
9 to compensate for phase jitter. The output of the phase error detection unit 43 is also given to the reference signal unit 36 and adjusts the phase of the reference signal.

Although the change in updating the variable multiplication coefficient is performed in the control unit 37 according to the path metric value, the phase metric is also added to the control unit 38 by adding the path metric value from the Viterbi decoding unit 40. The correction data of the correction unit may also be provided with a correction coefficient according to the path metric value. Phase compensation when an instantaneous error occurs can be performed more stably.

In the modem including the automatic equalizer described in this embodiment, two DSPs are formed on one chip, and the Viterbi decoding unit 40 and the tentative determination unit 41 are connected to the first DS.
P, and other functions such as modulation / demodulation, scrambler / descrambler, automatic equalization, etc.
It is possible to process with P.

[0018]

As is apparent from the above description, according to the present invention, when the path metric value is large, the variable multiplication coefficient is changed with a large change width to improve the convergence accuracy, and the path metric is improved. When the value is not large, there is an effect that the variable multiplication coefficient of the automatic equalizer can be optimally controlled by reducing the change width of the variable multiplication coefficient.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an automatic equalizer of the present invention.

FIG. 2 is a block diagram showing a basic configuration of a conventional automatic equalizer.

FIG. 3 is a block diagram of an embodiment in which the automatic equalizer of the present invention is applied to a facsimile machine.

[Explanation of symbols]

 1 Automatic Equalization Unit 2 Control Unit 3 Viterbi Decoding Unit 4 Error Detection Unit 5 Temporary Judgment Unit

Claims (1)

[Claims] 1. An automatic equalization unit, a Viterbi decoding unit that decodes the output of the automatic equalization unit, a temporary determination unit that temporarily determines the output of the automatic equalization unit, and an identification error of the temporary determination unit. An automatic equalizer having a control unit for controlling a variable multiplication coefficient of the automatic equalization unit, the control unit controlling a control width of the variable multiplication coefficient according to a path metric value of the Viterbi decoding unit; Chemist.