JPH08317012A - Digital demodulator - Google Patents

Abstract

PURPOSE: To improve the demodulation performance and to reduce the circuit scale by expressing a symbol position accurately in a small bit number without increasing a quantization error in A/D conversion so as to reduce respectively the quantization error and a symbol discrimination error. CONSTITUTION: A variable gain amplifier 10 provided in an intermediate frequency stage applies gain adjustment to an input reception intermediate frequency signal IFS in response to a dynamic range of A/D converters 13I, 13Q. A gain control circuit 20 provided newly applies gain adjustment to a digital complex signal quantized by the A/D converters 13I, 13Q to restore the level to a level before gain control by the variable gain amplifier 10 and the digital demodulation signal after gain adjustment is fed to a symbol discrimination device 191.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication device used in the fields of broadcasting and communication by using a digital modulation method such as a multilevel QAM (quadrature amplitude modulation) method or a QPSK (quadrature phase shift keying) method. The present invention relates to a digital demodulator used for demodulating a transmitted wireless communication signal.

[0002]

2. Description of the Related Art In recent years, in the field of wireless communication, various studies have been made on a high efficiency coding technique and a digital transmission system. Among them, the digital television broadcasting using the multi-level QAM system is being tested and studied for practical use mainly in the cable television (CATV) broadcasting system, and is considered to be a key to future digital transmission. There is.

FIG. 8 shows one of the digital demodulators 6
It is an example of a circuit configuration of a 4QAM demodulator.
In the figure, the reception intermediate frequency signal IFS output from a radio circuit (not shown) is amplitude-controlled by an intermediate frequency amplifier including a variable gain amplifier 10 and an automatic gain control circuit (AGC) 11, and then input to a quadrature detector 12. To be done. The quadrature detector 12 includes multipliers 121I and 121Q.
, The local oscillator 122, and the local oscillation signal generated from the local oscillator 122 by π / 2 phase shift to obtain the multiplier 12
Π / 2 phase shifter 123 is supplied to 1I, and quadrature detection is performed by multiplying the received intermediate frequency signal IFS by the local oscillation signal by the multipliers 121I and 121Q.

The complex signal obtained by this quadrature detection is
Analog / digital (A / D) converters 13I, 13Q
Is input to the A / D converters 13I and 13Q, is sampled in synchronization with the sampling signal given from the oscillator 14, and is converted into a digital signal.
Then, the digital complex signal is input to the complex multiplier 16 after the frequency components other than the desired band are removed by the low pass filters (LPF) 15I and 15Q.

In the complex multiplier 16, the digital complex signal is multiplied by the signal generated by the carrier phase synchronization circuit 17 and quadrature detection is again performed, whereby carrier phase synchronization is achieved. The carrier phase synchronization circuit 1
7 is a phase error detector 171 and a PLL filter 172.
And a numerically controlled oscillator (NCO) 173 and a sine / cosine converter (sin / cos) 174. Then, in the phase error detector 171, the equalizer 1 described later
8 and the output signal of the error detector 19, the phase error of the carrier is detected, and the phase error detection signal is passed through the PLL filter 172 to remove the harmonic component and remove the NCO.
Input to 173. The NCO 173 generates a frequency signal corresponding to the phase error detection signal supplied from the PLL filter 172. This frequency signal is converted by the sine / cosine converter 174 into a frequency signal of a sine waveform and a cosine waveform, and then the complex signal is generated. It is given to the multiplier 16.

The digital demodulated signal output from the complex multiplier 16 is input to the equalizer 17. This equalizer 17
Is an adaptive equalizer that detects the state of the transmission line based on the output signal of the error detector 19 and dynamically updates the internal filter coefficient. As a result, interference components such as reflection are removed. The error detector 19 has a symbol determiner 191 and a differencer 192, and calculates and outputs the difference between the position of a symbol near the input signal and the input signal. Equalizer 114
The digital demodulated signal output from is supplied to the phase error detector 171 and the error detector 19 for detecting the phase error and the error, and is also supplied to a decoding circuit (not shown).

By the way, in such a digital demodulator, the number of output bits of the A / D converters 13I and 13Q is generally smaller than the number of processing bits downstream thereof, and therefore, the A / D converter. The performance of the demodulator is influenced by reducing the quantization error of 13I and 13Q. For this reason, it is desirable that the amplitude value of the input signal to the A / D converters 13I and 13Q be as large as possible within the dynamic range. Therefore, the above-mentioned pre-stage side of the A / D converters 13I and 13Q is described above. Thus, the automatic variable gain type intermediate frequency amplifier is arranged to control the input amplitude value.

However, when this input amplitude value is controlled, the number of bits expressing the symbol position determined by the symbol determiner 191 changes. Taking a 64QAM-modulated signal as an example, in this signal, the ratio of the values of the coordinates A, B, C, and D on the Q axis of the symbol is 1: 3: 5: 7 as shown in FIG.
Distributed in the proportion of. Incidentally, the coordinates of the I axis are similarly distributed. Here, when the amplification factor of the variable gain amplifier 10 is set to an arbitrary value and amplitude control is performed, the A / D converter 13
If the outputs of I and 13Q are represented by 6 bits and have the bit arrangement as shown in FIG. 9B, the variable gain amplifier 1
When the amplification factor of 0 is increased a little more, for example, as shown in FIG.
The bit arrangement is as shown in (c). These Figure 9
Looking at the bit arrangements in (b) and FIG. 9 (c), the bit representations in both cases are the ratio of the Q-axis coordinates of the symbol arrangement: 1:
It is kept at 3: 5: 7, but in order to express this, please refer to FIG.
9B requires only 3 bits, whereas FIG. 9C requires 5 bits.

The difference in the number of representation bits is equalized by the equalizer 1.
The circuit scale after 8 is affected. In particular, the symbol determiner 191 needs to accurately determine the symbol position,
If the number of bits for expressing this symbol position increases, the circuit scale will be correspondingly increased. Furthermore, depending on the amplification factor of the variable gain amplifier 10, it may not be possible to allocate a sufficient number of bits for expressing the symbol position to the symbol determiner 191. In this case, since the symbol position is not accurately determined, the output of the error detector 19 contains an unnecessary error, which may deteriorate the performance of the demodulator.

That is, in the digital demodulator that performs demodulation using the symbol determination result as described above,
In order to reduce the circuit scale and improve the demodulation performance, it is necessary to represent the symbol position accurately and with as few bits as possible.

[0011]

However, in the above-mentioned conventional configuration, the quantization accuracy in the A / D converters 13I and 13Q is prioritized so that the amplitude value of the input signal is A / D converter 13I. , The gain of the variable gain amplifier 10 is controlled to be as large as possible within the dynamic range of 13Q,
The number of bits for expressing the quantized symbol position increases, resulting in an increase in the circuit scale of the demodulator.
Also, the number of bits required to express the symbol position cannot be assigned to the symbol determiner, which results in deterioration of the symbol position determination accuracy. On the other hand, if the amplitude value of the input signal to the A / D converters 13I and 13Q is determined in order to accurately represent the symbol position,
The quantization error in the A / D converters 13I and 13Q becomes large, or the amplitude value of the input signal is A / D converters 13I and 13Q.
There was a case where the dynamic range of Q was exceeded, which was extremely undesirable.

The present invention has been made in view of the above circumstances, and an object thereof is to accurately represent a symbol position with a small number of bits without increasing a quantization error in A / D conversion. So that A /
It is an object of the present invention to provide a digital demodulator capable of reducing the quantization error in D conversion and the symbol position determination error in symbol determination to improve demodulation performance and reducing the circuit scale.

[0013]

In order to achieve the above object, the present invention quantizes a received digital modulated wave signal by an analog / digital converting means and then performs a predetermined demodulation process to obtain a demodulated signal. In a digital demodulator that determines a symbol included in this demodulated signal by a symbol determination means according to a predetermined threshold value and uses the symbol determination result in the demodulation process, a first stage is provided before the analog / digital conversion means. Gain adjusting means is provided, and the amplitude of the signal input to the analog / digital converting means is adjusted to a preset amplitude level according to the dynamic range of the analog / digital converting means by the first gain adjusting means. And a second gain adjusting means between the analog / digital converting means and the symbol judging means. The second gain adjusting means adjusts the amplitude of the quantized signal output from the analog / digital converting means to a preset amplitude level based on the symbol determination result of the symbol determining means. It was done like this.

According to the present invention, in the second gain adjusting means, the difference between the amplitude value of the signal whose amplitude level has been adjusted by the gain adjusting means and a preset reference value is obtained and the time average thereof is obtained. The quantized signal output from the analog / digital converting means is multiplied by the obtained time average value.

Further, the gain preset so that the amplitude value of the signal output immediately after the start of the operation of the second gain adjusting means is equal to the expected amplitude convergence value of the signal output from the gain adjusting means. It is also characterized by giving the initial value of.

At this time, the initial value of the gain may be changed according to the modulation system of the received digital modulated wave signal.
Further, according to the present invention, in the second gain adjusting means, a gain adjusting magnification set to a reciprocal of the gain adjusting magnification by the first gain adjusting means is generated, and the generated gain adjusting magnification is used as the analog value. Another feature is that the quantized signal output from the / digital conversion means is multiplied.

Further, according to the present invention, when the equalizing means for performing the waveform equalizing process of the digital demodulated signal is provided between the analog / digital converting means and the symbol determining means, the second gain adjusting means is provided. In the analog / digital conversion means, the tap coefficient of the equalization means is changed based on the difference between the symbol position of the demodulated signal output from the equalization means and the symbol determination result of the symbol determination means. It is characterized in that the amplitude of the output quantized signal is adjusted.

In the second gain adjusting means, the tap of the equalizing means may be given an initial value expected as a converged value of the tap before starting the waveform equalizing process. Further, at this time, the initial value given to the tap of the equalization means by the tap coefficient initialization means may be changed according to the modulation system of the received digital modulated wave signal.

[0019]

As a result, according to the present invention, the received signal is adjusted to a preset amplitude level in the first gain adjusting means in accordance with the dynamic range of the analog / digital converting means, and then input to the analog / digital converting means. Are quantized. Therefore, the dynamic range of the analog / digital converting means can be effectively used, and the quantization error can be reduced. The signal output from the analog / digital converting means is gain-adjusted by the second gain adjusting means and then input to the symbol determining means for symbol determination. Therefore, the symbol position of the symbol determination result can be expressed with a small number of bits without error.

That is, according to the present invention, both the quantization error of analog / digital conversion and the error of the symbol determination result can be suppressed to be low, whereby the demodulation performance of the digital demodulator can be improved.
Moreover, since the number of bits of the symbol determination result can be reduced, it is possible to reduce the circuit scale of the circuit that performs processing using the symbol determination result.

Further, according to the present invention, a time average of the difference between the amplitude value of the signal whose amplitude level is adjusted by the second gain adjusting means and the preset reference value is obtained, and the obtained time average is obtained. Based on the value, the amplitude level of the quantized signal output from the analog / digital conversion means is adjusted. Therefore, even if the quantized signal changes in level, it is possible to always supply a signal having a constant amplitude level to the symbol determination means.

Further, in the second gain adjusting means, the initial value of the gain set in advance so as to be equal to the expected amplitude convergence value is given, so that the second gain adjusting means rises quickly at the start of reception. Can be converted. At this time, if the gain initial value is changed according to the modulation system of the received signal, it is possible to support a plurality of modulation systems.

Further, according to the present invention, by fixing the gain adjustment magnification of the second gain adjusting means, the structure of the second gain adjusting means can be greatly simplified. In this case, the level fluctuation of the quantized signal cannot be corrected, but it is effective when the level fluctuation of the quantized signal is small.

Further, according to the present invention, when the waveform equalizing means is provided, the amplitude level of the quantized signal is adjusted by changing the tap coefficient. For this reason, the gain of the quantized signal can be adjusted by using the existing waveform equalizing means without newly providing a gain adjusting circuit, and thus the circuit configuration can be prevented from becoming complicated and large in size and simplified. And a small circuit can be provided.

Further, if the initial value of the tap coefficient is given to the tap of the equalizing means at the start of the equalization processing operation, the equalizing means can be started up at a high speed. At that time, if the initial value of the tap coefficient is changed according to the modulation system of the received signal, it becomes possible to support a plurality of modulation systems.

[0026]

1 is a circuit block diagram showing the configuration of a digital demodulator according to an embodiment of the present invention. In the figure, the same parts as those in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

A gain control circuit 20 is arranged between the LPFs 15I and 15Q and the complex multiplier 16. The gain control circuit 20 includes multipliers 21I and 21Q and a gain adjuster 22. The gain adjuster 22 is the equalizer 18
The power value of the digital demodulated signal output from
Based on the difference between the detected power value and the reference value, the LPF
It operates so as to match the power value of the digital complex signal output by 15I and 15Q with the reference value.

FIG. 2 is a circuit block diagram showing the configuration of the gain adjuster 22. In the figure, the digital demodulated signal output from the equalizer 18 is input to the amplitude calculator 221. The amplitude calculator 221 obtains the power value by calculating the amplitude value of the input digital demodulation signal. The calculated power value is compared with a preset reference value (average amplitude value) in the differentiator 222 and supplied to the adder 223. In the adder 223, the current symbol and the symbol one symbol before are added, and the addition output is delayed by the delay device 224. That is, the error between the power of the input signal and the reference value is integrated by the circuit configured by the adder 223 and the delay device 224.

The integrated value of this error is multiplied by the coefficient k1 output from the coefficient generator 226 in the multiplier 225, and the constant C1 output from the constant generator 228 is added in the adder 227. The error integrated value obtained by multiplying and adding these coefficients is given to the multipliers 21I and 21Q as a gain adjustment signal.

The value C1 of the above constant may be C1 = 1 normally, but when the initial gain output by the gain adjuster 22 is changed, it can be set to a value commensurate with the initial gain. For example, if it is expected that the output of the LPFs 15I and 15Q will eventually be multiplied by 1.5, the value C1 of the constant is set to C1 = 1.5, so that The output can be concentrated in the vicinity of 1.5 immediately after the operation is started, and there is an advantage that the convergence time of the gain adjusting process in the gain adjuster 22 can be shortened.

By the way, the reference value (average amplitude) is set as follows. That is, it is now assumed that the symbol arrangement of the received intermediate frequency signal IFS is the arrangement of the 64QAM system and the amplitude thereof is as shown in FIG.
It is assumed to be substantially equal to the dynamic range DL of I and 13Q. In this case, since the amplitude of the symbol arrangement is almost equal to the dynamic range DL, when the symbol arrangement rotates due to the phase shift of the carrier, the transmission symbol goes out of the dynamic range of the A / D converters 13I and 13Q. As a result, accurate quantization cannot be performed.

Therefore, the gain of the variable gain amplifier 10 is controlled so that all symbols fall within the dynamic range of the A / D converters 13I and 13Q even if the symbol arrangement is rotated due to the phase shift. For example, as shown in FIG. 4B, the distance from the origin of the symbol arrangement to the furthest symbol is 2 with respect to the amplitude a of the received intermediate frequency signal IFS.
It becomes / 3.

Then, the A / D converters 13I and 13Q
When the amplitude value corresponding to the dynamic range DL of is represented by 8 bits, the quantized value of each symbol of A, B, C, and D in the symbol arrangement shown in FIGS.
5B and 5C, respectively. As is clear from the figure, the symbol arrangement shown in FIG.
As shown in (b), it can be seen that the symbol position can be completely expressed by using only 4 bits out of 8 bits. On the other hand, the symbol arrangement shown in FIG.
As shown in (c), a maximum of 7 bits out of 8 bits must be used. Further, regarding the symbols A, C, and D among the symbols in FIG. 5C, it is difficult to completely represent the symbol positions even if all the 8 bits are used, and thus there is a possibility that an error may occur in the symbol positions. There is

Therefore, the gain of the gain adjuster 22 is adjusted to increase the amplitude of the digital complex signal by, for example, 3/2 from the state shown in FIG. 5 (b). That is, the magnitude of the input signal amplitude suppressed by the gain adjustment by the variable gain amplifier 10 is restored. Then, the symbol determiner 191 will be shown in FIG.
Since the digital demodulated signal represented as shown in (b) is supplied, the determination result of the symbol determined by the symbol determiner 191 can be represented by 4 bits. That is, it is possible to accurately represent the symbol position with a small number of bits.

In the above case, the reference value used by the gain adjuster 22 is 3 / of the average amplitude in the symbol arrangement shown in FIG. 4 (b).
It is double. This average amplitude is the dynamic range DL
Can be obtained from the symbol arrangement of FIG.

With such a configuration, when reception is started, the reception intermediate frequency signal IFS is first adjusted in amplitude by the variable gain amplifier 10 and then input to the quadrature detector 12, where it is quadrature detected. A after being converted to a complex signal
It is input to the / D converters 13I and 13Q. Here, in the amplitude adjustment in the variable gain amplifier 10, the amplitude level of the reception intermediate frequency signal IFS is adjusted to the A / D converters 13I and 13Q.
To be 2/3 times the dynamic range DL of
It is controlled by the GC 11. Therefore, the complex signal is accurately quantized in the A / D converters 13I and 13Q even if the symbol arrangement is rotated due to the phase shift of the carrier.

The digital complex signals output from the A / D converters 13I and 13Q are LPFs 15I and 15Q.
After the unnecessary frequency component is removed by Q, the gain control circuit 20
Are input to the multipliers 21I and 21Q. Then, in the multipliers 21I and 21Q, the gain adjustment signal output from the gain adjuster 22 is multiplied to perform the gain adjustment of the amplitude value. This gain adjustment is controlled to multiply the amplitude of the digital complex signal by 3/2. Therefore, the amplitude level of the digital complex signal is returned to a sufficiently large amplitude level before the gain control by the variable gain amplifier 10 and the AGC 11.

Therefore, a digital demodulated signal having a sufficiently large amplitude level is input to the symbol determiner 191 of the error detector 19, which results in accurate symbol determination. In addition, each symbol after the symbol determination is represented by a relatively small number of bits, whereby the circuit of the circuit such as the phase error detector 171 and the equalizer 18 that performs processing using this symbol determination result. The scale will be reduced.

That is, in the digital demodulator of the present embodiment, the variable gain amplifier 10 provided in the intermediate frequency stage has A
Gain adjustment according to the dynamic range of the A / D converters 13I and 13Q is performed on the input reception intermediate frequency signal IFS, and new adjustment is provided for the digital complex signals quantized by the A / D converters 13I and 13Q. Gain control circuit 2
The gain is adjusted to 0 to return the amplitude level to the level before the gain control by the variable gain amplifier 10, and the digital demodulated signal after the gain adjustment is performed by the symbol determiner 19
I am going to give it to 1.

Therefore, the A / D converters 13I and 13Q
Then, even if the symbol arrangement is rotated due to the phase shift of the carrier or the like, the complex signal is converted into the A / D converter 13I,
It is quantized accurately in 13Q without distortion of the symbol arrangement. That is, quantization with a small error can be performed. In addition, the symbol determiner 191
Since the digital demodulated signal whose amplitude level has been returned to a sufficiently large value by the gain adjustment of the gain control circuit 20 is supplied, the symbol position determined by the symbol determiner 191 can be expressed with a small number of bits without error. Becomes Therefore, it is possible to obtain a symbol determination result with a small error, whereby the A / D converters 13I and 13Q can be obtained.
The demodulation performance can be improved in combination with the reduction of the quantization error in. Moreover, since the number of bits of the symbol determination result can be reduced, it is possible to reduce the scale of a circuit that performs processing using the symbol determination result, such as the phase error detector 171.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the gain adjuster 22
The reference value set to 1 is obtained by multiplying the average amplitude of the digital demodulated signal input to the gain adjuster 22 by the reciprocal of the amplification factor of the variable gain amplifier 10. However, it is not limited to the reciprocal of the amplification factor of the variable gain amplifier 10. That is,
It is not necessary to completely restore the magnitude of the input signal amplitude changed by the gain adjustment by the variable gain amplifier 10 by the gain adjustment of the gain adjuster 22. For example, when the amplitude of the received intermediate frequency signal IFS is reduced to 2/3 times by the variable gain amplifier 10, the average amplitude of the digital demodulation signal input to the gain adjuster 22 may be tripled. Good.

In short, in the variable gain amplifier 10, the amplitude of the received intermediate frequency signal IFS is converted into A / D converters 13I, 1
After being attenuated to a value according to the dynamic range of 3Q, the A / D converters 13I, 1 in the gain control circuit 20 are
It is sufficient to increase the amplitude of the symbol arrangement quantized in 3Q again so that the symbol position after the symbol determination can be accurately represented with the smallest possible number of bits.

The gain adjuster 22 can be constructed as follows. FIG. 3 shows the simplest configuration as an example. The gain adjuster 23 constantly outputs the coefficient K2 regardless of the input amplitude value of the digital demodulation signal. The value of the coefficient K2 is, for example, as shown in FIG.
In the case of the symbol arrangement shown in (a) and (b), K2 =
It is set to 3/2. At this time, the multipliers 21I and 21Q simply multiply the input signals from the LPFs 15I and 15Q by the coefficient K2 and output.

In this case, the gain adjuster 23 and the equalizer 1
Since there is no buffer between 8 and 8 for adjusting the gain of the signal, it is possible to perform gain control in the equalizer 18. By performing the gain adjustment by the equalizer 18, the gain signal aimed at by the gain adjuster 23 is changed to the symbol determiner 1
It is also possible that it is not accurately input to the synchronous demodulation circuit such as 91. However, if the influence is small, it is sufficiently possible to accommodate the gain adjusting function in the equalizer 18.

Further, when the equalizer is an adaptive equalizer that changes the coefficient according to the output of the error detector 19, the input symbol R to the error detector 19 is located in the vicinity thereof as shown in FIG. The equalizer may be configured to perform an operation such that the symbol output of the symbol determiner 191 is closer to the determination output symbol P. The algorithm of the equalizer 180 in this case may be expressed by the following equation, for example.

The _{θ t + 1 = θ t +} K3 · conj (X t) · e t (1) θ t: filter coefficient of the equalizer at time t vector K3: constant coefficient X _t: at time t, the equalization past input signal remaining inside the vessel column vector e _t: signal from the error detector 19 conj (): input function for obtaining the complex conjugate of the complex signal (each element of the vector X _t, θ _t is complex) this Is an example of an algorithm for rewriting the filter tap coefficient by the LMS method. By this rewriting algorithm, the equalizer 180 changes the filter tap so that the input symbol R is brought closer to the symbol position P in the vicinity thereof.

FIG. 7 shows the structure of the filter of the equalizer for realizing the rewriting algorithm expressed by the equation (1) for two taps. The entire equalizer has these taps connected in series.

In the figure, the digital complex signal or the output signal of the filter tap of the previous stage is inputted to the delay device 81, the complex multiplier 86 and the conjugate complex number generator 82, respectively. In the complex multiplier 86, the input signal is delayed by the delay unit 8
5 is multiplied by the filter tap coefficient, and the tap output obtained by this is added to the tap output of the previous stage in the adder 87. Then, the tap output obtained by the adder 87 is given to the adder at the next stage. The delay device 85 delays the output of the adder 84 and outputs it. The adder 84 adds the output of the complex multiplier 83 that is a correction value for updating the tap coefficient to the current tap coefficient that is the output of the delay device 85, and outputs this as the tap coefficient of the next symbol timing. The complex multiplier 83 multiplies a signal obtained by multiplying the output of the error detector 19 by a constant gain adjustment coefficient and a signal obtained by taking a conjugate complex number from the input complex signal by the conjugate complex number generator 82, and obtains the corrected value of the tap coefficient. As adder 84
Give to. The input signal is given to the conjugate complex number generator 82, delayed by one symbol timing by the delay device 85, and given to the next tap.

In the equalization algorithm for performing the operation of bringing the input symbol closer to the reference symbol position like the algorithm described here, the center tap of the equalizer, that is, the gain of the signal after passing through the equalizer is calculated. The determined tap coefficient operates so that the average amplitude of the input signal matches the average amplitude of the symbol position P in FIG. For example, when the symbol positions determined by the symbol determiner 191 are distributed as shown in FIG. 4A, it is assumed that the input signal to the equalizer is 2/3 times as shown in FIG. 4B. As the tap coefficient of the equalizer is changed by the output of the error detection circuit 19, the center tap changes its input to 3 /
The output signal of the equalizer is shown in FIG.
Will have the symbol arrangement of. After all, the center tap of the equalizer here has the same function as the gain adjuster 22 in FIG.

When the equalizer has the function of the gain adjuster, the final magnitude of the coefficient of the center tap can be predicted. Even in the gain adjuster 22 of FIG. 1 in which the equalizer does not have the function of the gain adjuster, the delay device 2 of FIG.
The 24 outputs can be given the expected magnitude. For that purpose, when determining the reference value of the gain adjuster 22 shown in FIG. 2, as shown in FIG. 4 (b) and FIG. 5 (b), the symbol arrangements are compared to obtain the amplitude ratio. It suffices to compare the value of the signal quantized by the D converters 13I and 13Q with the value of the determination output of the symbol determining unit 191, and give the result to each. For example, the ratio of the average amplitude of the signals quantized by the resulting A / D converters 13I and 13Q and the average amplitude of the symbol determination output is the value of the center tap. If this value is given to the center tap in advance before demodulation, there is an advantage that the tap coefficient convergence time associated with the process of gain adjustment or equalization in the equalizer 18 can be shortened.

In the configuration described above, the gain adjuster 22
Alternatively, the reference value used when adjusting the gain by the main tap of the equalizer 18, the coefficient K2 or the value suitable as the initial value of the main tap is, as described above, the average amplitude of the output signal of the variable gain amplifier 10. Not only that, but also the modulation method of the original received intermediate frequency signal IFS. When the values of the coefficient K1 and the coefficient K2 are constantly 1, the multiplier 225 and the multiplier 2 respectively.
It is obvious that 1I, 21Q, etc. are unnecessary.

Further, in FIG. 1, the output of the complex multiplier 16 for phase synchronization is input to the equalizer 18, but this is an example, and the complex multiplier 16 and the equalizer 18 are shown. The order of inputting signals to the gain controller 22 is not limited to the order shown in FIG. For example, in the case of a demodulator in which the processing of the complex multiplier and the equalizer is performed in the reverse order of the configuration shown in FIG. 1, the signal output from the equalizer 18 and input to the complex multiplier 16 is It may be configured to be input to the gain adjuster 22. Further, in the case of the demodulator shown in FIG. 1, the output signal of the complex multiplier 16 may be directly input to the gain adjuster 22 without passing through the equalizer 18.
The configuration of these signal processing sequences should be determined according to the performance required of the demodulator.

Further, in the above embodiment, the symbol arrangement of the 64QAM system has been described as an example, but it is clear that the present invention is not limited to this, and modulation systems having other symbol arrangements such as 16QAM, BPSK, QPSK, 8
Even in the case of each PSK modulation method, the gain adjustment can be performed so that the symbol position output of the symbol determiner 191 to be compared with the input symbol can be expressed with a desired small number of bits, and the method is the method described by the 64QAM method. Is the same as.

Further, the demodulator of the above-described embodiment is constructed so that the received intermediate frequency signal IFS is subjected to quadrature detection and then A / D converted. This A / D conversion is performed on the received intermediate frequency signal IFS before quadrature detection. You may also do it. That is, even in a demodulator that obtains a baseband signal by performing quadrature detection after A / D converting the received intermediate frequency signal, a gain adjuster that adjusts the input gain of the A / D converter and an A / D converted signal A demodulator having a gain adjuster for adjusting the symbol position by adjusting the gain of 1 can be configured by the same method as in the above-described embodiment, and the same effect can be obtained. As described above, even for a demodulator having a configuration different from that of the demodulator shown in the embodiment, the mechanism for accurately expressing the symbol position by the gain adjustment of the present invention can be configured.

[0055]

As described in detail above, in the digital demodulator of the present invention, the first gain adjusting means is provided in front of the analog / digital converting means, and the analog gain is adjusted by the first gain adjusting means. The amplitude of the signal input to the digital / digital conversion means is adjusted to a preset amplitude level according to the dynamic range of the analog / digital conversion means, and a second signal is provided between the analog / digital conversion means and the symbol determination means. Gain adjusting means is provided, and the amplitude of the quantized signal output from the analog / digital converting means is preset by the second gain adjusting means based on the symbol determination result of the symbol determining means. I try to adjust it to the level.

Therefore, according to the present invention, the symbol position can be represented accurately and with a small number of bits without increasing the quantization error in the A / D conversion. It is possible to provide a digital demodulator capable of reducing the determination error of the symbol position in the symbol determination and the symbol determination, improving the demodulation performance, and reducing the circuit scale.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a digital demodulator according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of a gain adjuster of the digital demodulator shown in FIG.

FIG. 3 is a diagram showing another configuration example of a gain adjuster.

FIG. 4 is a diagram showing an example of a symbol arrangement with different amplitudes.

5 is a bit configuration diagram when the symbol arrangement shown in FIG. 4 is represented by 8 bits.

FIG. 6 is a symbol arrangement diagram used to describe another embodiment of the present invention.

FIG. 7 is a partial block diagram of an equalizer for implementing a replacement algorithm according to another embodiment of the present invention.

FIG. 8 is a circuit block diagram showing an example of a configuration of a conventional digital demodulator.

FIG. 9 shows a symbol arrangement in the demodulator shown in FIG.
Bit configuration diagram when expressed in bits.

[Explanation of symbols]

 10 ... Variable gain amplifier 11 ... Automatic gain control circuit (AGC) 12 ... Quadrature detector 121I, 121Q ... Quadrature detection multiplier 122 ... Local oscillator 123 ... .pi. / 2 phase shifter 13I, 13Q ... A / D converter 14 ... Oscillator for generating sampling signal 15I, 15Q ... Low pass filter (LPF) 16 ... Complex multiplier 17 ... Carrier phase synchronization circuit 171 ... Phase error detector 172 ... PLL filter 173 ... Numerically controlled oscillator (NCO) 174 ... Sine / cosine converter (sin / cos) 18 ... Equalizer 19 ... Error detector 191 ... Symbol determiner 192 ... Subtractor 20 ... Gain control circuit 21I, 21Q ... Gain adjusting multiplier 22, 23 ... Gain adjusting 221 ... Amplitude calculator 222 ... Difference calculator 223, 227 ... Adder 224 ... Delay device 225 ... Multiplier 226 ... Coefficient generator 228 ... Constant generator 81, 85 ... Delay device 82 ... Conjugate complex number generator 83, 86 ... Complex multiplier 84, 87 ... Adder

Claims (8)

[Claims] 1. A received digital modulated wave signal is quantized by an analog / digital conversion means and then a predetermined demodulation process is performed to obtain a demodulated signal, and a symbol included in this demodulated signal is predetermined by a symbol determination means. In the digital demodulator for judging according to the threshold value and using the symbol judgment result for the demodulation processing, the amplitude of the signal input to the analog / digital converting means is arranged before the analog / digital converting means. A first gain adjusting means for adjusting the amplitude level to a preset amplitude level according to the dynamic range of the analog / digital converting means, and the analog / digital converting means and the symbol determining means. The amplitude of the quantized signal output from the analog / digital conversion means is represented by the symbol Digital demodulator characterized by comprising a second gain adjusting means for adjusting the amplitude level set in advance based on the symbol decision result of constant section. 2. The second gain adjusting means obtains a difference between an amplitude value of a signal whose amplitude level is adjusted by the gain adjusting means and a reference value set in advance, and a difference means. And a means for multiplying the quantized signal output from the analog / digital conversion means by the time average value obtained by the smoothing means. The digital demodulator according to claim 1. 3. In the second gain adjusting means, the amplitude value of the signal output immediately after the start of the operation of the gain adjusting means is equal to the expected amplitude convergence value of the signal output from the gain adjusting means. 2. A gain initializing means for giving an initial value of gain preset so that
Or the digital demodulator described in 2. 4. The second gain adjusting means comprises an initial value changing means for changing the initial value of the gain given by the gain initializing means according to the modulation system of the received digital modulated wave signal. 4. A digital demodulator according to claim 3, characterized in that 5. The second gain adjusting means generates a gain adjusting magnification set to a reciprocal of the gain adjusting magnification of the first gain adjusting means, and the gain adjusting generated by this means. 2. The digital demodulator according to claim 1, further comprising means for multiplying the quantized signal output from the analog / digital converting means by a multiplication factor. 6. The second gain adjusting means, when equalizing means for performing waveform equalizing processing of a digital demodulated signal is provided between the analog / digital converting means and the symbol determining means. Output from the analog / digital conversion means by changing the tap coefficient of the equalization means based on the difference between the symbol position of the demodulated signal output from the equalization means and the symbol determination result of the symbol determination means. The digital demodulator according to claim 1, wherein the amplitude of the quantized signal is adjusted. 7. The second gain adjusting means comprises a tap coefficient initializing means for previously giving an initial value expected as a converged value of the tap to the tap of the equalizing means before starting the waveform equalization processing. The digital demodulator according to claim 6, characterized in that 8. The second gain adjusting means comprises initial value changing means for changing the initial value given to the tap of the equalizing means by the tap coefficient initializing means according to the modulation system of the received digital modulated wave signal. The digital demodulator according to claim 7, characterized in that