JPH06149752A - Barrier synchronization system for parallel computer - Google Patents

Abstract

PURPOSE:To improve the throughput of the whole system by performing fast and irreducible necessary coherence operation as a factor of an overhead in spite of essentially the same synchronous timing with a conventional system. CONSTITUTION:Parallel computers are provided with plural cache memories CM, which are accessed by processors P0, P1, P2, and P3 and store parts of the storage contents of a main memory, between the processors and the main memory which is connected with a network, and the barrier synchronization system of the parallel computers is so constituted that the execution of a next series of processes is allowed after each processor recognizes the end of a series of processes executed by plural processors on the basis of the value of a synchronous variable 'count' updated each time each process ends a process. Then the coherence operation for the synchronous variable is performed only when barrier synchronism conditions are met each time the synchronous variable is updated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a plurality of cache memories, which are accessed by the processors and store a part of the stored contents of the main memory, between a plurality of processors and a main memory connected by a network. In a parallel computer, the next series of processes is performed after each processor recognizes the end of the series of processes executed by the plurality of processors based on the value of the synchronization variable that is updated each time the processes of each processor are completed. The present invention relates to a barrier synchronization method for a parallel computer configured to allow the execution of the above process.

[0002]

2. Description of the Related Art Conventionally, when executing a calculation process in a parallel computer, a series of processes are configured by parallelized loops and each loop is assigned to each processor to realize high-speed processing. The barrier synchronization method that allows the execution of the next series of processing after each processor recognizes the end of each loop has been realized as follows. That is, the synchronization variable is mapped to the main memory, and each processor is configured to update the synchronization variable through the cache memory when the processing of the loop allocated to itself is completed, and the loop processing of itself is completed. The specified processor periodically refers to the cache to which the synchronization variable is allocated until the synchronization variable reaches a value indicating that the barrier synchronization condition is satisfied, that is, until the loop processing of another processor ends. It was configured to be in the spin wait state.

[0003]

However, in the above-mentioned conventional barrier synchronization method, a coherence operation for maintaining the consistency of data between caches is required every time the synchronization variable is updated, and the overhead of the synchronization operation itself causes the system to operate. There was a drawback that the overall throughput decreased. Invalidation protocol generally used as coherence operation, that is, main memory notifies cache memory of invalidity of data, and each cache performs block transfer of data from main memory as mishit processing that occurs when processor accesses. However, the method of adopting the method has a drawback that every time a synchronization variable is updated by an arbitrary processor, competing accesses from other processors are concentrated and the network function is deteriorated. For example, as shown in FIG. 4, four processors P
In the parallel computer configured with 0, ..., P3, among the update processing (1, 2, 3, 4) for the synchronization variable performed after the end of the loop processing assigned to each,
For (2,3,4), (11,12) respectively
And (13, 14-16), the coherence operation using the invalidation protocol is performed, and the data of the normal cache line size is transferred by the remote access of (17-22). Sometimes memory conflicts (23-26) will occur. Also,
There is also a drawback in that the data capacity transferred from the main memory to the cache memory each time the coherence operation is performed is larger than the data capacity originally required for the barrier synchronization, and there is a limit in reducing the overhead.

An object of the present invention is to allow a barrier synchronization system in a parallel computer to perform a coherence operation which is a factor of its overhead at a high speed and at a necessary minimum while giving essentially the same synchronization timing as the conventional system. It is therefore to provide a barrier synchronization method for a parallel computer capable of increasing the throughput of the entire system.

[0005]

In order to achieve this object, a characteristic configuration of a barrier synchronization system of a parallel computer according to the present invention allows caching of the synchronization variable, and a barrier periodic condition among the updates of the periodic variable. The point is that the coherence operation for the synchronization variable is performed only when the above condition holds. In the above configuration, it is preferable that the coherence operation is a write / update type coherence operation. Further, it is preferable that the data transferred by the coherence operation is composed of only the minimum data indicating the establishment of the barrier synchronization condition.

[0006]

In other words, the processor that has completed its own loop processing only needs to be able to determine the timing at which the barrier synchronization condition is satisfied from the synchronization variable, and the synchronization variable that changes one after another until the barrier synchronization condition is satisfied. Focusing on the fact that the value itself is essentially unnecessary, if the coherence operation for the synchronization variable is performed only when the synchronization condition is satisfied among the updates of the synchronization variable, the barrier synchronization timing is essentially the same as that of the conventional method. Therefore, there is no inconvenience even if the synchronization variables temporarily existing in a plurality of cache memories are allowed to be inconsistent.

Then, as a protocol of the coherence operation which is performed only when the synchronization variable indicating the establishment of the barrier synchronization condition is established, a generally used invalidation protocol, that is, the main memory notifies the cache memory of invalidity of data. However, instead of the method of block transfer of data from the main memory as a mishit process that occurs when each cache accesses from the processor, a protocol of a write update method, that is, the main memory transfers a block of valid data to the cache memory. By using this method, the overhead can be further reduced.

Further, the data to be transferred at that time is limited to the minimum data indicating the establishment of the barrier synchronization condition, that is,
Limiting the synchronization variable and its associated data can reduce the data transfer time and further reduce the overhead.

[0009]

According to the present invention, while giving essentially the same synchronization timing as the conventional method, the coherence operation that causes the overhead is performed at a high speed and to the minimum necessary, and the throughput of the entire system is improved. It has become possible to provide a barrier synchronization method for parallel computers that can improve the performance.

[0010]

EXAMPLES Examples will be described below. As shown in FIG. 3, a plurality of processors P0, P1, P2, P3 are provided with a plurality of cache memories CM respectively connected via a first network B1, and these cache memories C are provided.
M through main network MM via second network B2
A parallel computer C is configured by connecting to each other, and a high-speed processing is realized by allocating each loop to each processor P0, P1, P2, P3 among a series of processing configured by parallelized loops. To do.

The main memory MM is composed of a memory controller MMC that controls data transfer with the cache memory CM and manages its own data, and a data section MMD that stores data. The data part MMD of the main memory MM and the data part CM3 of the cache memory CM are divided into blocks of the same size, and data is normally transferred in units of blocks.

The cache memory CM has a directory section CM2, a data section CM3 for reading and storing a part of data from the main memory MM, and the main memory MM corresponding to accesses from the plurality of processors P. And a cache control unit CM1 for controlling the reading and writing of data between them.

The directory portion CM2 has a capacity corresponding to the number of sets of cache memory and the number of ways, and each unit is an address tag portion CM21 indicating the position of corresponding data on the main memory MM, that is, a block address. , Whether or not the way is allocated as a block indicated by an address tag, that is, a valid bit V indicating whether data is valid or invalid, and the head of data to be actually transferred among blocks to be allocated to the way. It is composed of an attribute portion CM22 indicating an address and a data amount. Here, the valid bit V is a flag used for the coherence control of the invalidation system, and is reset by the control signal indicating that the consistency of the data transmitted from the main memory MM cannot be maintained, and is targeted for the data update processing. This is a flag that is set when a block is allocated, that is, at the start of the update process, and the status bit B
Is a flag that is set by the start of the update process and reset by the end.

The cache control unit CM1 compares the address information obtained via the first network B1 with the block address of the address tag unit CM21, and the comparison unit determines that the addresses match. In addition, when the valid bit V is set (hereinafter, referred to as "cache hit"), the data transfer control unit and the comparison unit that exchange the relevant data with the processor P determine that they do not match, Alternatively, when the valid bit V is reset (hereinafter, referred to as "cache miss hit"), the second network B
2, a data replacement processing unit for performing data replacement processing on the main memory MM via 2, and a logic circuit for controlling the operations thereof.

A case will be described where the above-mentioned parallel computer is used to execute an application in which a plurality of series of processes (referred to as "body") composed of parallelized loops are combined, and each processor P0, P1, P2, P
After executing the processing of the loops assigned to each of the three, the barrier synchronization is taken based on the algorithm shown in FIG. 2 and the processing of the next body is started.

A detailed description will be given below with reference to FIG. A counter "count" that stores a synchronization variable is mapped to one block of the data part MMD of the main memory MM (here, two types of counters are mapped assuming execution of a plurality of bodies), The number of processors 4 is set as an initial value. Each processor P0, P1, P2
When P3 finishes its own loop processing, the subtraction instruction "fetch and decrement" of the counter "count" is given to each cache memory CM.
To execute. The corresponding cache memory CM sets the value of the counter “count” to 1 with respect to the main memory MM.
Fetch the value that has been subtracted.
(In this case, after the value of the counter "count" is fetched (fetched), the value obtained by subtracting (decrementing) 1 from the value may be stored in the main memory MM.) The above subtraction instruction is executed from each processor. Every time the counter "count" on the main memory MM decreases, the counter "c" allocated to another cache memory.
Although the value of “outt” is deviated, the memory controller MMC does not perform the above-described invalidation-type coherence control for each cache memory CM until the barrier condition is satisfied. Now, the processors P0, P3, P2, and P1 When the barrier condition is satisfied, that is, when the counter “count” value becomes 0, the memory controller MMC performs write-update type coherence control for each cache memory CM, that is, all caches. A counter "cou" with a value of 0 for the memory CM
nt "data is transferred. At this time, the transfer data capacity does not transfer all the data of the block to which the counter" count "data is mapped, but the counter" count "data of the block address is mapped. Only the counter "count" data is transferred together with the existing address information.

Each processor P0, P1, P2, P3
When it is confirmed that the counter "count" value in each cache memory CM is 0, the processing of the next body is started, and thereafter the same barrier synchronization processing is repeated to complete the application.

Another embodiment will be described below. The parallel computer described in the above embodiment has been described as being configured with a cache memory unique to each processor. However, it is a parallel computer in which one cache memory among a plurality of cache memories is shared by some processors. Even if there is, it can be applied similarly. Further, the execution of the body does not necessarily need to be performed by allocating a loop to all the processors, and may be executed by any number of processors. At this time, the initial value of the synchronization variable may be set to the number of processors in charge of executing the body. Further, at this time, different bodies are executed by different processor groups by the same barrier synchronization control.

[Brief description of drawings]

FIG. 1 Flowchart of barrier synchronization

FIG. 2 is an explanatory diagram showing an algorithm of barrier synchronization.

FIG. 3 is a block diagram of a parallel computer.

FIG. 4 is a flowchart of barrier synchronization showing a conventional example.

[Explanation of symbols]

 CM cache memory MM main memory P0, P1, P2 processor

Claims (3)

[Claims] 1. A parallel computer having a plurality of cache memories, which are accessed from the processor and store a part of the stored contents of the main memory, between the plurality of processors and a main memory connected by a network,
After each processor recognizes the end of the series of processes executed by the plurality of processors based on the value of the synchronization variable that is updated each time the process for each processor ends, the next series of processes is executed. A barrier synchronization method of a parallel computer configured to allow, allowing caching of the synchronization variable, and performing coherence operation for the synchronization variable only when a barrier synchronization condition is satisfied in each update of the periodic variable. A barrier synchronization method for parallel computers configured to perform. 2. The barrier synchronization method for a parallel computer according to claim 1, wherein the coherence operation is a write / update type coherence operation. 3. The barrier synchronization method for a parallel computer according to claim 1, wherein the data transferred by the coherence operation is composed of only a minimum amount of data indicating that the barrier synchronization condition is satisfied.