JPH02297656A - Data control system - Google Patents

Abstract

PURPOSE:To reduce the scale of a hardware by writing write data to a cache memory of a central processing unit itself by the central processing unit in a reception side only when the data are coincident with a parallel processing task identifier which is stored in a parallel processing task identifier storing means. CONSTITUTION:When write operation is generated in a certain central processing unit at the time of program execution and the write data are written to a cache memory 6, the parallel processing task identifier is broadcasted to all the other central processing units together with the write data and a write address. The write data, write address and parallel processing task identifier are received by the central processing unit to be recognized under parallel processing by a parallel processing state recognizing means 100. The central processing unit in the reception side compares the parallel processing task identifier, which is stored in a parallel processing task identifier storing means (PIDR) 7, with the received parallel processing task identifier and when the identifiers are coincident, the write data are written to the cache memory 6. Thus, the scale of the hardware is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention applies to a multiprocessor system that shares a main memory, especially when parallel processing is performed. It relates to a data control method for controlling data.

[Conventional technology]

Conventionally, in multiprocessor systems that share main memory, maintaining the validity of data among multiple central processing units has been an important issue since they share data in a single main memory. . That is, when a central processing unit modifies a copy of data in cache memory or some main memory in local memory,
Any other central processing unit that maintains a copy of the data at the same address as the modified main memory data in cache memory or local memory is told to invalidate that copy because it is no longer usable. The practice was to give instructions. In this method, in order to use this invalidated data again, this data is retrieved from the main memory again, or if the central processing unit has the data, this data is retrieved from the central processing unit where it was last modified. There is a need. For this reason, when the same data is shared by multiple central processing units, data transfer may occur frequently. This resulted in a number of communications taking place.

A multiprocessor system disclosed in Japanese Patent Publication No. Sho 62-55187 is an example of a conventional system that improves this and reduces communication between the central processing unit and the main memory, or between the central processing units.

7 and 8 are block diagrams showing a cache memory control section of a multiprocessor system disclosed in Japanese Patent Publication No. 62-55187, and a diagram showing the contents of a cache directory.

Note that the explanation of FIGS. 7 and 8 is given in the publication, so the explanation will be omitted here.

In a conventional example such as the multiprocessor system shown in Japanese Patent Publication No. 62-55187, a flag called an exclusive control (EX) flag is provided in the cache directory to correspond to each piece of data in the cache memory. , depending on whether this flag is on or off, it is shared by multiple central processing units and only readable (
Rb) It is possible to distinguish between data that is exclusively held and written by one central processing unit (EX) data, and that data is exclusively used privately by that central processing unit. data, or data shared with other central processing units throughout the system.

As a result, access to private data of any central processing unit has no effect on other central processing units, and there is no need to disable it. Processing called a mutual inquiry request to check whether copies of the same data are held is also unnecessary, so overhead can be reduced.

Also, on the side of the central processing unit that issues the request,
Access to private data (EX request) in the same way as the exclusive control flag in the request issued by yourself
or read-only access (RO request) to shared data. For accesses where only reading is performed, R
When fetching data that will be written in the near future, it is set to EX read at the time of reading so that writing can be performed immediately.

EX requests include both reading and writing, but RO requests only have writing, and writing can only be performed with EX requests.

Therefore, when access to private data is specified in an EX request, other central processing units are not affected in any way when the access occurs, so invalidation does not occur, and data that needs to be invalidated is not affected. There is no need for cross-inquiry to find out whether or not the information is maintained.

It is disclosed that the configuration as described above can reduce the overhead associated with communication between processors for maintaining the validity of data within a multiprocessor system.

[Problem to be solved by the invention]

However, in a conventional multiprocessor system as shown in Japanese Patent Publication No. 62-55187, the data in the cache memory of each central processing unit is shared by all central processing units and is data that is only readable. It only identifies two types of data: private data that is held only in one central processing unit and is allowed to be written without affecting other central processing units; It was not possible to differentiate cache memory control for each task.

In addition, since a flag bit is attached to the cache directory to indicate the distinction between shared data and private data, flags are retained for all entries in the cache directory for the same number of data retained in the cache memory. This increases the capacity of the cache directory, and requires a comparator to compare flag bits to accommodate the additional cache directory entries, which requires more hardware. There was a problem with that.

In this way, in conventional systems, it is not possible to differentiate cache memory control for each task that is being processed in parallel, making it impossible to improve the execution efficiency of multiple parallel processing tasks. There was a problem in that it required a large amount of hardware, making it difficult to downsize.

This invention was made to solve the above-mentioned problems, and in addition to realizing hardware downsizing,
The purpose of this invention is to provide a data control method that can improve the execution efficiency of multiple parallel processing tasks.

[Means to solve the problem]

The data control method according to the present invention is exclusively added for each task to be executed in parallel from the time when parallel execution of a certain program starts until the time when the execution of the program ends. The parallel processing task identifier is stored in the parallel processing task identifier storage means (PIDR7) of the central processing unit used for parallel execution among all the central processing units 1, and a write operation occurs when a certain central processing unit executes a program. When the write data is written to the cache memory 6, the parallel processing task identifier is broadcast together with the write data and the write address to all other central processing units, and the parallel processing state recognition means 10
Only the central processing unit that is recognized as being in parallel processing by 0 receives the write data, write address, and parallel processing task identifier, and furthermore, the central processing unit on the receiving side stores the parallel processing task identifier storage means (PIDR7).
This feature is characterized in that the write data is controlled to be written into its own cache memory only when the parallel processing task identifier matches the parallel processing task identifier stored in the parallel processing task identifier.

[Effect]

From the time when parallel execution of a certain program starts until the time when execution of the program ends, the parallel processing task identifier is stored in the parallel processing task identifier storage means (PIDR7) of the central processing unit used for parallel execution. be done.

When a write operation occurs in a certain central processing unit when a program is executed and the write data is written to the cache memory 6, a parallel processing task identifier is broadcast to all other central processing units along with the write data and write address. be done. The write data, write address, and parallel processing task identifier are received by the central processing unit that is recognized by the parallel processing state recognizing means 100 as being in parallel processing. The central processing unit on the receiving side uses parallel processing task identification brush storage means (PIDR7).
The parallel processing task identifier stored in the parallel processing task identifier and the received parallel processing task identifier are compared, and if a match is detected, the write data is written to the cache memory 6 of the central processing unit.

[Embodiments of the invention]

FIG. 1 is a block diagram showing a multiprocessor system employing a data control method according to an embodiment of the present invention. In the figure, 1a and 1b are central processing units that perform data processing, 2 is a system control unit that controls the entire system, and 3
4 is a main storage device that stores information necessary for data processing; 5a and 5b are central processing units 1a and lb;
address control units 6a and 6b are central processing units la and l.
cache memory 7a, 7b central processing unit 1a;
, lb parallel processing task identifier (PIDR), 8a.

8b is a main memory access data bus; 9a and 9b are main memory access address buses; 10a and 10b are main memory access PID buses; 11 is a system controller data bus;
2 is a system controller address bus, 13 is a system controller PID bus, 14 is a main memory address bus, 1
5 is a main memory data bus. The inside of the central processing unit is shown in FIG.

FIG. 2 is a block diagram showing in more detail one of the central processing units constituting this multiprocessor system. In the figure, 1 is a central processing unit, 5 is an address control unit, and 6 is a central processing unit.
is cache memory, 7 is PID register (PIDR)
, 8 is a main memory access data bus, 9 is a main memory access address bus, 10 is a main memory access PID bus, 16
17 is an execution control unit that controls program execution; 17 is a PI
Parallel processing mode flag set by D register 7, 18 a comparator that compares the output of PID register 7 and the output of MPIDR below, 19 main memory data bus register (MDBR), 20 main memory address bus register ( MABR), 21 is the main memory PrD path register (M
PIDR). For the sake of simplicity, it is assumed that all basic components of a computer such as arithmetic units, which are not related to the present invention, are included in the execution control unit, and will not be specifically explained.

Next, the operation of this embodiment will be explained.

In this embodiment, the central processing unit (hereinafter referred to as CPU)8
Assume a multiprocessor system consisting of several processors. Each C
The PU1 includes an execution control unit 1 that controls program execution.
6. There is a cache memory 6 and an address control unit 5 that controls addresses for main memory access or cache memory access.

Here, for the sake of simplicity, it is assumed that the arithmetic unit, data register, etc. are included in the execution control unit 16, and that the cache directory that holds the address of the cache memory 6 is included in the address control unit 5. Main memory access accompanying program execution is performed by transferring the main memory address requested by the execution control unit 16 to the address control unit 5.
makes a judgment, generates an address of the cache memory 6 or a real address of the main memory, issues a request, and causes the cache memory access or the main memory access to be performed. To access the main memory, a request address is stored in the main memory address bus register (hereinafter abbreviated as MABR) 20, and sent from the main memory access address bus 9 to the system controller address bus 12, and the request address is sent to the main memory address bus register (hereinafter abbreviated as MABR). 14 to request the main storage device 4.

The requested data is taken into the main memory data bus register (hereinafter abbreviated as MDBR) 19 from the main memory device 4 via the main memory data bus 15, system controller data bus IL, and main memory access data bus 8. Store in cache memory 6.

When data in the cache memory 6 of this CPU is requested from another CPU, the request address is transferred from the main memory access address bus 9 to the MABR 20.
The address control unit 5 determines the request address and transfers the data from the cache memory 6 to the MDB.
Read to R19, from main memory access data bus 8,
The data is sent to the system controller data bus 11.

On the other hand, within the CPUI there is a PIDR 7 that stores parallel processing task identifiers, which can be read and written by instructions. For purposes of explanation, assume that PIDR7 is 4 bits. When necessary, the parallel processing task identifier in the PIDR 7 is stored in the MPIDR 21 and sent via the main memory access PID bus 10 to the system control bag W.
It can be sent to the PID bus 13. Also, other C
The parallel processing task identifier sent from the PU is MPI
It can be received by the DR 21 and compared with the parallel processing identifier in its own PIDR 7 by the comparator 18.

In addition, the parallel processing task identifier in PIDRV determines whether or not a parallel processing task is being executed according to its value, and when it is recognized that a parallel processing task is being executed, a parallel processing mode flag is set. Turn on 17.

FIG. 3 shows a circuit (parallel processing state recognition means 100) that tests the parallel processing task identifier and tests the parallel processing state.
) shows an example. By the OR gate 22, PI
When there is a bit that is turned on among the bits of DR7, the parallel processing mode flag 17 is turned on, indicating that a parallel processing state is entered.

The value of the parallel processing task identifier is assigned exclusively within the multiprocessor system, so that no other task with the same value exists at any given point in time. This exclusive assignment of parallel processing task identifiers can be realized, for example, by allowing a control program that manages tasks to be executed in a multiprocessor system to allocate them.

For example, it is assumed that the definition is as shown in FIG. In this example, a parallel processing task identifier of "0" is assigned to a normal task that is not assigned to parallel processing but is assigned to one CPU. In other words, the fact that no bit is turned on means that parallel processing is not performed. By allocating one bit to each parallel processing task in the following order, four parallel processing task groups are defined, and up to four parallel processing tasks can exist simultaneously in the multiprocessor system.

This assigned parallel processing task identifier is simultaneously written into the PIDR 7 of all CPUs executing the parallel processing task by the control program when execution permission for the parallel processing task is granted and execution is started. So-called synchronization processing for simultaneous writing can be easily realized by a locking mechanism by a control program in a shared main storage area. This parallel processing task identifier is held until the corresponding parallel processing task is saved due to completion of execution of the parallel processing task or task switch. If a parallel processing task is saved by a task switch, the contents of PIDR7 are also saved along with the saved data register, control register that stores control data, program counter that holds the address of the instruction being executed, etc. and restore it in the same way when restarting this task.

Here, an example of assignment of parallel processing task identifiers and the operation of the cache memory 6 according to the assignment will be described.

For example, suppose three tasks exist within a multiprocessor. One is a "Group 0" parallel processing task that uses four CPUs, the second is a "Group 2" task that uses three CPUs, and the third is a single non-parallel processing task. This is a normal task processed by the CPU.

FIG. 6 shows the value of PIDR7 of each CPU at a certain point in time. In this example, the parallel processing tasks of group O are CPU・o, cpU・1. CPU・2
is assigned to CPU 5, and the P of these four CPUs is
A parallel processing task identifier of “1ooo <binary)” is set in IDR7. Group 1 parallel processing tasks are CPU 3. It is assigned to CPU-4 and CPU-7, and “00” is assigned to PIDR7 of these three CPUs.
A parallel processing task identifier of 10 (binary)' is set. A normal task is assigned to CPU 6, and PIDR7 is assigned “oooo <binary)
” parallel processing task identifier is set.

Here, it is assumed that the CPU 0 stores data in the cache memory 6. In this CPU, the parallel processing task identifier in PIDRT is "1000 (binary)", so the parallel processing mode flag 17 is on.
It is in parallel processing state.

The data of CPU 0 in parallel processing state is transferred to other CPUs.
This indicates that the stored data and its address may be shared in the MDBR 19 and MABR 20, as a copy of the same data may exist in the cache memory 6 of another CPU. Then, from the main memory access data bus 8 and the main memory access address bus 9, all (7
) broadcast to the CPU. At this time, CPU-0 (7) P I
DR? The value of the parallel processing task identifier in MPIDR2
1, and main memory access PID at the same time as data
System control bag from bus 10? It is broadcast to all CPUs using the 1fpID bus 13.

The broadcasted addresses on the system controller address bus 12, data on the system controller data bus 11, and parallel processing task identifiers on the system controller PID bus 13 are all for which the parallel processing mode flag 17 is on. CPU.

That is, CPU・1, CPU・2, CPU・3, CP
MABR2 by U-4, CPU-5, CPU-7
0, MDBR 19, and MPIDR 21, and the transmitted parallel processing task identifier and the value of PIDR 7 are compared by a comparator 18. Of these, CPU・1,
As a result of this comparison, CPUs 2 and 5 match, so they know that the broadcasted data belongs to CPU 0, which shares the data with them, and store the corresponding data in their own cache memory 6. It searches for data at the specified address, and if it has a copy of that data, it overwrites the data there and updates it, thereby maintaining the validity of the data.

On the other hand, CPU-3, CPU-4, and CPU-7 compare the sent parallel processing task identifier with the value of PIDR7 and find that they do not match. Knowing that it is not CPU 0, I throw away the broadcast data. Naturally, the address search within the cache memory 6 is not performed either.

Furthermore, the value of the parallel processing task identifier of PIDR7 is "0000 (binary)", and CPU 6 is executing a normal task, is not performing parallel processing, and is copying all broadcast data. Since there is no possibility that the program has the data, it ignores all the data that has been broadcast and moves on to the next process.

Next, when the parallel processing task identifier of the CPU that performed the store is "0000 (binary)", that is, the CPU
Consider when U.6 performs a store.

The value of the parallel processing task identifier of PIDR7 is "oooo <binary)" for CPU 6, which means that it is performing a normal task and is not performing parallel processing. Therefore, the data stored in the cache memory 6 by the CPU 6 is private data of the CPU 6.
This indicates that there is no possibility that this copy exists in other CPCIs.

Therefore, when the CPU 6 stores data in the cache memory 6, there is no need to perform any communication with other CPUs, and only writing to the cache memory 6 is performed.

By the way, in the above embodiment, when a plurality of CPUs simultaneously execute a plurality of tasks under the supervision of a control program, the control program allocates a parallel processing task identifier having an exclusive value to the plurality of tasks, The parallel processing task identifier corresponding to the task currently being executed on the relevant CPU is always retained, and when the control program changes the task that is being executed in parallel using multiple CPUs, the task is changed. all CP
It is also possible to synchronize U0 and change the parallel processing task identifier at the same time.

In this way, the data control method of the above embodiment has multiple CPs.
When processing is being performed in parallel by some of U', each CPU must indicate that it is one of the CPUs performing parallel processing and is currently performing parallel processing. When processing is being performed in parallel by several central processing units, each CPU can respond to tasks that are being executed in parallel by itself. The process of selecting and allocating an exclusive parallel processing task identifier within a multiprocessor system, the process of retaining the assigned parallel processing task identifier, and the process of allowing any CPU to identify the parallel processing task it is currently executing. Parallel processing task identifier to all other CPUs
1-to-1 transfer of data directly between the cache memories of all CPUs, or 1-to-multiple broadcast processing, and processing to transfer data addresses accompanying data transfer. .

According to the above embodiment, each central processing unit is in a state in which it is executing a task by parallel processing using multiple central processing units, or is in a state in which it is executing a single task individually by itself. When processing one task individually, the data used to process that task is considered to be private data and is not sent to other central processing units. It is stipulated that there will be no influence whatsoever. Also, when performing parallel processing, it is assumed that data shared with other central processing units is used, and only when parallel processing is performed, a certain central processing unit writes to the cache memory. When this is done, the corresponding address in the cache memory of the other central processing units is changed. Furthermore, normally when such a change is made, the data at the changed address is invalidated or broadcast to all central processing units and rewritten, but this broadcasting light is By limiting the overhead on the receiving side and managing the tasks exclusively with as little hardware as possible, it is possible to independently manage multiple tasks in parallel processing that exist simultaneously in a multiprocessor system. Accordingly, writing control to the cache memory of each central processing unit can be performed separately, and a multiprocessor system that can efficiently execute a plurality of parallel processing tasks can be obtained.

In the above embodiment, the 4-bit parallel processing task identifier was defined as 4 groups, but as shown in FIG. 5, each bit is not defined as 1 bit, but the parallel processing task identifier is numbered sequentially A similar effect can be obtained by defining up to 15 groups with 4 focal points. Further, in the above embodiment, the number of central processing units is limited to about eight, and the parallel processing task identifier is limited to 4 bits, but the same effect can be obtained even if the number of bits is expanded. Furthermore, in the above embodiment, the explanation is limited to a plurality of central processing units connected to the system control unit, but this also applies when an input/output device that performs main memory access is connected. It is possible.

〔Effect of the invention〕

As described above, according to the present invention, among the requests issued and received between each central processing unit, unnecessary requests from other central processing units are ignored and truly necessary requests are selected. It is also possible to recognize requests for private data and issue requests to other central processing units using less hardware and without having the same impact on other central processing units. This makes the processing for maintaining data validity in multiprocessor systems more efficient, and reduces the number of communications between central processing units, thus reducing the hardware size. can be realized, and the execution efficiency of multiple parallel processing tasks can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of a multiprocessor system adopting a data control method according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the central processing unit in FIG. 1, and FIG. The figure is a circuit diagram of a control circuit related to the PID register of the central processing unit, FIGS. 4 and 5 are diagrams showing examples of assignment of parallel processing task identifiers to parallel processing tasks in this embodiment, and FIG. A diagram showing an example of assignment of parallel processing task identifiers in a multiprocessor system having eight central processing units in this embodiment, FIG. 7 is a block diagram showing the configuration of a cache memory control unit of a conventional multiprocessor system, FIG. 8 is a diagram showing the contents of the cache directory in this conventional example. la, lb, 1--CPU (central processing unit), 4-
...Main storage device, 6a, 6b, 6... Cache memory, 7a, 7b, 7... PIDR- (parallel processing task identifier storage means), 100... Parallel processing state recognition means. Agent: Masuo Oiwa (and 2 others) Figure 1 Figure 2 Figure 3 ``Island Pavilion with Drum Row Treatment'' Figure 4 Figure 6 PIDR A J1 Procedural Amendment (Voluntary)

Claims (1)

[Scope of Claims] A multiprocessor system configured to include a plurality of central processing units that share a main memory that stores information necessary for data processing and is equipped with a cache memory that can be read or written at high speed, From the time when the parallel execution of a certain program starts until the time when the execution of the program ends, the parallel processing task identifier that is exclusively added corresponding to each task to be executed in parallel is used by all central processing The parallel processing task identifier of the central processing unit used for parallel execution in the device is stored in the storage means, and when a write operation occurs in one central processing unit when a program is executed, and the write data is written to the cache memory, another The parallel processing task identifier is broadcast together with the write data and the write address to all the central processing units of and a parallel processing task identifier, and further writes the write data into its own cache memory only when the receiving central processing unit matches the parallel processing task identifier stored in the parallel processing task identifier storage means. A data control method characterized by controlling.