JPH06149569A - Register number changing device - Google Patents

Abstract

PURPOSE:To shorten instruction decode time and to reduce the amount of circuit by changing the register number of an instruction generating any competition into an unused register number stored in an unused register number storage means. CONSTITUTION:A register competition detection part 5 detects the register competition, an instruction selection part 2 decides which instruction in an instruction buffer 1 is first executed, a register number change control part 7 performs reloading control to the register number of that instruction, and an execution unit 3 executes that instruction. In that case, the source operand of arithmetic is read from a register file 4 or a name change register 8, and the arithmetic result is written in the register file 4 or the name change register 8. Then, a name change register control part 9 holds the unused register in the name change register 8 with queue structure and reports the register number at the head of this queue to the register number change control part 7. When the register number of the instruction buffer 1 is reloaded, that number is extracted from the queue.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, the present invention relates to a register number changing device used in an information processing device capable of efficiently processing register conflict.

[0002]

2. Description of the Related Art Conventionally, in an information processing apparatus, there is a problem that a high speed execution cannot be realized due to a state called register hazard, that is, register conflict, and in order to avoid this problem, a method called register renaming Was taken. First, register conflict will be described, and then the register renaming method will be described.

FIG. 2 shows an example of an instruction sequence that causes register conflict. Where ADD and SU
B is an instruction type, which is an addition or subtraction instruction, respectively.
The first argument that comes next is the register number portion that should store the instruction execution result, and the second and third arguments that follow are the register number portion that holds the operation argument. Here, it is assumed that the information processing apparatus performs pipeline control and performs pipeline stage processing as shown in FIG.

In FIG. 3, each stage F, D, E,
Reference characters M and W respectively represent stages for fetching an instruction, reading an instruction decode / source operand, executing an instruction / calculating an address, accessing a memory, and writing a register.

FIG. 4 shows the timing when the instruction shown in FIG. 2 is executed in the pipeline stage shown in FIG. The operation when the instruction shown in FIG. 2 is executed will be described with reference to FIG.

Since the instruction (2) of FIG. 2 is a subtraction instruction which uses the execution result R12 of the addition instruction of (1) as the second argument, after the register write stage W of (1),
The instruction execution / address calculation stage E of (2) must be performed, and the execution start of (2) is delayed. further,
Since the instruction (3) is an addition instruction that uses the execution result R10 of (2) as the second argument, after the register write stage W of (2), the instruction execution / address calculation step of (3) is performed. J must be performed, and the start of execution of (3) is delayed. In the case of the following instruction (4), it is necessary to write to R10 after the reading of R10 by the register write stage W of these instructions (2) and the instruction of (3) is completed. In addition, the execution start of the instruction of (4) is delayed. Such a factor that delays the start of execution is called register conflict. In particular, the register conflict between (3) and (4) is reduced to WAR (write after r).
ead) hazard, and register conflict between (2) and (4) is caused by WAW (write after write).
e) It is called a hazard.

In the conventional register conflict, the WAR hazards that occur between (3) and (4) and between (2) and (4).
A register renaming method has been adopted in order to solve the data hazard between the data and the WAW hazard. Next, this method will be described.

FIG. 5 is a block diagram showing the structure of the register renaming system. In the figure, 20 is an instruction buffer for storing a plurality of instructions. Reference numeral 21 denotes an instruction selection unit that determines and selects the instruction execution order from the register conflict state. A register conflict detection unit 22 detects register conflict between instructions. An execution unit 23 executes the instruction selected by the instruction selection unit. Two
Reference numeral 4 is a register file. Reference numeral 25 is a register change table.

In such a configuration, the register line
In the Mming method, when the instruction (4) read from the instruction buffer 20 is decoded, the write destination register in the register file 24 is used in the instructions (2) and (3). It is detected by the detection unit 22. When the register conflict detection unit 22 detects it,
If this register conflict is the only obstacle for executing the instruction of (4), the write destination register number of the instruction of (4) is changed at the start of execution, and the register change table 25 further stores the register. The number is changed and the destination is written. Since the register number is changed in this way, the execution timing of the instruction sequence is as shown in FIG.
As a result, the execution of the instruction of (4) starts earlier. After this instruction, when executing the instruction that uses the register where the register hazard occurred, the register change table
The bull 25 is checked to identify that the register number has been changed, and the change destination is read to access the change destination register.

FIG. 6 shows the configuration of the register change table 25. In that table, R10 is written in the register number (1) and R32 is written in the corresponding register number (2). Therefore, when this table is checked, the register is written in R10. There is a change in the number, and the change destination can be identified as R32.

[0011]

However, in the conventional register renaming system as described above, it is necessary to refer to the register change table 25 for each register access. Therefore, the register change table 25 is referred to. Only time
It had the drawback that it would take a long time.

Further, since the register change table requires a large amount of circuits, there is a drawback that the circuit scale increases.

[0013]

Therefore, the present invention has been made to eliminate the above-mentioned drawbacks. According to the register number changing device of the present invention, a plurality of instructions can be held.
In an information processing device having a register conflict detection function for detecting register conflict in a plurality of instructions and a preceding control function for starting execution from an instruction in which register conflict does not occur, a register specified by the register number of the instruction A register for change provided separately from the register file that it has, an unused register number storage means for holding an unused register number in the register for change, and an instruction in which a conflict occurs when register conflict is detected. Register number changing means for changing the register number of No. 1 to the unused register number stored in the unused register number storing means.

[0014]

With this structure, it is not necessary to always check the register change table when register conflict is detected, which is necessary for shortening the instruction decoding time and for the conventional register change table. It is possible to reduce the number of circuits required.

[0015]

EXAMPLES The present invention will be described below with reference to examples.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an instruction buffer. Two
Is an instruction selection unit. 3 is an execution unit. Four
Is a register file. Reference numeral 5 is a register conflict detection unit. 6 is a register number changing device. 7 is
It is a register number change control unit. Reference numeral 8 is a name change register. Reference numeral 9 is a name change register control unit.

The instruction buffer 1 holds a plurality of instructions prior to execution, and the information processing apparatus shown in the figure selects an executable instruction from the instruction buffer 1 and executes it.

The register conflict detection unit 5 detects register conflict between instructions held in the instruction buffer 1 and between instructions being executed, for example, by comparing all register numbers.

The instruction selecting section 2 receives the register conflict state from the register conflict detecting section 5 to determine which instruction among the instructions in the instruction buffer 1 is to be executed first and to select it.

The register number change control unit 7 controls the rewriting of the register number of the instruction in the instruction buffer 1 based on the conflict determination result of the register conflict detection unit 5.

The execution unit 3 executes the instruction selected by the instruction selecting section 2. At that time, the source operand of the operation is read from the register file 4 or the name change register 8 and the operation result is written in the register file 4 or the name change register 8. The selection of the register file 4 or the name change register file 8 is instructed by the register number of the instruction in the instruction buffer 1 rewritten by the register number change control unit 7.

The name change register control section 9 holds an unused register in the name change register 8 in a queue structure, and notifies the register number change control section 7 of the register number at the head of this queue. . When the register number change control unit 7 receives this register number and rewrites the register number of the instruction buffer 1 with the register number, the register number is taken out from the queue. The unused register number in the name change register 8 is added to the end of this queue.

Next, the operation will be described with reference to the instruction sequence shown in FIG. Further, the timing at which the instruction sequence shown in FIG. 2 is executed is the same as that in FIG.

First, the name change register 8 and the name change register controller 9 will be described. As shown in FIG. 8, the name change register 8 is an 8-word register which is sequentially numbered from the register file 4, and its initial state is not specified.

As shown in FIG. 9, the name change register control section 9 puts the number of the register which has become unused in the name change register 8 at the end of the queue as an input and causes the register number change control section 7 to start It outputs the register number of.

Next, the operation when register conflict occurs in the above configuration will be described with reference to FIG. 7 with the instruction sequence of FIG.

At time 1, the instructions (1) and (2) are fetched.

At time 2, the instructions of (3) and (4) are fetched and the instruction decoding of (1) and (2) is performed.
The register conflict detection unit 5 further detects register conflict. Here, since there is a hazard regarding the register number R12 between the instructions (1) and (2), only the instruction (1) is issued and passed to the execution unit, and the instruction (2) is issued. Is not done.

At time 3, the instruction of (1) is executed by the execution unit 3, the instructions of (3) and (4) are decoded, and the instruction to be executed next is determined.
At this time, the instruction (2) is not considered as a candidate for the execution instruction because the execution result of the instruction (1) is not yet in the register file 4. The instruction (3) is not a candidate for an execution instruction because there is a hazard regarding the register number R10 between the instruction (3) and the instruction (2). The command of (4) is
WA with respect to R10 between the instructions of (2) and (3)
Although there are W and WAR hazards, by rewriting the register number R10 of the instructions of (2) and (3) to another register number as shown below, (2) and (3)
Execution can be started before the instruction of.

First, the register conflict detection unit 5 detects the hazard between the instructions (2) and (3) and the instruction (4). When this is notified to the register number change control unit 7,
The register number change control unit 7 takes out the register number R32 at the head of the queue from the name change register control unit 9,
R10 of the instructions (2) and (3) in the instruction buffer 1 is rewritten to R32. The name change register control unit 9 extracts R32 from the beginning of the queue.

Which register number of which instruction is rewritten is determined from various conditions such as processing time.

At time 4, the memory access of the instruction (1) and the execution / address calculation of the instruction (4) are performed.

At time 5, the operation result of the instruction (1) is written in the register file 4 and the memory access of the instruction (4) is performed. Furthermore, since the source operand of the instruction of (2) is obtained by writing the instruction of (1) to the register file 4, the instruction selecting unit 2 selects the instruction of (2).

At time 6, the instruction (2) is executed and the execution result of the instruction (4) is written in the register file 4.

At time 7, the memory access stage of the instruction (2) is started.

At time 8, although the operation result of the instruction (2) is originally written in the register file 4,
Since the write destination is changed to the register number R32, the result is written to R32 in the name change register 8. Furthermore, since the last remaining source operand of the instruction of (3) is obtained by the end of the instruction of (2), the instruction selecting unit 2 selects the instruction of (3) and the source operation is performed. The land is read. At this time as well, since R10 of the source operand of the instruction (3) is rewritten to R32, R32 in the name change register 8 is changed.
The data is read from.

Further, at times 9, 10 and 11, each stage of (3) instruction execution / address calculation, memory access and register write is performed and completed.

The operation of the register number changing device in the information processing device under pipeline control has been described above, but the present invention is also applicable to an information processing device in which register hazards may occur due to sharing of registers. .

[0039]

As described above, according to the register number changing device of the present invention, the contents of the instruction to be issued at the time of instruction decoding are changed as in the prior art, and mapping is performed in the register. Instead, register conflict can be resolved. Therefore, it is possible to reduce the instruction decoding time and the circuit amount. Therefore, the present invention can improve the performance of the information processing apparatus.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus including a register number changing device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an example of an instruction sequence.

FIG. 3 is a diagram showing an example of a pipeline stage of an information processing apparatus.

FIG. 4 is a timing chart when processing the instruction sequence shown in FIG.

FIG. 5 is a block diagram of a conventional information processing apparatus.

FIG. 6 is a block diagram of a register change table in a conventional information processing apparatus.

FIG. 7 is a timing chart when the instruction sequence shown in FIG. 2 is processed by a register renaming method.

FIG. 8 is a configuration diagram showing an example of a register file and a name change register of the information processing apparatus according to the present invention.

FIG. 9 is a configuration diagram of a register queue of a name change register control unit of the register number change device according to the present invention.

[Explanation of symbols]

 1, 10 ... Instruction buffer 2, 21 ... Instruction selection unit 3, 23 ... Execution unit 4, 24 ... Register file 5, 22 ... Register conflict detection unit 25 ... Register change table 6 ... Register number changing device 7 ... Register number Change control unit 8 ... Name change register 9 ... Name change register control unit

Claims (1)

[Claims] 1. An information processing apparatus having a register conflict detection function for holding a plurality of instructions and detecting register conflict in the plurality of instructions, and a preceding control function for starting execution from an instruction in which register conflict does not occur. In the above, there is a register conflict with a register for change provided separately from a register file having a register specified by the register number of the instruction, an unused register number storage means for holding an unused register number in the register for change, A register number changing device for changing the register number of the instruction in which the conflict has occurred to the unused register number stored in the unused register number storing means when detected. .