JP3017866B2 - Interrupt processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method in a pipeline type computer for processing a branch instruction having a delay slot.

[0002]

2. Description of the Related Art In a pipeline computer, when a branch instruction is processed in a pipeline, a subsequent instruction is taken into the pipeline before execution of the branch unless a branch is performed in the first stage of the pipeline. Hazard occurs in pipeline.

As a method of reducing the pipeline hazard, an instruction field called a delay slot is provided after the branch instruction, and the instruction placed in the delay slot is executed regardless of the presence or absence of the branch by the preceding branch instruction. It has been known. In this way, only instructions that can be executed independently of the branch will be placed in the delay slot. Therefore, if there is no instruction unrelated to the branch, the NOP (no operation) instruction is designated.

[0004] As an example of the delay slot of the branch instruction, the pipeline is composed of an instruction fetch stage (F stage).
And instruction decode and branch processing stages (D stage)
, An operation stage (E stage), and a write-back (write result) stage (W stage).
FIG. 4 shows a case where the delay slot is one stage (because the branch processing is performed in the second D stage).

As shown in FIG. 4, the conventional branch instruction (B)
An interrupt is prohibited between the delay slot and the delay slot (S). Also, unlike the example of FIG. 4, when a plurality of stages of delay slots are provided, interrupts between the delay slots are also prohibited. This is because the branch destination address of the preceding branch instruction is lost due to the occurrence of an interrupt from the delay slot, and when returning to the delay slot, the branch destination instruction cannot be executed.

For this reason, conventionally, no instruction which may cause an interrupt, such as a load instruction or a store instruction, is placed in a delay slot, and a branch instruction and a delay slot are not placed over a page boundary of a virtual address. Further, processing such as not inserting an asynchronous interrupt between the branch instruction and the delay slot has been performed. Note that an interrupt may be generated by a load instruction, a store instruction, or the like because an address conversion interrupt may be generated by operand address generation.

[0007]

As described above, conventionally, when an interrupt from a delay slot causes the branch destination address of a preceding branch instruction to be lost and the operation returns to the delay slot, the branch destination instruction cannot be executed. In order to prevent this, an instruction such as a load / store instruction which may cause an interrupt cannot be placed in a delay slot of a branch instruction. For this reason, there is a problem that the instructions that can be placed in the delay slot are limited, and the delay slot cannot be used effectively. Further, for the same reason, the delay slot cannot be located at the page boundary of the virtual address, so that there is a problem that the performance is deteriorated when the branch instruction is frequently used near the page boundary.

The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible for a branch instruction having a delay slot to enable an interrupt from within the delay slot and return to an interrupt to the delay slot. An object of the present invention is to provide an interrupt processing method capable of processing instructions at a high speed by eliminating the restrictions on the instructions that can be placed in the delay slot and effectively using the delay slot.

[0009]

SUMMARY OF THE INVENTION The present invention provides a method for decoding instructions.
An instruction decoding device (12) for controlling the code;
Whether the branch instruction is decoded by the code unit (12)
When a branch address (15) indicating the branch destination is generated from
And a first control signal (16) delayed by one cycle therefrom.
Address generating device (13) for generating
Address at the last stage of the interrupt
(18) and an interrupt signal (19), and
Generates the second control signal (20) one cycle behind
Interrupt detection device (17), and the branch address (1)
5) Or, use the interrupt address (18) as the branch destination address.
First branch destination address register (23) to hold
The instruction location of the decode stage.
Select the next instruction location that has been incremented, and
The first or second control signal (16 or 20) is output
The first branch destination address register (23)
Selector (25) for selecting the output of
The selected output of (25) is transferred to the instruction
1st location register held as application
(26) and the output of this location register (26)
Are sequentially stored according to the pipeline cycle.
The second number of stages corresponding to each stage following the
Of the location registers (27, 28)
1 outputs the output of the branch destination address register (23) to the pipeline.
Decode stage that holds sequentially according to the in-cycle
The second branch destination address of the number of stages corresponding to each stage following
A row of dress registers (31, 32) and the first control
The state of the signal (16) is sequentially changed according to the pipeline cycle.
Next hold, in each stage following the decode stage
A row of status registers (33, 34) of the corresponding number of stages
In the column of the second location register (27, 28),
Output of the final stage register (28) to the return destination from interrupt processing
Is held in accordance with the interrupt signal (19).
Return address register (30)
Last stage register of the column of the foremost address register (31, 32)
The output of the master (32) is output to the delay
As the branch destination address of the branch instruction preceding the extension slot
Third branch destination held in response to the interrupt signal (19)
The address register (29) and the status register (3
The final stage register of the column of 3,34) interrupt the output of the (34)
Indicates whether the return from the process is within the delay slot
Retained as identification information according to the interrupt signal (19).
And an identification information register (35) that performs
When returning from the interrupt processing , the address generation device (13) determines whether or not the return destination is within the delay slot based on the identification information held in the identification information register (35) . If above, return address register
Address (30) is the branch destination address
Output as (15), and in the subsequent cycle
Stored in the third branch destination address register (29).
If the address is not within the delay slot, only the address held in the return address register (30) is used as the branch address (15).
Is output .

[0010]

In the above configuration, the instruction decoding device (1
2) the branch instruction having the delay slot is decoded
As a result, the branch address is generated from the branch address generator (13).
When the address (15) is generated, the branch address (15)
In the next cycle, the branch address generator (13)
According to the first control signal (16) output from the
First branch destination address register (23) as address
Is held. At this time, the first location register
In (26), the instruction is executed in the delay slot of the branch instruction.
Instruction location (that is, the location next to the branch instruction)
Is maintained. The first location register (2
Contents of 6) (location of instruction in delay slot)
Is synchronized with the pipeline cycle in the second location
Are sequentially moved to the row of the option register (27, 28).
You. At the same time, the first branch destination address register (23)
Contents (branch destination address) synchronized with pipeline cycle
Are sequentially moved to the columns of the registers (26, 27) at the subsequent stage.
And the second branch destination address register (31, 3
It is also moved to the column of 2) in order. In addition, the above branch destination address
Control signal generated one cycle later than the
First control signal (1) corresponding to the branch destination address
The state of 6) is the first branch destination address register (23)
Of the status register (3
(3, 34). Therefore, the delay
The location of the instruction in the lot is the second location
Register (27, 28)
At the stage moved to 8), the life in the delay slot
When the decree has advanced to the final stage of the pipeline,
The branch destination address of the branch instruction preceding the delay slot is
In the column of the second branch destination address register (31, 32),
The final stage register (32) stores the address corresponding to the branch destination address.
The state of the first control signal (16) is
In the last stage register (34) of the column of (3, 34), respectively,
Be moved. The interrupt detection device uses an interrupt
The stage prior to the final pipeline stage
At the end of the instruction in the delay slot.
Execution of the instruction stearyl over di preceding spline stage
When the occurrence of an interrupt is detected, the next pipeline stage
Page, that is, the interrupt address in the last pipeline stage
And generate an interrupt signal. This allows the interrupt address
According to the interrupt processing instruction sequence starting with the instruction specified by
The interrupt processing is started. At this time, the second location
Register (27, 28)
8) shows the location of the instruction in the delay slot
Last stage of column of branch destination address register (31, 32)
The branch preceding the delay slot is stored in the register (32).
The branch destination address of the instruction is the status register (33, 34)
Is stored in the last register (34) of the column
The state of the first control signal (16) corresponding to
And these are synchronized with the above interrupt signal,
Return address register (30), third branch address
Register (29), identification information register (35)
Is done. In the branch address generation device (13), when returning from the interrupt processing, first, the identification information register (35)
It is determined whether or not the return destination is within the delay slot based on the identification information stored in the delay slot.

If the address is within the delay slot as in the above example , the branch address generator (13)
Branch the address held in the address register (30)
Output as the destination address (15), and
In the third branch destination address register (29).
The output address is output as the branch destination address. This
By Les, a branch to the first return address of the instruction, scold
Later, it is possible to branch to the instruction at the branch destination address . As described above, if the return destination from the interrupt processing is the delay slot of the branch instruction, it is possible to branch to the branch destination of the preceding branch instruction after executing the instruction in the delay slot.

On the other hand, if the return destination is not within the delay slot, the branch address generator (13)
Only the address held in the address register (30).
Output as the branch destination address (15). This allows
Only the branch to the instruction at the return address is performed, and the instruction sequence starting from that instruction is executed.

[0013]

FIG. 1 is a block diagram of a main part showing an embodiment of a pipeline type computer to which the present invention is applied. In this embodiment, the pipeline has a four-stage configuration of an F stage, a D stage, an E stage, and a W stage, and the branch processing is performed at the D stage. The number of stages of the delay slot is assumed to be one because branch processing is performed in the D stage.

In FIG. 1, reference numeral 10 denotes a memory for storing various programs, data, and the like, and reference numeral 11 denotes a memory control device that controls access to the memory 10 and the like. The memory control device 11 sequentially fetches instructions from the memory 10 while incrementing the memory address, unless there is a branch request or an interrupt request.
To supply. When there is a branch request or an interrupt request, the memory control device 11 starts fetching an instruction from a memory address indicated by a branch address or an interrupt address.

Reference numeral 12 denotes an instruction decoding device for decoding an instruction supplied from the memory control device 11, and reference numeral 13 denotes a branch address generation device. This branch address generation device 13
Generates and outputs a branch signal 14 and a branch address 15 which become true when a branch is taken from a branch instruction decoded by the instruction decoding device 12. The branch address generator 13 also generates a control signal 16 which becomes true one cycle later than the branch signal 14. The control signal 16 indicates that the instruction currently in the D stage is the instruction in the delay slot (the instruction next to the branch instruction), and controls the fetching of the branch destination address into the location register 26 of the D stage described later. Used to do.

Reference numeral 17 denotes an interrupt detecting device for detecting occurrence of an interrupt. The interrupt detector 17 generates an interrupt address 18 and an interrupt signal 19 when an interrupt is detected.
The interrupt detecting device 17 also generates a control signal 20 which is obtained by delaying the interrupt signal 19 by one cycle. This control signal 2
0 is used to control the fetching of the branch destination address (interrupt address) into the location register 26 of the D stage, similarly to the control signal 16 described above.

An OR circuit 21 performs an OR operation on the branch signal 14 from the branch address generator 13 and the interrupt signal 19 from the branch address generator 13 and outputs the OR signal to the memory controller 11 as a branch request. , 22 are selectors. The selector 22 receives the branch address 15 from the branch address generator 13 or the interrupt detector 17
, And selects one of the interrupt addresses 18 according to the interrupt signal 19 and outputs the selected address to the memory control device 11 as a branch destination address.

Reference numeral 23 denotes an address register (B-ADRS) for holding a branch destination address selected and output to the memory control device 11 by the selector 22. Reference numeral 24 denotes a control signal 16 from the branch address generation device 13 and an interrupt detection device 17. And an OR circuit 25 for ORing the control signal 20 from the control circuit 20 and a selector 25. The selector 25 outputs one of the next instruction location, which is an increment of the current instruction location indicated by the location register 26 described later, and the output (branch destination address) of the address register 23 to O.
The selection is made according to the output signal of the R circuit 24.

26 is a location register (D-LOC) for holding the output of the selector 25 as an instruction location of the D stage, and 27 is a location register 2
A location register (E-LOC) 28 for holding the output of 6 as an instruction location of the E stage, and a location register (W-LOC) 28 for holding the output of the location register 27 as the instruction location of the W stage.

Reference numeral 29 denotes an address register (BA) to be described later.
DRS2) is an address register (B-ADRS3) for holding the branch destination address indicated by 32 in response to the interrupt signal 19 from the interrupt detection device 17. When the return destination from the interrupt processing is in the delay slot, this register 29 holds an address that must branch after execution of the instruction in the delay slot (branch destination address of a branch instruction preceding the delay slot). It has become. 3
Reference numeral 0 denotes an address register (RTN-ADRS) for holding the output of the location register 28 as a return address from the interrupt processing in accordance with the interrupt signal 19.

31 is an address register (B-ADRS)
An address register (B-ADRS1) for holding the contents of 23 one cycle later, and an address register (B-ADRS3) 32 for holding the contents of the address register (B-ADRS1) 31 one cycle later. .

Reference numeral 33 denotes a register (ES) for holding the state of the control signal 16, and indicates whether or not the instruction at the E stage is a delay slot for a branch instruction. Reference numeral 34 denotes a register (WS) for holding the contents of the register (ES) 33 with a delay of one cycle, and indicates whether or not the instruction at the W stage is a delay slot for a branch instruction. Reference numeral 35 denotes a register (R-S) for holding the contents of the register (WS) 34 in response to the interrupt signal 19 from the interrupt detector 17.
S), and indicates whether the return destination from the interrupt processing is a delay slot.

Next, the operation of the configuration shown in FIG. 1 will be described with reference to a timing chart shown in FIG. 2, taking an example in which an interrupt occurs in a delay slot of a branch instruction. The timing chart of FIG. 2 shows the operation of the pipeline when an address translation interrupt occurs in the generation of the operand address of the load instruction L executed in the delay slot of the branch instruction B. In the figure, N1 is a branch instruction specified by the branch instruction B, N2 and N3 are instructions following the branch instruction N1, I1,
Are instructions for interrupt processing generated by the load instruction L. In the present embodiment, it is assumed that an operand address is generated in the D stage, an address conversion interrupt is detected (determination of an interrupt by the interrupt detection device 17) in the E stage, and an interrupt process is performed in the W stage.

If there is no instruction branch or interrupt, the memory controller 11 fetches the instruction from the memory 10 while incrementing the memory address, and
Supply to As a result, as shown in the example of FIG. 2, the branch instruction B is first fetched from the memory 10 and then the load instruction L placed in the delay slot of the branch instruction B (F stage of the cycles T1 and T2). It is assumed that the data is supplied to the decoding device 12.

The instruction decoding device 12 decodes the instruction supplied from the memory control device 11. Thereby, in the case of the branch instruction B, the branch address generation device 1
3, a determination is made as to whether the branch is taken or not. When the branch is taken, a valid branch signal 14 and a branch address 15 indicating the storage location of the branch destination instruction N1 are generated and output by the branch address generator 13 (D in cycle T2). stage). In the next cycle (T3), the control signal 16 which is a signal obtained by transmitting the branch signal 14 for one cycle is output from the branch address generation device 13.

The branch address 15 generated by the branch address generator 13 is supplied to the 0-side input of the selector 22. As long as the interrupt signal 19 from the interrupt detection device 17 is not true, the selector 22 selects the branch address 15 which is the 0-side input, and outputs it to the memory control device 11 as a branch destination address. At this time, the output of the OR circuit 21 is a valid branch signal 1 from the branch address generator 13.
4 is true, and a branch request is input to the memory control device 11.

Thus, the memory control device 11 fetches the branch destination instruction N1 specified by the branch address 15 generated in the D stage of the branch instruction B (cycle T2) from the memory 10 (F stage in cycle T3), and The data is supplied to the decoding device 12.

When the load instruction L in the delay slot (of the branch instruction B) is fetched from the memory 10 in the cycle T2, an operand address is generated in the next cycle T3 (D stage). Then, in the next cycle T4 (E stage), the interrupt detection device 17 detects an address conversion interrupt.

If an address translation interrupt occurs and is detected in cycle T4 (E stage), interrupt processing is started in the next cycle T5 (W stage), and the same cycle T5 (W stage) is started. In the stage, an interrupt signal 19 valid and an interrupt address 18 indicating the storage location of the first instruction I1 of the interrupt process are generated and output by the interrupt detection device 17. In the next cycle (T6),
A control signal 20, which is a signal obtained by transmitting the interrupt signal 19 for one cycle, is output from the branch address generation device 13.

The interrupt address 18 generated by the interrupt detector 17 is supplied to one input of the selector 22. When an interrupt is detected by the interrupt detector 17, the selector 22 selects an interrupt address 18, which is one input of the selector, according to a valid interrupt signal 19 from the interrupt detector 17, and selects the interrupt address as a branch destination address. Output to the memory control device 11. At this time, the output of the OR circuit 21 is a valid interrupt signal 1 from the interrupt detection device 17.
9 is true, and a branch request is input to the memory control device 11.

Thus, the memory control device 11 transmits the interrupt processing instruction sequence I1, I2, I3... Starting from the interrupt processing instruction I1 specified by the interrupt address 18 generated in the W stage (cycle T5) of the load instruction L to the next. After the cycle T6, the data is sequentially fetched from the memory 10 and supplied to the instruction decoding device 12. As a result, an interrupt process is started.

In the present embodiment, the location is controlled as described below in order to know the location of the instruction that caused the interrupt. Further, since the branch address is determined in the D stage as described above, the location control is also performed in the D stage.

First, the branch destination address (branch address or interrupt address) selected by the selector 22 is held in the address register (B-ADRS) 23, and is delayed by one cycle from the cycle passed to the memory controller 11 by the branch request. You. The branch destination address held in the address register 23 is supplied to one input of the selector 25. The 0-side input of the selector 25 has the next instruction location obtained by incrementing the current D-stage instruction location indicated by the location register (D-LOC) 26 (for example, if the current D-stage is a branch instruction B, , The location of load instruction L in the delay slot of instruction B).

The selector 25 performs a selecting operation in accordance with the output of the OR circuit 24. If the output of the OR circuit 24 is false, the 0 side (next instruction location); if it is true, the 1 side (branch destination address). Select The output of the OR circuit 24 is false when the control signal 16 from the branch address generator 13 and the control signal 20 from the interrupt detector 17 are both false, that is, when neither branch nor interrupt occurs. In that case, the instruction location next to the instruction location of the current D stage is selected. On the contrary,
When a branch or interrupt occurs, the control signal 16 or 20 becomes true and the output of the OR circuit 24 becomes true,
The branch destination address held in the address register (B-ADRS) 23 is selected. The next instruction location or branch destination address selected by the selector 25 is held in a location register (D-LOC) 26.

In this embodiment, the branch address is determined at the D stage, and the delay slot of the branch instruction is one stage. Thus, the instruction location of the D stage will change to the location of the branch destination two cycles after the branch instruction (ie, in the next cycle of the delay slot). Therefore, in this embodiment, the branch destination address selectively output from the selector 22 to the memory control device 11 as described above is supplied to one side of the selector 25 while being delayed by one cycle by being held in the address register 23. Branch signal 1
4, the control signals 16 and 20 obtained by delaying the interrupt signal 19 by one cycle are input to the OR circuit 24 so that the contents of the location register 26 are correctly updated to the branch destination location two cycles after the branch instruction. .

As a result, the location register (D-
LOC) 26 indicates the location of the branch instruction B in cycle T2, and in the next cycle T3, the next instruction location obtained by incrementing the instruction location of branch instruction B, that is, loading the delay slot of branch instruction B In the next cycle T4, the instruction L is updated to indicate the location of the instruction L, and to indicate the branch destination address (branch address 15) to the branch destination instruction N1 generated in the D stage of the branch instruction B.

The detection of an interrupt (in the interrupt detecting device 17) is performed in the W stage as described above. For this reason, an instruction location is required in the W stage.
Therefore, in this embodiment, the location register (D-LO
C) On the output side of 26, a location register (E-LO
C) 27 and location register (W-LOC) 2
8 are connected in multiple stages, and the location is pipelined to the W stage in synchronization with the instruction. As a result, the content of the location register (D-LOC) 26 is delayed by two cycles to the location register (W-LOC).
C) 28, and the register (W-LOC) 28
The cycle T4 indicates the location of the branch instruction B, the next cycle T5 indicates the location of the load instruction L, and the next cycle T6 indicates the location of the branch destination instruction N1.

In this embodiment, when an interrupt occurs, it is determined whether or not the instruction that caused the interrupt is in the delay slot, and therefore, whether or not the return from the interrupt processing is in the delay slot. Control signal 16 (branch signal 14) output from the branch address generator 13
(E-S) 33 and a register (W-
S) 34 is provided, and the control signal 16 is also operated in a pipeline operation in synchronization with the instruction until the W stage (when an interrupt is detected).

Further, in this embodiment, the address register (B
-ADRS) 23, an address register (B-ADRS1) 31 and an address register (B-ADRS2) 32 having a two-stage connection structure are provided on the output side.
Up to the stage, pipeline operation is performed in synchronization with the instruction, and the operation is held until the interrupt is detected.

As described above, when the branch signal 14 and the branch address 15 indicating the instruction N1 at the branch destination are output from the branch address generator 13 at the D stage (cycle T2) of the branch instruction B, the following is performed. In the cycle T3, the control signal 16 obtained by delaying the branch signal 14 by one cycle is output.
The state of the control signal 16 is held in the register (ES) 33 in synchronization with the pipeline cycle. Similarly,
The output of the register (ES) 33 is held in the register (WS) 34 at the next stage in synchronization with the pipeline cycle. Therefore, the register (E-
S) 33 becomes "1", and in the next cycle T5, the contents of the register (WS) 34 become "1".

The branch address 15 indicating the branch destination instruction N1 is stored in the address register (B) in cycle T3.
-ADRS) 23. The contents of the address register (B-ADRS) 23 (the branch destination address to the branch destination instruction N1) are transferred to the address register (B-ADRS1) 31 in the next cycle T4, and further in the next cycle T
At 5, the data is moved to the address register (B-ADRS2) 32.

Here, as described above, an address conversion interrupt occurs at the D stage (cycle T3) of the load instruction L, and the effective interrupt signal 19 and the start of the interrupt processing at the W stage (cycle T5) of the instruction L The interrupt address 18 indicating the storage location of the instruction I1 and the interrupt detection device 17
Is assumed to be generated and output. In this case, the interrupt address 18 is selected as the branch destination address by the selector 22 and output to the memory control device 11. Also, O
The output of the R circuit 21 becomes true, and a branch request is input to the memory control device 11. As a result, after the cycle T6, the interrupt processing instruction sequences I1, I2, I3,... Are fetched from the memory 10, and the interrupt processing is performed.

When a valid interrupt signal 19 is output from the interrupt detector 17 in the cycle T5 (W stage of the load instruction L), the instruction location indicated by the location register (W-LOC) 28 at that time, that is, the interrupt The location of the load instruction L in the W stage that has caused the (address conversion interrupt) is held in the address register (RTN-ADRS) 30 in cycle T6 as the address of the instruction to return from the interrupt processing.

At the same time, the register (W-
The contents (“1”) of S) 34 are held in the register (RS) 35. At this time, the content (“1”) of the register (RS) 35 matches the state of the control signal 16 output from the branch address generator 13 in the cycle T3, and the return destination from the interrupt processing branches. Indicates a delay slot of an instruction (here, a branch instruction B).

The contents of the address register (B-ADRS2) 32 in the cycle T5 (the branch destination address of the branch instruction B preceding the delay slot) are stored in the cycle T6.
At the address register (B-ADRS3) 29.

Next, the operation in the case of returning from the above interrupt processing will be described with reference to the timing chart of FIG. 3 in addition to the timing chart of FIG. In FIG. 3, B1 is a return destination from the interrupt processing (load instruction L).
The branch instruction B2 is a branch instruction to the instruction to be executed next to the load instruction L. L is a return instruction from the interrupt processing (a load instruction causing an interrupt), and N1 is an instruction which is a branch destination of the branch instruction B shown in FIG.

When returning from the interrupt processing, first, a branch instruction for branching according to the contents of the register (RS) 35 is executed. The D stage of this branch instruction (cycle T
10), the contents of the register (RS) 35 are checked by the branch address generator 13 and if it is indicated that the operation is to return to the delay slot as in the present embodiment, the cycle T11 is executed. Hereinafter, the branch instruction B described below
1, B2 are executed.

First, in the case of returning to the delay slot, the branch destination is set to the address register (R
TN-ADRS) Branch instruction B at the address indicated by 30
1, that is, the branch instruction B1 having the branch destination as the return destination (load instruction L) from the interrupt processing is fetched from the memory 10, and the D stage of the branch instruction B1 is performed in the next cycle T12. In the cycle T12, the branch destination is the branch instruction B2 (placed in the delay slot of the branch instruction B1), that is, the return instruction (the load instruction L in the delay slot) set to the address indicated by the address register (B-ADRS3) 29. The branch instruction B2 to the branch destination instruction (N1) of the preceding branch instruction (B) is fetched, and the next cycle T1
At 3, the D stage of the branch instruction B2 is performed.

In the D stage (cycle T12) of the branch instruction B1, the content held in the address register (RTN-ADRS) 30 is fetched by the branch address generator 13, and the address indicated by the register (RTN-ADRS) 30, that is, the address indicated by the register (RTN-ADRS) 30, The address of the return instruction (load instruction L) is output as the branch address 15. This branch address 1
5 is selected by the selector 22 and the memory controller 11
Supplied to At the same time, a valid branch signal 14 is output, and a branch request is input to the memory control device 11.

As a result, the memory controller 11 fetches from the memory 10 the load instruction L specified by the branch address 15 (the address of the return load instruction L) generated in the D stage (cycle T12) of the branch instruction B1. (F stage of cycle T13), and supplies it to the instruction decoding device 12. As a result, from the next cycle T14, the processing after the D stage of the load instruction L that caused the interrupt in the delay slot of the branch instruction B is performed.

Next, in the D stage (cycle T13) of the branch instruction B2, the contents held in the address register (B-ADRS3) 29 are fetched by the branch address generator 13 and indicated by the register (B-ADRS3) 29. The address, that is, the address of the branch instruction (N1) of the branch instruction (B) preceding the return instruction (load instruction L) is output as the branch address 15. The branch address 15 is selected by the selector 22 and supplied to the memory control device 11. At the same time, a valid branch signal 14 is output, and a branch request is input to the memory control device 11.

As a result, the memory control device 11 specifies the instruction N1 (the branch address of the branch instruction B preceding the return instruction L) generated at the D stage (cycle T13) of the branch instruction B2. The branch destination instruction of the branch instruction B preceding the delay slot) is stored in the memory 10
(F stage of cycle T14) and supplies it to the instruction decoding device 12. As a result, the next cycle T
From 15 onward, the processing after the D stage of the instruction N1 at the branch destination of the branch instruction B is performed.

As described above, in the present embodiment, when returning from the interrupt processing, first, the contents of the register (RS) 35 are examined, and if it is indicated that the operation is to return to the delay slot, it is indicated. , Address register (RTN-ADR
S) Instruction at return address indicated by 30 (load instruction L)
The branch instruction B1 designating the branch to the branch instruction B1 is executed, and the address register (B
-ADRS3) The branch instruction B2 that specifies the branch to the instruction indicated by 29 (the branch instruction N1 of the branch instruction B preceding the return instruction L) is executed.

By executing the above branch instructions B1 and B2,
When the return destination is the delay slot of the branch instruction (B) as in this embodiment, first, the instruction (load instruction L) that generated the interrupt in the delay slot is executed, and the execution of the instruction (L) is executed. Later, the branch instruction (B) preceding the delay slot branches to the branch destination instruction (N1), and the return to the delay slot becomes possible.

On the other hand, if the return destination is not the delay slot of the branch instruction, only the branch instruction B1 is fetched, and a branch to the return instruction indicated by the address register (RTN-ADRS) 30 is performed. Return. In the normal processing after the return, the instruction sequence following the return instruction is executed.

[0056]

As described in detail above, according to the present invention,
At the start of interrupt processing, while holding the address of the return destination from the interrupt processing and identification information indicating whether the return destination from the interrupt processing is within the delay slot, the return destination from the interrupt processing is branched. If the instruction is a delay slot of an instruction, the branch destination address of the branch instruction preceding this delay slot is held, and when returning from interrupt processing, the return destination is the delay slot based on the held identification information. If the return is to the delay slot, first branch to the return address, execute the instruction at the return destination, and then execute the branch instruction preceding the instruction at the return destination. Branching to the branch destination address, and if returning from outside the delay slot, branching to only the return destination address is used.
Interruption of the branch instruction from within the delay slot and return to the delay slot can be performed.

Therefore, there is no restriction on the instructions that can be placed in the delay slot, and the delay slot can be used effectively. Further, the branch instruction and the delay slot can be placed over the page of the virtual address, and the performance is not reduced even if the branch instruction is used near the page boundary.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part showing an embodiment of a pipeline type computer to which the present invention is applied.

FIG. 2 is a timing chart for explaining an operation when an interrupt occurs in a delay slot of a branch instruction.

FIG. 3 is a timing chart for explaining an operation when returning from interrupt processing.

FIG. 4 is a timing chart for explaining delay slots of branch instructions in the pipeline computer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Memory, 11 ... Memory control device, 12 ... Instruction decoding device, 13 ... Branch address generation device, 14 ... Branch signal, 15 ... Branch address, 16, 20 ... Control signal, 17
... interrupt detection device, 18 ... interrupt address, 19 ... interrupt signal, 22, 25 ... selector, 23 ... address register (B-ADRS), 26 ... location register (D
-LOC), 27 ... Location register (E-LO)
C), 28 ... location register (W-LOC), 2
9 ... Address register (B-ADRS3, second address holding means), 30 ... Address register (RTN-AD
RS, first address holding means), 31 ... address register (B-ADRS1), 32 ... address register (B
-ADRS2), 33 ... register (ES), 34 ... register (WS), 35 ... register (RS, identification information holding means).

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/46 G06F 9/38 JICST file (JOIS) CSDB (Japan Patent Office)

Claims (1)

(57) [Claims] 1. A branch instruction having a delay slotDecoding
In the pipeline including the stageProcessMeterCalculatorIn
Interrupt processing method,An instruction decoding device for decoding instructions; Branch instruction decoded by the instruction decoding device
Generates a branch address indicating the branch destination from
A branch address for generating a first control signal one cycle later than
A dress generation device; Interrupts due to interrupts generated at the last stage of the pipeline
Generates address and interrupt signals, and
Interrupt detection device for generating second control signal delayed in cycle
And The branch address or interrupt address is stored in the branch destination address.
A first branch destination address register held as a Normally, the instruction location of the decode stage is incremented.
To the next instruction location
Alternatively, when the second control signal is output, the first
A selector for selecting the output of the forehead address register; The selected output of the selector is sent to a new decode stage.
1st location cash register to keep as command location
And Pipelining the output of the first location register
Hold sequentially according to cycle, after decode stage
A second location with the number of stages corresponding to each subsequent stage
A row of registers; Pipeline the output of the first branch destination address register
To the decode stage, which holds the data sequentially according to the cycle
Second branch destination address of the number of stages corresponding to each subsequent stage
And a row of The state of the first control signal is changed in response to a pipeline cycle.
Each stage following the decode stage
Rows of status registers corresponding to the number of stages, Last stage register of the column of the second location register
Output Return address from interrupt processingAs the above
According to the interrupt signalHoldReturn address register
When,Last stage register of the column of the second branch destination address register
Output Return destination from interrupt processingBecomesDelay slot
Destination address of the branch instruction preceding theAs above
Depending on theHoldThird branch destination address register
TaWhen,The output of the last stage register in the column of the status register Said percent
Whether the return destination from the embedding process is within the delay slot
Identification informationAccording to the interrupt signalKnowledge to hold
Other informationregisterWithThe branch address generation device includes: Return from interrupt processing
In some cases, the identification informationregisterIdentification information stored in
From the information, determine whether the return destination is within the delay slot,
Within the delay slotReturn address registerTo
HeldOutput address as branch destination address
And the third branch destination address in a subsequent cycle.
registerIs held inThe address as the branch destination address
OutputIf not in the delay slotReturn ad
Less registerIs held inOnly the address
Output as a dressInterrupt processing method characterized by the following:
formula.