JPH06118141A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent lack of an input and output pin number at the time when an inside logic circuit composed of a field programmable gate array, a gate array and the like are divided into a plurality of semiconductor chips. CONSTITUTION:A serial and parallel conversion circuit 5 is provided in the input and output part of an inside logical circuit 2 composed of a field programmable gate array, a gate array and the like. Data transmission with the inside logical circuit 2 divided and formed on a semiconductor chip 1 is performed through the serial and parallel conversion circuit 5 in series, so that an input and output pin is allowed to effectively function as a plurality of input and output pins.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a gate array and a field array.
Programmable gate array
te array) and programmable in-circuit emulators using them.
It is related to effective technology when applied to (mulator).

[0002]

2. Description of the Related Art In a small-quantity, multi-product system or a prototype system, the logic circuit thereof may be created by using a field programmable gate array or a gate array.

Regarding the above-mentioned field programmable gate array, I E E 1991 (“A
large scale FPGA with 10K core cells with CMOS 0.8
μm3-layered Metal Process "H.Muroga et.al., Tos
hiba corporation, 1991, Proceedings of the IEEE 199
1 CUSTUM INTEGRATED CIRCUITS CONFERENCE) and the gate arrays are described in "Hitachi High Speed CMOS Gate Array HG62E Series Design Manual" issued by Hitachi, Ltd. in 1988.

[0004]

A conventional system in which a logic circuit is composed of a field programmable gate array or a gate array is divided into a plurality of semiconductor chips when the scale of the logic circuit becomes large. Must be allocated.

However, when the logic circuit is divided into a plurality of semiconductor chips, the number of input / output signals crossing the division boundary becomes large as compared with the size of each divided circuit, and thus the number of input / output pins becomes insufficient, so that the logic circuit is divided. More semiconductor chips have to be subdivided.

As a result, there is a problem that the system cost is increased due to a decrease in gate utilization efficiency and a decrease in mounting density due to an increase in the number of semiconductor chips, and a system characteristic due to an increase in wiring length and parasitic impedance due to an increase in the number of semiconductor chips. The problem of lowering occurs.

Therefore, an object of the present invention is to provide a technique capable of preventing an insufficient number of input / output pins when a logic circuit is divided into a plurality of semiconductor chips.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, a serial / parallel conversion circuit is provided in the input / output section of the programmable internal logic circuit, and data transmission between the internal logic circuits formed by dividing on a plurality of semiconductor chips is performed via the serial / parallel conversion circuit. Are performed in series.

[0011]

According to the above-mentioned means, the signal output in parallel from the internal logic circuit is converted into the serial signal through the serial-parallel conversion circuit provided in the input / output section of the internal logic circuit, and the serial signal is input to the internal logic circuit. It is possible to transmit a plurality of input / output signals with one input / output pin by converting a serial signal to parallel signals.

That is, since one input / output pin can effectively function as a plurality of input / output pins, the number of input / output pins when the internal logic circuit is divided into a plurality of semiconductor chips and allocated. The shortage can be prevented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic diagram of a main part of a semiconductor chip on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed.

On the main surface of the semiconductor chip 1, an internal logic circuit 2, an input buffer 3 for inputting a data signal to the internal logic circuit 2, and an output buffer 4 for outputting a data signal of the internal logic circuit 2. The serial-parallel conversion circuit 5 is connected between the internal logic circuit 2 and the input buffer 3 and the output buffer 4.

The internal logic circuit 2 is composed of a so-called field programmable gate array in which a user programs mutual wirings between a plurality of logic gates arranged in a matrix and wirings in each logic gate.

A plurality of input / output signal lines S _{1 to} S _N are connected between the input / output section of the internal logic circuit 2 and the parallel input / output terminal of the serial-parallel conversion circuit 5. Further, between the serial input terminal of the serial-parallel conversion circuit 5 and the input buffer 3,
The input line 6 is connected, and the output line 7 is connected between the serial output pin and the output buffer 4.

Reference numeral 8 is an inter-chip signal line, which is commonly connected to the input terminal of the input buffer 3 and the output terminal of the output buffer 4. Reference numeral 9 is a data transfer control circuit, which has a plurality of transfer address lines A ₁ through A _{1 at} its input terminals.
A _M and the transfer clock line 10 are connected, an output enable line 11 connected to the enable terminal of the output buffer 4 at the output terminal, and a serial / parallel conversion connected to the conversion direction control input terminal of the serial / parallel conversion circuit 5. The direction control signal line 12 and the serial / parallel conversion circuit clock line 13 are connected.

The serial-parallel conversion circuit 5 is an internal logic circuit 2
The parallel signal output from is converted to a serial signal and output line 7
The serial signal input from the input line 6 is accumulated and output in parallel to the internal logic circuit 2. These conversion operations are performed in synchronization with the clock signal transmitted from the data transfer control circuit 9 through the serial / parallel conversion circuit clock line 13.

The data transfer control circuit 9 disables the transfer clock line 10 and the output enable line 11 when the transfer address lines A _{1 to} A _M are all chip non-selected (for example, all bits are 0). At this time, all the serial-parallel conversion circuits 5 are in a stopped state, and the internal logic circuit 2 operates normally.

[0020] When the address signals transfer address lines A ₁ to A _M is equal to the address of the semiconductor chip 1, the semiconductor chip 1 is the transmission mode, the data transfer control circuit 9, an internal logic signal to be transmitted to the transfer destination connection The serial-parallel conversion direction control signal line 12 is set to the serial conversion direction with respect to the serial-parallel conversion circuit 5, and the clock signal is output to the serial-parallel conversion circuit clock line 13 according to the clock signal input through the transfer clock line 10. The output enable line 11 is enabled.

[0021] When the address signals transfer address lines A ₁ to A _M is not equal to the address of the semiconductor chip 1, the semiconductor chip 1 is the reception mode, the data transfer control circuit 9
Is the serial-parallel conversion direction control signal line 12 to the serial-parallel conversion circuit 5 to which the internal logic signal to be received from the transfer source is connected.
In the parallel conversion direction, the clock signal is output to the serial-parallel conversion circuit clock line 13 according to the clock signal input through the transfer clock line 10, and the output enable line 11
Is disabled.

FIG. 2 is a configuration diagram of a main part of a programmable in-circuit emulator in which a plurality of (1a to 1n) semiconductor chips 1 shown in FIG. 1 are mounted.

The semiconductor chips 1a to 1n are connected in parallel to the inter-chip signal line 8, the transfer address line A and the transfer clock line 10. The transfer address line A is also connected to the output terminal of the transfer controller 14 and the input terminal of the set number memory 15.

The output signal from the set number memory 15 is transferred through the set number output line 16 to the transfer clock generator 1.
Type in 7. The transfer clock generator 17 is the source of the transfer clock line 10 and is connected to the transfer controller 14 through the transfer clock trigger line 18 and the count end signal line 19.

The operation of the programmable in-circuit emulator will be described with reference to FIGS. 2 and 3.

(Step 0) The transfer controller 14 outputs an all-chip non-selection signal (for example, 0) to the transfer address line A. At this time, each of the semiconductor chips 1a to 1n performs a normal internal logic operation and does not transfer data.

(Step 1) The transfer controller 14 returns to Step 0 if the previous address is equal to the address of the final semiconductor chip (1), otherwise it sets the address to 1.
Only, and output to the transfer address line A. At this time, the set number of pins of the semiconductor chip (1) corresponding to the address is transmitted from the set number memory 15 to the transfer clock generator 17 through the set number output line 16.

As a result, the semiconductor chip (1) at the corresponding address is placed in the reception mode, the other semiconductor chips (1) are placed in the transmission mode, and the internal logic circuit 2 of each of the semiconductor chips 1a to 1n is in the suspended state. Become. At the end of this step, the transfer controller 14 outputs a transfer trigger to the transfer clock generator 17.

(Step 2) When the transfer clock generator 17 outputs the transfer clock, the semiconductor chip (1) in the transmission mode is synchronized with the semiconductor clock (1) in the reception mode in synchronization with the output of the transfer clock.
Data is transmitted in series through the chip signal line 8.
The semiconductor chip (1) in the reception mode converts the data into parallel signals by the serial-parallel conversion circuit 5 shown in FIG. 1 and inputs the parallel signals to the internal logic circuit 2 through the input / output signal lines S _{1 to SN} .

The above step 2 is performed by the transfer clock generator 1
The number of sets in 7 is decremented by 1 and repeated until it reaches 0. When the number of sets reaches 0, the process returns to the beginning of step 1.

As described above, according to this embodiment, by using one input / output pin of each semiconductor chip (1), a plurality of input / output signals are transmitted in series to another semiconductor chip (1). Since one input / output pin can effectively function as a plurality of input / output pins, the number of input / output pins is insufficient when the internal logic circuit 2 is divided and allocated to the plurality of semiconductor chips 1a to 1n. Can be prevented.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above embodiment, the internal logic circuit is composed of the field programmable gate array, but it can be applied to the case of being composed of the gate array.

[0034]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

A serial-parallel conversion circuit is provided in the input / output section of the programmable internal logic circuit, and data transmission between the internal logic circuits formed by dividing the semiconductor chip into a plurality of semiconductor chips is performed serially via the serial-parallel conversion circuit. By doing so, it is possible to prevent an insufficient number of input / output pins when the internal logic circuit is divided into a plurality of semiconductor chips.

[Brief description of drawings]

FIG. 1 is a main part configuration diagram of a semiconductor chip on which a semiconductor integrated circuit device according to an embodiment of the present invention is formed.

2 is a main part configuration diagram of a programmable in-circuit emulator in which a plurality of semiconductor chips shown in FIG. 1 are mounted.

FIG. 3 is a programmable in-circuit circuit shown in FIG.
It is a figure explaining operation | movement of an emulator.

[Explanation of symbols]

1 semiconductor chip 1a to 1n semiconductor chip 2 internal logic circuit 3 input buffer 4 output buffer 5 serial-parallel conversion circuit 6 input line 7 output line 8 inter-chip signal line 9 data transfer control circuit 10 transfer clock line 11 output enable line 12 serial parallel Conversion direction control signal line 13 Serial / parallel conversion circuit clock line 14 Transfer controller 15 Set number memory 16 Set number output line 17 Transfer clock generator 18 Transfer clock trigger line 19 Count end signal line A Transfer address line A ₁ ~ A _M Transfer address line S _{1 to} S _{N I} / O signal line

Claims (4)

[Claims] 1. A serial signal input to the internal logic circuit by converting a parallel signal output from the internal logic circuit into a serial signal to an input / output unit of a programmable internal logic circuit formed on a semiconductor chip. A serial-to-parallel conversion circuit for converting a parallel signal into a parallel signal is provided. 2. The semiconductor integrated circuit device according to claim 1, wherein the internal logic circuit is a gate array or a field programmable gate array. 3. A plurality of semiconductor chips according to claim 1, wherein a serial / parallel conversion circuit is provided in an input / output portion of a programmable internal logic circuit, and data between the internal logic circuits formed on each semiconductor chip. A semiconductor integrated circuit device characterized in that transmission is performed in series. 4. The semiconductor integrated circuit device according to claim 3, which is a programmable in-circuit emulator.