JPH0588972A - Peripheral ic - Google Patents

Abstract

PURPOSE:To enable continuously to make access to peripheral IC access time or cycle time without managing it by a user. CONSTITUTION:Inherent access time included in a peripheral IC is managed by an ACK control circuit 13 provided in an element, and when an access is started, the time management is automatically started, and after the lapse of an inherent time, an access time signal/ACK is outputted to inform the time lapse to a user. At the end of the access, the time management is automatically started, and even when the succeeding access is started, the start of the access to the element is automatically inhibited until the inherent cycle time has elapsed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral IC which is an IC for peripheral devices.

[0002]

2. Description of the Related Art When a peripheral IC is used, the access time and cycle time peculiar to the IC are always specified. Therefore, the conventional method is as follows. <In case of access time> In order to satisfy the time specified by the peripheral IC, the ready signal (ACK signal) to the CPU is delayed by using a counter or the like.

<Case of Cycle Time> The CPU waits the time defined by the IC to gain time, and starts the next access. (For example, insert before the NOP processing or the delay routine is accessed.)

First, examples of access times are shown in FIGS. This is an example of the case where two peripheral ICs are used. In FIG. 7, CPUCLK is a CPU clock, / CS1 and / CS2 are chip select signals of each IC, / RD is a read signal, / ACK1 and / ACK2 are access time signals which are ready signals of each IC, and Data.
1 and Data2 are data of each IC. And Tac
1, Tac2 is the access time of each IC. In this specification, "/" means a signal of negative logic or low active, and is shown with an overline in the figure.

FIG. 8 shows a concrete circuit example for making the access times Tac1 and Tac2. In this example, the counter 1 is used to create this timing. That is, the counter 1 counts the CPU clock CPUCLK when the input read signal / RD becomes "L", and when the count value becomes "2", the output Qa becomes "H" and the count value becomes "3". Then, the output Qc is set to "H".

On the other hand, address data is input to the decoder 2 and a chip select signal / C is input according to the address.
One of S1 and / CS2 is activated and inverted by inverters 3 and 4, respectively, and the signal CS1 and the output Qa of the counter 1 are supplied to the NAND circuit 5, and the signal CS2 and the output Qc of the counter 1 are supplied to the NAND circuit 6. Enter each. The outputs of the NAND circuits 5 and 6 are set as access time signals / ACK1 and / ACT2, respectively, and the output of the NAND circuits 5 and 6 is sent to a CPU via a NOR circuit (equivalent to AND circuit) 7 having both inversion inputs.
Send to 8.

In this example, the CPU 8 has the access time signal ACK at the fall of the CPU clock CPUCLK.
When 1 or ACK2 is detected, the cycle ends. Therefore, each CPU cycle ends in the C3 and C4 cycles.

[0008]

As described above, in order to access the conventional peripheral IC, not only the access time control circuit as shown in FIG. 8 is required,
Each time the number of elements (peripheral ICs) increases, it is necessary to manage the timing, which causes a problem of increasing the number of circuits.

FIG. 9 shows an example of cycle timing. In this way, the read / write cycle time trv is defined for each IC. Therefore, when continuously accessing the peripheral IC, the CPU needs to wait for the time, so that the NOP process or the wait routine program is put in each access to manage the time.

The present invention has been made in view of the above points, and enables continuous access without the user managing the above access time and cycle time.
The purpose is to prevent an increase in the number of circuits for the user, reduce the load on the CPU, and reduce the total cost.

[0011]

In order to achieve the above-mentioned object, the peripheral IC according to the present invention has means for managing the unique access time of the element by the element itself.
When the access is started, the time management is automatically started, and after a specific time has passed, a signal for notifying the user is output. Also, when access is completed, time management will start automatically,
It is also provided with means for automatically inhibiting access to the device until its own cycle time has passed, even if the next access is started.

[0012]

According to the present invention, the peripheral IC element itself manages time, and outputs an access time end signal after a specific time has elapsed from the start of access. There is no need for management, the circuit configuration can be simplified, and circuit mistakes can be reduced. Further, since the cycle time is controlled by the element itself, it is not necessary for the user to create a program for time management, and the program capacity can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows a peripheral I according to the present invention.
The block diagram of the principal part of C is shown. This peripheral IC1
0 has a data bus buffer 11 and a read / write control circuit 12 similarly to the conventional peripheral IC, and has a configuration in which an ACK control circuit (access time output circuit) 13 is newly added. Reference numeral 14 is an internal bus, and 15 is a data bus.

A concrete circuit example of the ACK control circuit 13 is shown in FIGS. The access time will be described with these. Figure 2 shows an example circuit in asynchronous mode,
FIG. 3 shows an example of a circuit in the system synchronization mode. In the example of the asynchronous mode shown in FIG. 2, a NAND circuit (OR circuit) having both inverted inputs of the chip select signal / CS and the read signal / RD signal
(Equivalent to a circuit) 16 and delays its output through a simple C / R delay circuit consisting of a resistor R1 and a capacitor C1 and an access time signal / AC via a buffer 17.
Output as K.

In the system synchronization mode example shown in FIG. 3,
CPU clock CPUCLK is input to the peripheral IC element, and chip select signal / CS and read signal / RD
The access time signal / ACK is output in synchronization with the CPU clock by the AND circuit (equivalent to the NOR circuit) 18 of both inversion inputs for inputting the signal and the counter 19.

Such a simple circuit is used as a peripheral IC.
When the element is held in the element and the element is accessed, the access time signal / A is delayed by a time determined by the CR time constant of the resistor R1 and the capacitor C1 or a time satisfying the access time by the count value of the counter 19.
Output CK. Therefore, the user does not need to manage the access time for each element, and a very simple hardware configuration is possible.

Next, the cycle time will be described. Basically, the circuit configuration is similar to that of FIGS.
Shows only an example of asynchronous mode. This circuit inputs the chip select signal / CS and the read signal / RD signal to the AND circuit 21, and outputs the output from the resistor R2 and the capacitor C.
N is delayed through a simple CR delay circuit by 2.
Invert by OT circuit 22 and cycle time signal / Cycle
When outputting the next time, the user sees the signal of this cycle time signal / Cycle before accessing.

In the above description, since the access time signal / ACK and the cycle time signal / Cycle are respectively output, the user must manage them, but in order to make the circuit configuration simpler, both signals must be controlled. Should be together. An example thereof is shown in a block diagram in FIG. 5 and a timing chart in FIG. The configuration of FIG. 5 has two counters 23,
24 and counter control circuits 25 and 26, and have both the access time management function and the cycle time management function.

The operation of this example will be described with reference to FIG.
First, when the first access is started, the next C when the chip select signal / CS and the read signal / RD become "L"
The counter 23 starts in synchronization with the PU clock.
The access time signal / ACK becomes "L" after a certain time, and the first access ends.

Then, the counter 24 is started in synchronization with the next CPU clock when the chip select signal / CS and the read signal / RD become "H". During that time, the CPU starts the next access without being aware of the cycle time. However, since the read signal / RD in the element is ANDed with the cycle time signal / Cycle, it does not become active until the cycle time signal / Cycle of the counter 24 becomes "L". Therefore, the read signal / RD is activated by the counter 24 after a prescribed cycle time, and the cycle is started. The above control is performed by the logic of the counter control circuits 25 and 26.

With such a structure, only one output signal is required, and the user does not need to manage the access time and cycle time. Further, in order to have more versatility, it may be configured to have a register in which the user can set the counter value and compare the output with the counter.

[0022]

As described above, according to the present invention, since the peripheral IC element itself outputs the access time end signal, the user does not need to manage the time for each element, and the circuit configuration can be simplified. It is possible to reduce circuit mistakes. In addition, since the cycle time is managed by the device itself, it is not necessary for the user to create a program for time management, and the program capacity can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a peripheral IC showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit example of an asynchronous mode of an ACK control circuit 13 in FIG.

FIG. 3 is a diagram showing a specific circuit example of the system synchronization mode.

FIG. 4 is a diagram showing an example of a circuit in asynchronous mode for explaining the cycle time.

FIG. 5 is a block diagram showing an example of a circuit that can similarly manage both access time and cycle time.

6 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 7 is a timing chart for explaining the access time of a conventional peripheral IC.

8 is a block diagram showing a specific circuit example for creating access times Tac1 and Tac2 in FIG. 7. FIG.

FIG. 9 is a timing chart for explaining the cycle timing of the same.

[Description of Reference Signs] 10 peripheral IC 11 data bus buffer 12 read / write control circuit 13 ACK control circuit 14 bus buffer 19, 23 to 26
counter

Claims (2)

[Claims] 1. A device for managing the unique access time of the device by the device itself, and a device for automatically starting time management when access is started, and for the user after the unique time has passed. And a means for outputting a notification signal. 2. A device for managing the unique cycle time of the device by the device itself, and automatically starting time management when the access is completed, and the unique cycle time is maintained even when the next access is started. A peripheral IC having means for automatically prohibiting starting access to the device until the time passes.