JPH0588663A - Image signal input/output device - Google Patents

Abstract

PURPOSE:To enable high-speed data transfer without restricting CPU operation by performing high-speed access without using an expensive RAM such as a video RAM, but using a normal inexpensive DRAM which has a slow access speed. CONSTITUTION:The image signal input/output device which is equipped with a page buffer 3 of DRAM constitution controlled by a control means 5 and a data width converting circuit 7 for conversion between the data width of the page buffer 3 and the width of a data bus to an external device 6 for image reading and generating operation, and performs bus arbitration by the control means 5 through the data width converting circuit 7 to input and output an image signal between the external device 6 and page buffer 3 is provided with an address timing generating circuit 8 where the input/output timing of the page buffer 3 is set according to the nibble mode of the DRAM; while the apparent access speed is increased by input/output processing in the nibble mode to shorten the time of bus acquisition affecting the operation of the control means 5, the high-speed data transfer is implemented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for connecting a printer controller and a laser beam printer (LBP),
The present invention relates to an image signal input / output device such as a device that reads an image signal from an image reading device into a page buffer.

[0002]

2. Description of the Related Art Conventionally, for example, a high-speed, high-density LBP uses an electrophotographic technique. Therefore, in order to execute various print commands from a host computer, it is necessary to stop the machine during output. Therefore, a page buffer corresponding to the size of one page of the transfer paper is provided, and when the data is prepared, this content is printed out.

Here, as means for connecting the page buffer and an external device such as a printer, for example, a dedicated RAM for connecting the CRT and the page buffer (generally,
It is common to use dual port RAM with independent read / write ports or referred to as video RAM).
Therefore, some graphic display controllers (hereinafter referred to as GDCs) have a built-in function of controlling the video RAM (for example, Mitsubishi integrated circuit <A
SSP>"M66250P / FP", 5th edition, '88
November, 5120 words x 8-bit high-speed line memory provisional material).

On the other hand, there is a direct memory access controller (hereinafter referred to as DMAC) as a means for efficiently connecting a memory connected to a CPU bus to an external device and inputting / outputting image data, and this is used. The method is also general.

[0005]

When a video RAM is used, the timing circuit is almost unnecessary, so the circuit configuration is simple. However, although the cost of memory has been decreasing year by year, such a video RAM with a high access speed has the same storage capacity as that of a normal dynamic RAM (hereinafter referred to as DRAM) and a bit unit price of about 1.5.
~ 2 times more expensive. When the storage capacity is small such as for CRT display (for example, 1024 dots × 1024
16 colors can be displayed with dots x 4 = 524 Kbytes)
May be such a video RAM, but with high density LB
In the case of P, for example, the capacity required for one A4 size page with a density of 400 DPI is 210 mm × 400 ÷ 25.4.
× 297 mm × 400 ÷ 25.4≈2 Mbytes can express only two colors of black and white, resulting in extremely high cost.

On the other hand, when the DMAC is used, data is transferred in units of 1 byte (= bit) or 1 word (= 16 bits), and the transfer speed is limited. Also,
When the DMAC uses the CPU bus, the CPU operation is limited, and the processing speed of the entire device is reduced.

Incidentally, the timing of normal read / write access to the DRAM is shown in FIGS.
Since most CPUs, GDCs, or DMACs input / output data in units of their respective bus widths, the circuit is designed according to this timing when accessing the DRAM.

In the figure, each time t is t _RC : Random read / write cycle time t _RAC : / RAS access time ('/' indicates a bar ... The same _{applies to} other signals) t _CAC : / CAS access time t _OFF : Output buffer turn-off delay time t _RP : / RAS precharge time t _RAS : / RAS pulse width t _RSH : / RAS hold time t _CSH : / CAS hold time t _CAS : / CAS pulse width t _RCD : (/ RAS )-(/ CAS) delay time t _CRP : (/ CAS)-(/ RAS) precharge time t _ASR : Row address setup time t _RAH : Row address hold time t _ASC : Column address setup time t _CAH : Column address hold Time t _AR : Column address hold time (/ RAS standard) t _RCS : Read command setup time t _RCH : Read command Hold time (/ CAS reference) t _RRH : Read command hold time (/ RAS reference) t _WCH : Write command hold time t _WCR : Write command hold time (/ RAS reference) t _WP : Number of write command pulses t _RWL : (Write Command)-(/ RAS read time) t _CWL : (Write command)-(/ CAS read time) t _DS : Data input setup time t _DH : Data input hold time t _DHR : Data input hold time (/ RAS reference) is there. Also, in the timing chart, the shaded portions indicate that they are unrelated to H and L.

This is TMM4125AP-1 manufactured by Toshiba
It is quoted from the 0 data book, and at a minimum,
It takes 190 nsec, but in reality, it takes a little longer than this minimum value due to the convenience of the CPU clock or the like.

In general, the LBP scans a laser beam in a direction perpendicular to the transfer paper conveyance direction and turns on / off the laser beam at this time to perform printing, and the page buffer uses one page at this time. Minutes on /
The off signal is stored. In such an LBP, normally, as shown in FIG. 20, the reading direction of the page buffer 1 and the scanning direction of the laser beam are made to coincide with each other.
When it is necessary to rotate the image signal as shown in FIG. 1, the rotated image signal is prepared in the page buffer 1 in advance. 2 is a transfer paper. That is, FIG. 20 shows the contents of the page buffer 1 when the transfer paper 2 is conveyed in the vertical direction, and FIG. 21 shows the contents of the page buffer 1 when the transfer paper 2 is conveyed in the horizontal direction. Figure 2
As can be seen from 1, the character “ABC” is rotated and prepared in the page buffer 1.

On the other hand, as shown in FIG. 22, the image signal of the page buffer 1 is always the same, and it is possible to deal with both the vertical and horizontal carrying directions as shown in FIGS. is there. That is, the signal reading from the page buffer 1 may be performed in the direction of (b) in the figure and in the direction of (c) in the figure. That is, by controlling the read / write address of the page buffer 1, processing in both directions can be dealt with. However, since a page buffer having a normal DRAM configuration takes access time, the transfer may not be in time.

[0012]

A page buffer by a DRAM controlled by a control means by a CPU or a graphic display controller, a data width of the page buffer, and a data bus width for an external device for image reading / forming. An image signal input / output, which comprises a data width conversion circuit for converting, and the control means performs bus arbitration via the data width conversion circuit to input / output an image signal between the external device and the page buffer. According to the invention of claim 1, an address timing generation circuit is provided in which the input / output timing of the page buffer is set based on the nibble mode of the DRAM.
In the invention according to claim 2, DRA is used in place of the nibble mode.
According to the third aspect of the invention, the static column mode is used instead of the nibble mode.

According to a fourth aspect of the present invention, an address timing generation circuit is provided in which the input / output timing of the page buffer is set based on these nibble mode, page mode or static column mode, and the mode of this address timing generation circuit is set. An external selection means for selectively setting any one of the nibble mode, page mode and static column mode is provided.

On the other hand, in the fifth aspect of the present invention, the page buffer by the DRAM controlled by the control means by the CPU or the graphic display controller and at least the input / output data of the external device for image reading / forming are provided in the page buffer. A line buffer for storing the number of lines corresponding to the data bus width, and the control means performs bus arbitration via the line buffer to input / output an image signal between the external device and the page buffer. Image signal input / output device
When the value equal to or greater than the number of addresses of M is n, the number of bits for one line of the page buffer is set to a unit of 2 n.
The page buffer is provided with a register block having a storage capacity of (data bus width) × (data bus width) in which a step amount of an address and a data read direction are set when an image signal is transferred to and from the line buffer. An address timing generating circuit for inputting and outputting an image signal between the register block and the register block is provided in the page mode of the DRAM. In the invention according to claim 6, the page mode is replaced by the static column mode.

According to a seventh aspect of the present invention, an address timing generating circuit for performing the page mode or the static column mode is provided, and the mode of the address timing generating circuit is selectively set to either the page mode or the static column mode. An external selection means is provided.

According to the present invention, while the image signal is being transferred between the line buffer and the page buffer via the register block, the other line buffer and the external device can be used. Two toggle-type line buffers for transferring an image signal between and are used.

[0017]

According to the first to third aspects of the present invention, an ordinary inexpensive DRAM having a slow access speed is used, but the input / output timing is set to nibble mode, page mode or static column mode, and the control means operation is performed. Since the bus acquisition time, which has an effect on, is shortened, the apparent access speed can be increased and high-speed data transfer becomes possible. In this case, according to the invention of claim 4,
Since the address timing generation circuit is configured for all modes and can be selected by the external selection means,
It becomes versatile regardless of the type of DRAM.

On the other hand, also in the case of the invention according to claim 5 or 6, high-speed data transfer is possible while using the DRAM as in the case of the invention according to claims 1 to 3, and a mode for accessing the DRAM at high speed and a line buffer are provided. By combining with the register block, the rotation processing of the image signal at the time of transfer can be performed at high speed, and the processing capacity is improved. In this case, also in the case of the invention described in claim 7, as in the invention described in claim 4, it has versatility regardless of the type of DRAM. Further, according to the invention of claim 8, two line buffers are prepared and alternately used for input and output by a toggle method, so that image signals can be continuously transferred.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. The same items as those shown in FIGS. 18 and 19 are indicated by the same notations. First, in the present embodiment, an ordinary DRAM is used as a page buffer, and attention is paid to the nibble mode to speed up the input / output timing of an image signal. 2 shows the access timing of the write cycle in the nibble mode, and FIG. 3 shows the access timing of the read cycle in the nibble mode. The illustrated mode uses four consecutive data (VALI
In this mode, D DATA) is read at high speed. In the figure, t _NC : nibble mode cycle time t _NCAS : nibble mode access time t _NWRSH : nibble mode write / read modify write cycle time t _NRRSH : nibble mode read / read modify write cycle time.

In this nibble mode, the first signal / RA
Based on the address specified by S and / CAS, the signal / CAS is changed four times to read or write four continuous data. For example,
The time required to write four pieces of data is calculated by (t _CSH + t _NC × 3) in the example shown in FIG.
According to the data book of TMM4125AP-10 manufactured by Toshiba mentioned above, t _CSH = 100 nsec, t _NC = 5.
Since it is 0 nsec, this time is 250 nsec. In actual circuit design, it will be longer than this value, but the time required to write data per unit is 250/4 = 70
nsec, which is about 1 compared to the normal access shown in FIG.
The time can be shortened to / 3. Therefore, DRAM
It can be seen that high speed data transfer is possible by using the nibble mode.

By the way, there are various devices such as CRTs, printers, and facsimiles that use the page buffer, and the circuit configuration of each device changes depending on the specifications. Therefore, a typical LBP is taken as an example here. The circuit configuration will be described.

First, the LBP is an electrophotographic printer that forms an electrostatic latent image on a photoconductor by turning a laser beam on and off, and transfers the image onto a transfer paper. By making / 0 correspond to on / off of the laser beam, an arbitrary figure can be formed on the transfer paper. 4 and 5 show how a black image is formed on the transfer paper 4 when each bit of the page buffer 3 is 1.

FIG. 1 shows an example of the configuration of an image signal input / output device used in such an LBP. The page buffer 3 of DRAM configuration is a control means 5 by a CPU or GDC.
Address bus, data bus and RAS, CAS and W
It is connected by each E signal line. Also, image reading
An external device 6 which is a scanner / printer for forming is provided, and the external device 6, the control means 5, and the page buffer 3 are connected via a data width conversion circuit 7 and a data bus. For example, in the case of the LBP example shown in FIGS. 4 and 5, since the data width is 1 bit, the data width conversion circuit 7 uses the transfer clock C as shown in FIG.
It may be converted so that 1 bit of data is transferred for each LOCK. Further, an address timing generation circuit 8 is provided. This address timing generation circuit 8 is used for the control means 5 by holding it with HOLDA, HOLD, RAS, C.
AS and WE are connected by signal lines and an address bus, and are connected to the data width conversion circuit 7 in the same manner as the external device 6 side, PMSYNC, FGATE, LSYNC, LGAT.
They are connected by respective timing signal lines of E and CLOCK, and the input / output timing is set by the nibble mode of the page buffer 3 of DRAM.

The relationship between the control means 5, page buffer 3 and address timing generation circuit 8 shown in FIG. 1 will be described with reference to FIG. FIG. 7 shows an example of GDC, TM34010 manufactured by Texas Instruments Incorporated.
It shows the timing of the bus release operation of
Address, data bus, RAS, CAS and other control signals are controlled by GDC. However, when you want to use these signals in the address timing generation circuit 8,
When the HOLD signal shown in FIG. 7 is set to the L level, the GDC generates the HLDA signal and releases the bus and other control signals (Hi-Z state in FIG. 7). The address timing generation circuit 8 knows the bus release by the HLDA signal and generates the address timing of the present invention.

In the above description, the address timing generation circuit 8 utilizing the nibble mode of the DRAM is used as the invention according to claim 1, but the page mode of the DRAM (corresponding to the invention according to claim 2) and the like. Alternatively, the static column mode (corresponding to the invention of claim 3) may be used.

FIG. 8 shows a timing chart of the page mode read cycle, and FIG. 9 shows a timing chart of the page mode write cycle. In the figure, t _PC is the page mode cycle time. In this page mode, the first specified Row Ad
The dress is fixed by RAS, and the content of the Column Address designated at each fall of CAS is read / written. FIG. 10 shows a timing chart of the write cycle in the static column mode, and FIG. 11 shows a timing chart of the read cycle in the static column mode. In the figure, t _SC is the static column mode cycle time. In this static column mode, RAS the Row Address when reading
Is fixed, CS and OE are set to L level, and WRITE is set to H
Data is output by fixing the level and changing the Column Address. On the other hand, when writing, Row Addr
Fix RAS to ess and C when WRITE is L level
Data is written to the address where S falls. Unlike the above nibble mode, these page mode and static column mode are not limited to four continuous data, and high speed access is possible.

Although the nibble mode, page mode and static column mode have some similarities, D
Since the types of RAMs are different, a versatility can be provided if the circuit configuration allows any type to be used. Therefore, in the invention according to claim 4, the address timing generation circuit 8 is set in advance to be usable in any of the nibble mode, the page mode and the static column mode,
Although any one mode is selected by an external selection means (not shown), it is actually more efficient to design a circuit for each mode, but the degree of integration is high as in recent gate arrays. When designing a circuit, designing all the mode-compatible circuits in one package and selecting them from the outside is also advantageous in that the type of DRAM is not selected.

The access timing of the DRAM is shown in FIGS. 2, 3 and 8 to 11, and the timing of obtaining the right to use the bus from the GDC will be described with reference to FIGS. 4 and 12. Since the page buffer 3 in FIG. 4 has a data bus width of 16 bits, 16 pieces of data are arranged for each address. Now, in order to have a page buffer 3 for two A4 size transfer papers with a density of 400 DPI, 210 × 400 divided in the lateral direction (length 210 mm)
25.4 / 16 = 206 words, vertical direction (length 297m
m) requires a memory for 297 × 400 ÷ 25.4 = 4677 lines. That is, if the head of the first line is the address 0, the head of the second line is the address 207, and the head of each line is 414 and 621. The horizontal length of the page buffer 3 configured as described above is LG
The ATE signal controls the vertical length with the FGATE signal.

FIG. 12 shows the relationship between the FGATE signal and the LGATE signal. Since the LBP scans the laser beam as described above, it is impossible to form an image for a specific period. For this reason, LGATE prohibits data transmission during this period. That is, the data transferable period is L
It is only during the period when both GATE and FGATE are valid (H level in the illustrated example). During this data transferable period, for example, in the nibble mode, a bus use right request is made to the GDC every 4 words (= 64 bits = 64 transfer clocks in FIG. 6), and after obtaining the bus, it is necessary. Then, the data is transferred to the data width conversion circuit 5.

In the page mode and the static column mode, almost the same operation as in the nibble mode is carried out, but the nibble mode has a data bus width of 4 units, but a large amount of data is transferred at once. However, the optimum design is performed in consideration of the refresh of the DRAM and the operation of the GDC (it cannot operate when the bus is released).

On the other hand, an example of the refresh cycle of the DRAM is shown in FIG. 13, which is very simple and has a timing of 8 times.
It is sufficient to perform 512 times in msec. Therefore, adding a DRAM refresh function to the address timing generation circuit 8 does not make it so complicated. By providing such a function, the page buffer 3 can be controlled by the control means 5 having no DRAM refresh function. Here, the refresh operation must always be performed, and if there is a conflict with the data transfer cycle,
The transfer cycle is prioritized.

In the above description, the data transfer from the page buffer 3 side to the data width conversion circuit 7 side like the printer controller is explained, but conversely, from the data width conversion circuit 7 side to the page buffer 3 side. For the data transfer to, the address timing generating circuit 8 may generate a difference between the read / write operation to the page buffer 3.

Next, a second embodiment of the invention will be described with reference to FIGS. In this embodiment, the image signal can be rotated, a line buffer 9 is provided in place of the data width conversion circuit 7 of the above embodiment, and
This line buffer 9, control means 5, page buffer 3
A register block 10 is interposed between and. Here, the line buffer 9 is at least the page buffer 3
The number of lines corresponding to the data width can be stored. Further, the page buffer 3 has an address timing generation circuit 8
According to the page mode (see FIGS. 8 and 9) or the static column mode (see FIGS. 10 and 11) for high speed access. In the present embodiment, as shown in FIG. N (where n is a value equal to or greater than the number of DRAM addresses, in the illustrated example, 2 to the 10th power)
Is configured to be. Therefore, the page mode or the static column mode can be used even when accessing in the direction shown in FIG. Alternatively, it can be adapted to any mode, and the external selection means can be configured to select one of the modes. In the page mode and static column mode, the Row address is fixed and the Column address is changed to access the data of a specific block. Therefore, the Row address must not be crossed during one access. . For this purpose, the number of times of access at one time is set to a power of 2, but this power is less than the number of DRAM addresses. Here, the register block 10 has a storage capacity of (data bus width × data bus width). D like this
The combination of the high-speed access mode of the RAM, the line buffer 9, and the register block 10 makes it possible to input and output an image signal accompanied by rotation processing at high speed.

An image signal input / output process for vertical and horizontal conveyance as shown in FIG. 22 in such a configuration will be described. As the line buffer 9, for example, a FIFO (first-in / first-out) memory in the above-mentioned Mitsubishi integrated circuit <ASSP> is used. Also, in the page buffer 3 as shown in FIG.
If the data width is 8 bits, register block 10
For example, as shown in FIG. 16, it is composed of a vertical transfer processing unit 10a, a horizontal transfer processing unit 10b, and a data selector 10c. Data transfer between the page buffer 3 and the register block 10 is a high speed access in the page mode or static column mode as described above. Therefore, the register blocks 10 are accessed in the order shown in the vertical transport processing unit 10a. That is, FIG.
To fix the Low address to 0 and the Column address to 0,
1024, 2048, ..., 7168 are changed to perform data transfer eight times.

On the other hand, for the data transfer between the register block 10 and the line buffer 9, two kinds of transfer can be selected by the vertical transfer processing section 10a and the horizontal transfer processing section 10b. At this time, during transfer by the vertical transfer processing unit 10a,
Make the next transfer address from address 8192, and
Block transfer is performed a predetermined number of times in units of 192 addresses. As a result, the image signals for 8 lines are transferred to the line buffer 9. Thereafter, the start point is increased by one address and the same transfer is repeated a predetermined number of times, whereby the image signal for one page is transferred. At the time of transfer by the lateral transfer processing unit 10b, the address is increased by one address, transfer for eight lines is performed, the start point is increased by 8192, and an image signal for one page is transferred.

By the way, if two line buffers 9 are prepared and are alternately used in a toggle system, while one line buffer is transferring data to and from the page buffer 3, the other one is used. Since the line buffer of (1) can transfer data with the external device 6 side, high-speed processing of data transfer becomes possible. FIG. 17 is a flowchart showing an example of data transfer processing when two line buffers of the toggle method are used.

By the way, although the image signal can be rotated by the above-mentioned procedure, in the case of rotating by 90 °, in actuality, the lower left of the page buffer 3 is used as a starting point, and block transfer is performed in units of −1024 addresses. However, when the line buffer 9 is a LIFO (last in first out) memory, this is not necessary. 180 °, 270
The same applies when rotating it.

[0038]

Since the present invention is configured as described above, according to the inventions of claims 1 to 3, an ordinary inexpensive DRAM having a slow access speed is used, but its input / output timing is a nibble mode. The page acquisition mode or the static column mode is used, and the bus acquisition time that affects the operation of the control means can be shortened. Therefore, the apparent access speed can be increased and high-speed data transfer can be achieved. At this time, according to the invention of claim 4, since the address timing generation circuit is configured to be compatible with all modes and can be selected by the external selection means, versatility can be provided regardless of the type of DRAM. You can

On the other hand, also in the case of the invention according to claim 5 or 6, high-speed data transfer is possible while using the DRAM as in the case of the invention according to claims 1 to 3, and in addition to such DRA.
Due to the combination of the mode for accessing M at high speed, the line buffer and the register block, the rotation processing of the image signal at the time of transfer can be performed at a high speed, and the processing capacity can be improved. According to the invention, like the invention described in claim 4, it has versatility regardless of the type of DRAM. Furthermore, according to the invention described in claim 8, two line buffers are prepared and a toggle system is provided. Thus, the image signal can be continuously transferred because the input and output are alternately used.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing a write cycle in a nibble mode.

FIG. 3 is a timing chart showing a read cycle in a nibble mode.

FIG. 4 is an explanatory diagram showing a relationship between a page buffer and a transfer sheet.

FIG. 5 is an explanatory diagram showing a part of a page buffer.

FIG. 6 is a timing chart showing the relationship between a transfer clock and data output.

FIG. 7 is a timing chart showing an example of releasing control of a bus.

FIG. 8 is a timing chart showing a read cycle in page mode.

FIG. 9 is a timing chart showing a write cycle in page mode.

FIG. 10 is a timing chart showing a write cycle in a static column mode.

FIG. 11 is a timing chart showing a read cycle in a static column mode.

FIG. 12 is a timing chart showing the relationship between FGATE and LGATE.

FIG. 13 is a timing chart showing a refresh operation.

FIG. 14 is a block diagram showing a second embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a page buffer configuration example.

FIG. 16 is a block diagram showing a configuration example of a register block.

FIG. 17 is a flowchart showing toggle processing of a line buffer.

FIG. 18 is a timing chart showing a normal read cycle of a DRAM.

FIG. 19 is a timing chart showing a normal write cycle of DRAM.

FIG. 20 is an explanatory diagram showing the relationship between the reading direction of the page buffer and the transfer paper conveyance direction.

FIG. 21 is an explanatory diagram showing the relationship between the reading direction of the page buffer and the transfer paper conveyance direction.

FIG. 22 is an explanatory diagram showing the relationship between the reading direction of the page buffer and the transfer paper conveyance direction.

[Explanation of symbols]

 3 Page buffer 5 of DRAM configuration 5 Control means 6 External device 7 Data width conversion circuit 8 Address timing generation circuit 9 Line buffer 10 Register block

Claims (8)

[Claims] 1. A page buffer by a dynamic RAM controlled by a control means by a CPU or a graphic display controller, and data for converting a data width of the page buffer and a data bus width for an external device for image reading / forming. And a width conversion circuit,
In the image signal input / output device in which the control means performs bus arbitration via the data width conversion circuit to input / output an image signal between the external device and the page buffer, the nibble mode of the dynamic RAM is set. An image signal input / output device comprising an address timing generation circuit in which the input / output timing of the page buffer is set based on the above. 2. A page buffer by a dynamic RAM controlled by a control means by a CPU or a graphic display controller, and data for converting a data width of the page buffer and a data bus width for an external device for image reading / forming. And a width conversion circuit,
In the image signal input / output device in which the control means performs bus arbitration via the data width conversion circuit to input / output an image signal between the external device and the page buffer, the dynamic RAM page mode is set. An image signal input / output device comprising an address timing generation circuit in which the input / output timing of the page buffer is set based on the above. 3. A page buffer of a dynamic RAM controlled by a control means of a CPU or a graphic display controller, and data for converting a data width of the page buffer and a data bus width for an external device for image reading / forming. And a width conversion circuit,
In the image signal input / output device, wherein the control means performs bus arbitration via the data width conversion circuit to input / output an image signal between the external device and the page buffer, a static column mode of the dynamic RAM. An image signal input / output device comprising an address timing generating circuit in which the input / output timing of the page buffer is set based on the above. 4. A page buffer of a dynamic RAM controlled by a control means of a CPU or a graphic display controller, and data for converting a data width of the page buffer and a data bus width for an external device for image reading / forming. And a width conversion circuit,
In the image signal input / output device, wherein the control means performs bus arbitration through the data width conversion circuit to input / output an image signal between the external device and the page buffer, a nibble mode of the dynamic RAM, An address timing generation circuit in which the input / output timing of the page buffer is set based on the page mode or the static column mode is provided, and the mode of the address timing generation circuit is any one of nibble mode, page mode or static column mode. An image signal input / output device, characterized in that external selection means for selectively setting is provided. 5. A page buffer of a dynamic RAM controlled by a control means of a CPU or a graphic display controller, and a line for input / output data of an external device for image reading / forming at least for a data bus width of the page buffer. An image signal input / output device having a line buffer for storing the number of image signals, wherein the control means performs bus arbitration via the line buffer to input / output an image signal between the external device and the page buffer. , When the value of the number of addresses of the dynamic RAM or more is n, the number of bits for one line of the page buffer is set to the n-th power of 2 and the step amount of address when transferring an image signal to and from the line buffer. And data read direction are set (data bus width) x (data bus ) Register blocks having a storage capacity provided in the input and output of image signals between the register block and the page buffer dynamic RAM
An image signal input / output device provided with an address timing generation circuit which operates in the page mode. 6. A line buffer of a dynamic RAM controlled by a control means of a CPU or a graphic display controller, and a line for input / output data of an external device for image reading / forming at least for a data bus width of the page buffer. An image signal input / output device having a line buffer for storing the number of image signals, wherein the control means performs bus arbitration via the line buffer to input / output an image signal between the external device and the page buffer. , When the value of the number of addresses of the dynamic RAM or more is n, the number of bits for one line of the page buffer is set to the n-th power of 2 and the step amount of address when transferring an image signal to and from the line buffer. And data read direction are set (data bus width) x (data bus ) Register blocks having a storage capacity provided in the input and output of image signals between the register block and the page buffer dynamic RAM
An image signal input / output device characterized in that an address timing generating circuit for performing the static column mode is provided. 7. A page buffer based on a dynamic RAM controlled by a control means based on a CPU or a graphic display controller, and a line corresponding to at least the data bus width of the page buffer for input / output data of an external device for image reading / forming. An image signal input / output device having a line buffer for storing the number of image signals, wherein the control means performs bus arbitration via the line buffer to input / output an image signal between the external device and the page buffer. , When the value of the number of addresses of the dynamic RAM or more is n, the number of bits for one line of the page buffer is set to the n-th power of 2 and the step amount of address when transferring an image signal to and from the line buffer. And data read direction are set (data bus width) x (data bus ) Register blocks having a storage capacity provided in the input and output of image signals between the register block and the page buffer dynamic RAM
And an external selection means for selectively setting the mode of the address timing generation circuit to either the page mode or the static column mode. Signal input / output device. 8. A line buffer transfers image signals between one line buffer and a page buffer via a register block while transferring image signals between the other line buffer and an external device. 7. The image signal input / output device according to claim 5 or 6, wherein two line buffers of a toggle type for performing are provided.