JPH0239383A - Image processor - Google Patents

Abstract

PURPOSE:To facilitate the execution of a multi-task by constituting the title process of an image memory for storing at least a one-screen portion or more, a data bus used exclusively for the image memory, an access port from a CPU, a data length converting circuit, a memory controller and an external i/f. CONSTITUTION:A CPU 2 executes a font development of a character and a dot pattern development of graphic data and image data to an image memory A8 through a CPU access port 6. Subsequently, a start is applied to a DMAC 12, data is read out of the image memory A8 and through a data bus A 14, access width of the memory and data width of an external i/f 13 are brought to matching by a data length converting circuit 11 and image data is transferred to a printer. On the other hand, the CPU develops image data of the second page to an image memory B9 after having applied a start to the DMAC 12. This time data of the image memory B9 is transferred to the external i/f 13 by the DMAC 12, and image data of the third page is developed to the memory A8. In such a way, plural pages can be printed out at a high speed.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention can be applied to computers, scanners, and printers.

The present invention relates to an image processing device that is connected to a fax machine or the like and performs high-speed image data transfer.

[Conventional technology]

Conventionally, as shown in FIG. 5, there are many double buffer configurations that do not have a dedicated memory for image data and are arranged in 1-ine units. The details of the configuration will be described later. but,
Such a configuration has the following drawbacks.

In the conventional example shown in FIG. 5, data cannot be directly transferred between the image memory 47 and the external I/F 13 due to speed constraints, so buffering is required, and the line buffer A42. I had a B43. In this case, the DMA controller 46 writes the data in the image memory 47 to the line buffer 42 or 43 via the system bus 1, and writes the data from the line buffer to the external i
/ f Send to 13. Alternatively, data can be written from the external I/F 13 to the line buffer, and from the line buffer to the image memory 47 via the system bus I. Therefore, image memory 47 and external i/f 13
When performing data transfer between 3 and 3, system bus 1 is dedicated to the transfer, and CPU 2 transfers data between memories 3 and 3. image memory 4
It was extremely difficult to access 7th grade. In other words, the drawback was that multitasking was difficult. As is clear from the above, in the past, (1) it was necessary to transfer data within the device in accordance with the transfer speed of the external device;
There may be cases where the PU operation is too slow to follow up.

(2) The system bus is occupied during image data transfer.

(3) During image data transfer, the CPU is occupied with data transfer.

(4) Due to (2) and (3) above, multitasking becomes difficult.

〔the purpose〕

In view of the above points, it is an object of the present invention to have an image memory for at least one screen, and to have an image memory and an external @1/f
An object of the present invention is to provide an image processing apparatus that can reliably perform screen-by-screen transfer at the transfer speed of an external device by providing a DMAC between the two.

An object of the present invention is to provide a memory controller that has two or more image memories, can control an access port from the CPU, a data bus between the data length conversion circuit and the image memory, and provides a memory controller that can control an access port from the CPU, a data bus between the data length conversion circuit and the image memory, and
It is an object of the present invention to provide an image processing device that can simultaneously access the image data from the computer, develop data for the next screen, etc. while outputting image data to a printer, etc., and increase overall speed.

The purpose of the present invention is to provide an image memory for one screen or more and an external I/O
By providing a DMAC between the cPU and the cPU, the system bus is open during image data transfer, and the cPU can perform other processing, thereby providing an image processing device that can easily perform multitasking.

An object of the present invention is to have two or more image memories,
An object of the present invention is to provide an image processing device which can continuously transfer data from two image memories by providing a double-screen data input/output.

〔Example〕

Figure 1 is a drawing that best represents the features of the present invention.
is a standard specification system bus such as VER3A VME,
2 is a CPU that controls and processes the entire device; 3 is a program memory; 4 is a video memory for display; 5
is CRT display, 6 is CPU access port, 7 is
1 is a control signal interface, 8 is an image memory A, 9 is an image memory B 510 is a memory controller, 11 is a data length conversion circuit, and 12 is a DMAC.

13 is an external interface (hereinafter referred to as external I/F), and 14 is a data bus A115 for the image memory 88.
The data bus B116 for the image memory B9 is a memory control signal A, 17 is a memory control signal B, 18 is a CPU acceptance signal, 19 is a CPU request signal, 20 is a DMA request signal, 2
1 is a DMA acceptance signal, 22 is a data length conversion control signal, 2
3 is an external request signal, and 24 is an external acceptance signal. external d
The operation of each part will be explained by taking as an example a case where a page printer is connected as the device.

CPU2 develops the font of characters to be printed, graphic data,
Dot pattern development of the image data is performed in the image memory A8 through the CPU access port 6. When the writing to the image memory A8 is completed, the DMAC 12 is activated, reads the data from the image memory A8, and transfers the data to the data bus AI.
4, the data length conversion circuit 11 matches the access width of the memory with the data width of the external I/F 13, and transfers the image data to the printer.

On the other hand, after activating the DMAC 12, the CPU develops the second page of image data in the image memory B9.

When data transfer from image memory A8 by DMAC and expansion to image memory B9 are completed, data in image memory B9 is transferred to external I/F1 by DMAC12.
3, and develops the image data of the third page in the image memory A8. This allows multiple pages to be printed out at high speed.

Here, the memory controller 10 receives a CPU request signal 19,
The memory cycle is determined according to the priority by looking at the states of the DMA request signal 20 and the refresh request signal generated inside the memory controller.

For example, refresh the priorities in descending order of priority>DM
If A>CPU, when a refresh request and a CPU request signal 19 are generated simultaneously, a refresh operation is performed first, and then a write/read operation from the CPU is performed. Also, during a write/read cycle between the CPU 2 and the image memory A8, the CPU access port 6 and the data bus A14 are connected, and during a write/read cycle by DMA, the data length conversion circuit 11 and the data bus AI4 are connected. do.

Note that the memory controller 10 has two control units for image memory 88 and image memory B9, and has a data path A1.
By separating CPU access port 6 and data bus A14.4 from data bus B15, CPU access port 6 and data bus A14. Data length conversion circuit 11
and data bus B15, and CPU2 connects image memory A.
8 and DMACI2 can access the image memory B9 at the same time. Therefore, with the above configuration, image memory A8 and image memory B9 have the characteristics of dual ports and double buffers,
Efficient memory access such as data rewriting while transferring data can be easily achieved.

A flowchart of the above operation is shown in FIG.

An example of printing a three-page document file will be explained. First, the contents of the first page are developed into a printed dot pattern using Sl and written into the image memory A. When the expansion is completed, the data in the image memory A is started to be transferred to the external i/[13] through the data length conversion circuit 11 in S2. S
3, since there are still two pages left, the process moves to S4, and the contents of the second page are started to be developed in the image memory B.

After the transfer of the data of the first page of image memory A is completed in S5 and S6 and the expansion of the contents of the second page of image memory B is completed, transfer of the data of the second page of image memory B is started in S7. There is still one page left in S8, so S
9, the third page starts to be developed in the image memory A again. When the data transfer of the second page of the image memory B is completed at SIO and Sll, and the contents of the third page of the image memory A are completed, the process moves to S2 and the transfer of the data of the image memory A is started. In S3, all three pages have been developed, so the process moves to S12 and waits until the data currently being transferred is completed, and printing is completed at the end of the transfer.

Next, the operation of the data length conversion circuit will be explained.

An example of the data length conversion circuit 11 is the configuration shown in FIG.

Here, 25.26. ．． 27 and 28 are bidirectional latch circuits with output control that can latch 8-bit data, 29 is an 8-bit data bus, 30. 31 is an 8-bit bidirectional data driver; 32. 33. 34.degree. 35 are tri-state output control signals of the bidirectional latch circuits 25-28. 36. 37. 38.
39 is a latch signal for the bidirectional latch circuits 25 to 28; 40 is a signal for controlling the direction of data in the bidirectional latch circuits 25 to 28 and the bidirectional data driver 30.31;
1 is a signal indicating the advancing direction of the address when accessing the image memory.

Here, an example will be shown regarding the image memory A8 side.

A similar latch circuit is connected to the 8-bit data bus 29 on the image memory B9 side as well. First, external i
The case where data is written from /f 13 to image memory 8 will be explained. The direction of data is set by DIR40, and when the address progression of memory access is normal, ADINC41 is used to set the direction of the data.
1 to enable and 30 to disable. Data coming from external I/F 13 is sent to data driver 31
The data flows through the 8-bit data bus 29 one after another. As the data came in, WRTO36, W
RTI 37. Latch signals are generated in the order of WRT2 38°WRT3 39. When the latching by WRT339 is completed, the 32-bit data from external I/F 13 is latched, so this data bus A
The 32-bit data on A14 is written to the image memory A8. Then, latching is repeated from WRTO again, and writing to the memory is performed once every four times.

If the address is in the opposite direction, the data driver 30 is enabled and the data driver 31 is disabled. here 3
Data is swapped for 0 and 31 and data bus 2
9 is connected. Data coming from external I/F 13 appears on data bus 29 through data driver 30. This time WRT3 39°WRT2 38
．． WRTI 37. The data is latched in the order of WRTO36 and written to memory. This means that when reading an image from a scanner, if the above operation is performed, the image will be rotated by 180 degrees. Also, if the transfer start address is on a 4-byte boundary only (byte
It is also possible at the te boundary.

For example, the above operations are performed at address 0 of image memory A8,
The case where the address starts from address 4, address 8, etc. is shown, but when the address starts from address 1, address 5, etc., the first address is WRTI 37. WRT2 38. WRT3 3
The data is latched in the order of 9, and when 3 bytes are latched, it is written to the image memory 88. From the second time onwards, WRTO36, WRT
I37. WRT2 38. It is sufficient to latch the data in the order of WRT3 to WRT39 and repeat the memory writing. Similarly, when starting from address 1, address 5, etc., if the address is in the opposite direction, WRTO36 is latched and written to the memory at first, and then WRT3 is written.39. WRT2 38. -W
RTI 37. All you have to do is latch it in the order of WRTO36 and write it to memory.

Data transfer from image memory A8 to external i/f l3 is the same, with DIR40 reversed to the above, and WRTO-W
It is sufficient to control the old parts 32 to 35 instead of RT3.

A flowchart of these operations is shown in FIG.

This is a flowchart for transferring data between the image memory and the external i/f 13.
/ f 13 to the image memory will be explained.

The process moves from S13 to 314, and if the transfer is to increase the memory address, the process moves to S15, where the data driver 31 in FIG. 3 is enabled and the data driver 30 is disabled, and the process moves to S17. If the transfer start address is expressed as 4n (n==0.1.2...) like 0.4.8, the process moves to S23 and the external request signal 23 (hereinafter referred to as DRQ) in FIG. ) comes, move to S24 W
RTO is generated and 25 in FIG. 3 latches the data. After that, every time DRQ comes, WRTI, WRT2゜WRT3
is generated and latches 4 bytes of data.

When the DMA request signal 20 is generated in S31 and the DMA acceptance signal 21 is received from the memory controller 10, the process returns to 823 and the above operations are repeated until the transfer is completed.

In S17, transfer start address 1. 5. When expressed as 4n+1 (n = 0, 1, 2-) like 9..., it skips S23゜S24 and moves to 325, generates WRTI, WRT2゜WRT3, and 3by
After latching the te data, a DMA request signal is generated to the memory in step 331. Once the reception is confirmed, the process moves to S23 and WRTO, WRTI.

WRT2. Generates WRT3. Transfer start address is 2
, 6, ... 4n+2 (n=o,
1-), it starts from S27 and the WR
T2. When WRT3 is generated and 2 by t'e is latched, the first memory write is executed. The transfer start address is 3, 7. 4n+3 (n=o,
1. ), the process moves to S29 and the WRT
3, latches the Ibyte data, and performs the first memory write. Thereafter, the above operations from S23 are repeated until the transfer is completed.

Next, if the mode in which the address decreases is set in S14, the process moves to S16, and the data driver 30 is enabled and 31 is disabled.

4(b) and 4(c), the order of the latch signals is reversed and WRT3. WRT2. The process is the same except that WRTI and WRTO are latched in that order, and the above operation is repeatedly executed until the transfer ends, except that the start changes depending on the transfer start address, in the same way as described in the above operation.

Next, the operation when transferring data from the image memory to the external I/F 13 will be explained.

First, the process moves from S13 to 341, where a DMA request signal 20 is generated. When the data is read from the memory and the DMA acceptance signal 21 is received, the process moves to S42 and latches 4 bytes of data from the memory. When the address increase mode is set, the process moves from 343 to 344, and the data driver 3
Enable 1 and disable 30. The transfer start address is 0.4.8. 4n (n=+0゜1.2
．． ...), the process moves from S45 to 354, and when DRQ arrives, RDO is generated in 355, and the data held by the bidirectional latch 25 is sent to the external I/F l 3 through the data driver 31. .

Next, every time DRQ comes, the old shore, T month, and door are generated, and S52
Then, the DMA request signal 20 is generated, data at the next address is read, and the above operations are repeated from S53 until the transfer is completed. If the transfer start address is expressed as 40+1, the process moves from S46 to 356, generates the old line, old buy, and old river, and after transferring 3 bytes, requests the second memory read in S52, and repeats the transfer every 4 bytes. .

If the transfer start address is expressed as 4n+2, RD2
．． After transferring 2 bytes by RD3, 4 bytes from the second time onwards
Transfer is executed in units of te. Transfer start address is 4n+
Even in the case represented by 3, after 1 byte transfer by RD3,
Transfer is performed in 4-byte units from the second time onwards. In the case of transfer in address decreasing mode, the process moves from S43 to 348, the data driver 30 is enabled, the data driver 31 is disabled, and the same operation as described above is performed with the order of occurrence of RDO to RD3 reversed.

〔Effect of the invention〕

As detailed above, according to the present invention, 1. Does not depend on the data transfer speed of the external device.

2. The CPU can occupy the system bus during data transfer with an external device, making parallel operation possible.

3. The CPU does not need to see the image data transfer side.

It has this effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a workstation implementing the present invention, FIG. 2 is a flowchart showing the operation that produces the effects of the present invention, and FIG. 3 is a specific example of the data length conversion circuit shown in FIG. FIGS. 4(a) to 4(a) are flowcharts showing the operation of the embodiment shown in FIG. 3, and FIG. 5 is a block diagram of the conventional example.

Claims (1)

[Claims] (1) In a device that processes and outputs image data such as input, editing, and storage, an image memory that stores at least one screen, a data bus dedicated to the image memory, an access port from the CPU, a DMAC, a data length conversion circuit, An image processing device consisting of a memory controller and external I/F.