JPH0571103B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides character and graphic information created by a computer by superimposing it on an image such as a television signal on a screen such as a CRT (cathode ray tube). display,
The present invention relates to a character/figure signal generator that can be efficiently used for producing still images for conference systems, advertisements, bulletins, educational materials, etc.

(Prior Art) Recently, there have been many opportunities to come into contact with information that uses CRT images as a medium, such as INS, capstan systems, or video conference systems. It is thought that such graphic systems will have even greater expectations in the future due to the strong appeal generated by the large amount of information and the rapidity of reporting as electronic images.

FIG. 3 is used for such a system. 1 is a block diagram showing the configuration of a conventional character/figure signal generator. In the figure, 1 is a display address control circuit on a display such as a CRT, and its output a
is applied to the graphic memory 2 in which the character and figure signals b from the host computer are stored, and the readout output c is subjected to signal parallel, serial conversion, color conversion, etc. by the output conversion circuit 3, and is converted into characters. The signal is sent to a video device (not shown) as a graphic signal d. 4 is a synchronization separation circuit, which separates a horizontal synchronization signal f and a vertical synchronization signal g from an external video signal e. Reference numeral 5 denotes a display clock generation circuit which generates a display clock pulse h having an integral multiple of the horizontal synchronization frequency of the synchronization separation circuit 4 and inputs it to the control signal generation circuit 6. The control signal generation circuit 6 receives the horizontal synchronization signal f, the vertical synchronization signal g, and the display clock h generated by the synchronization separation circuit 4 and the display clock generation circuit 5, and receives the display address control circuit 1,
It generates control signals and operation clock i for operating the graphics memory 2 and output conversion circuit 3. The display address control circuit 1 receives a horizontal synchronization signal f and a vertical synchronization signal g at the same time, and operates to be initialized for each horizontal synchronization and vertical synchronization.

The conventional character/figure signal generator has the above-mentioned configuration, and by separately providing a display address control circuit 1 and a control signal generation circuit 6, it can synchronize with an external video signal and generate signals from a host computer. It is possible to display characters and shapes.

(Problems to be Solved by the Invention) However, the conventional character/figure signal generator requires a circuit configuration that combines low-density ICs (integrated circuits), which makes the device large and expensive. The disadvantages were that it was expensive and lacked versatility.

In view of the shortcomings of the conventional character/figure signal generator, the present invention uses a versatile CRT controller capable of external synchronization using a frame synchronization signal to generate figures based on computer signals,
The object of the present invention is to provide a character/figure signal generator capable of displaying video signal figures on a single CRT.

(Means for Solving the Problems) The present invention provides a graphics memory for storing graphical information of a host computer, and parallel/parallel processing of its output.
A character/figure signal generator having a serial conversion circuit and a CRT controller capable of external synchronization by frame synchronization, which includes a CRT controller capable of synchronization by an external video signal, and separates the synchronization signal from the external video signal. A synchronization separation circuit, a display clock generation circuit that generates a display clock pulse of an integral multiple of the synchronization signal frequency obtained from the synchronization separation circuit, a counting circuit that counts the period during which the clock pulse is applied to the CRT controller, and which counts a predetermined count value. a switching circuit that stops the application of the clock pulse when the above clock pulse is applied;
The configuration includes an adjustment pulse circuit for ending the stop period within the allowable period of the CRT controller, thereby eliminating the drawbacks of the conventional character/graphic signal generator described above.

(Function) Since the present invention has the above-described configuration, even if the clock frequency of the display clock generator deviates and the number of count pulses during the horizontal synchronization period increases, the count value to the CRT controller is sent to the CRT controller with a count value that is several pulses fewer than the clock frequency of the display clock generator. Since the sending of clock pulses is stopped, horizontal synchronization is eliminated. Note that some CRT controllers lose control constants and malfunction even after stopping the application of several pulses.
This problem is solved because the present invention includes an adjustment pulse generation circuit to shorten the stop period.

(Embodiment) Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, and Fig. 2 shows the signal waveform of the main part of Fig. 1. Parts of the waveform are indicated by the symbols shown in Fig. 1. corresponds to The present invention will be explained in detail below using these figures.

First, in Fig. 1, numeral 7 indicates a CRT controller. Parameters such as display position, display size, and display configuration on the display screen are input and set in advance from the host computer, and display address signals are sent according to the set values. a is applied to the graphics memory 8. In graphic memory 8,
A graphic screen signal b from the host computer is stored, and its readout output c is applied to an output conversion circuit 9 where parallel/serial conversion, color conversion, etc. It is sent to a video device, etc. that has a Note that the basic clock pulse l at this time is applied to the CRT controller 7 from a switching circuit 13, which will be described later.

On the other hand, 10 is a synchronization separation circuit that separates a frame synchronization signal fa and a horizontal synchronization signal ga from the external video signal e. Reference numeral 11 is a display clock generation circuit which receives the horizontal synchronization signal ga separated by the synchronization separation circuit 10 in the previous stage and generates a synchronization frequency of 15.75kHz.
A 12.5MHz display clock h is created by multiplying by an integer, and the phase is also matched using the PLL method. 12 is a counting circuit which controls the above display clock h.
After counting 790 times, the gate switching signal k is applied to the switching circuit 13 and the basic clock pulse l is applied.
After about 800〓, the adjustment pulse generation circuit 14, which received the gate switching signal k at the same time, stops after about 300〓,
A pulse j having a pulse width of about 200 mm is sent to the switching circuit 13 and added directly to the basic clock pulse l. This basic clock pulse l is obtained by dividing the frequency of the display clock h into 1/2, and passes through the switching circuit 13 to the CRT controller 7.
, and the preset display parameter settings of the CRT controller 7 will establish a period that is an integral multiple of this basic clock pulse.

The switching circuit 13 and the counting circuit 12 are initialized by the horizontal synchronization signal ga for each horizontal synchronization, and the CRT controller 7 is initialized by the frame synchronization signal fa from the synchronization separation circuit 10.

As is clear from the above description of the present invention with reference to one embodiment, the present invention not only allows the CRT controller 7 to synchronize with the frame synchronization signal, but also allows the counting circuit 1
2. Due to the operation of the switching circuit 13 and the adjustment pulse generation circuit 14, the number of basic clock pulses is always constant during the horizontal synchronization period and is also synchronized with the horizontal synchronization signal. Synchronizable character and graphic signals can be extracted from the outside. Furthermore, since the present invention allows a large frequency tolerance of the display clock generating circuit, the number of man-hours required for adjusting the device is reduced.

(Effects of the invention) As can be seen from the above explanation, the invention has the following effects when implemented. (a) Since general graphics memory and general-purpose CRT controllers can be used, the device can be made compact and manufactured at low cost. (b) Since the frequency tolerance of the display clock generation circuit is large, manufacturing adjustments are easy. (c) general purpose
Since the CRT controller can be used as an assembly, the number of parts is reduced and reliability is increased. Furthermore, since a general-purpose CRT controller is used, character/figure signal generators with different frequency sweep methods can be easily designed.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a character/figure signal generator according to an embodiment of the present invention, FIG. 2 is a waveform diagram of the main part of FIG. 1, and FIG. 3 is a configuration of a conventional character/figure signal generator. FIG. 1... Display address control circuit, 2, 8... Graphic memory, 3, 9... Output conversion circuit, 4, 10...
Synchronous separation circuit, 5, 11...Display clock generation circuit, 6...Control signal generation circuit, 7...CRT controller, 12...Counting circuit, 13...Switching circuit, 14...Adjustment pulse generation circuit.

Claims (1)

[Claims] 1. In a character/graphic signal generator that has a graphics memory that stores graphic information from a host computer, a parallel/serial conversion circuit for its output, and a CRT controller that allows external synchronization by frame synchronization, synchronization is achieved from an external video signal. A synchronization separation circuit that separates signals, a display clock generation circuit that generates a display clock pulse having an integral multiple of the frequency of the separated synchronization signal, a counting circuit that counts the period during which the clock pulse is applied to the CRT controller, and A switching circuit that stops applying the above clock pulse when a predetermined value is counted, and a CRT that controls the stopping period.
What is claimed is: 1. A character/graphic signal generating device, comprising: an adjustment pulse circuit for terminating the process within a period allowed by a controller, and generating a character/graphic signal to be superimposed on an external video signal image.