JPS6153880A - Display and control device of character picture - Google Patents

Abstract

PURPOSE:To make a phase interval between a horizontal synchronizing signal and a clock pulse equal and to eliminate the dislocation in a raster scan type device by initializing a character clock with the aid of an external horizontal frequency signal beforehand. CONSTITUTION:A clock pulse CLK generated in a clock generator circuit is initialized by a horizontal synchronizing signal Hsync inputted outside in a frequency divider 241, and supplied as a count clock to a horizontal counter 211 and a memory address counter 231. Thus the time interval between the fall edge of the horizontal synchronizing signal Hsync and the rise edge of the next clock pulse CLK is made equal in the minimum units at the frequency divider 24a and the display dislocation hardly occurs, because in terms of the rise edge of the horizontal synchronizing signal the clock pulse is provisionally stopped to be at ''L'' level, and the action of a frequency divider circuit is again resumed from the fall edge of the horizontal synchronizing signal Hsync.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a character image display control device, and in particular to a character image display control device that enables external synchronization with a simple configuration and minimizes display deviation on the screen. Regarding equipment.

[Conventional technology]

Character image display control devices currently used in micro combinator systems or personal combinator systems, etc., and built into CRT display devices, etc.
In other words, the CRT controller normally performs a display operation at a scanning period specific to each device.

FIG. 4(,) shows the configuration of a video system including this type of CRT controller.
For example, 8-bit data is read out in parallel for each address from the video RAM 3 controlled by the ff controller 2, and is converted into a serial video output signal by the parallel serial conversion circuit 4 and sent to the CR. 'r5 is supplied.

The CRT controller 2 and the parallel serial conversion circuit 4 are each supplied with clock and clock pulses from an external clock generation circuit 7 via a frequency dividing circuit 8. In this case, the CR
The frequency of the clock pulse (so-called character clock) supplied to the T controller 2 is determined by the frequency dividing circuit 8.
? The frequency of the clock pulse (so-called dot clock) supplied to the parallel serial conversion circuit 4 is, for example, 100,
Data transmission from each of these clocks and legs is controlled by the CRT controller 2, and the horizontal synchronizing signal HIIY)ic and vertical synchronizing signal V8YNC, which are formed based on the clocks and legs, are sent to the CRT controller 2.
5, and a display operation is performed at a predetermined scanning cycle.

Therefore, when displaying an image signal from a television W/device, an image signal from a video device, and character image information, etc. from a microcomputer system or a sonal combinator system on the same screen,
It is necessary to perform so-called external synchronization to synchronize the display scanning cycle on the CRT controller side with the scanning cycle of the television set.

As a means for this purpose, a conventional multi-phase fixed circuit (P
LL circuit) is used to create a clock/IP pulse synchronized with the horizontal synchronizing signal sent from the television set and supply it to the CRT controller. However, this method has disadvantages in that the circuit size is large, the device configuration is complicated, and synchronization takes a long time.

Therefore, the present applicant first proposed a relatively simple idea in this kind of character image display control device, in which both the horizontal counter and the vertical counter are initialized by an external synchronization signal every horizontal scanning period and every vertical scanning period, respectively. We proposed that external synchronization be achieved through a device configuration that would shorten the synchronization pull-in time.

FIG. 4(b) shows the configuration of a video system using such a CRT controller, in which a horizontal synchronizing signal H8YNC and a vertical synchronizing signal V8Y from the television set 6 are shown.
NC is input to the CRT controller 2, and as described later, a horizontal counter and a vertical counter in the CRT controller 2 are initialized for each horizontal scanning period and each vertical scanning period by these synchronizing signals.
The controller 2 is configured to access the video RAM 3 in synchronization with each synchronization signal from the television camera device 6.

FIG. 3 shows a specific example of the configuration of the CRT controller used in the system shown in FIG. 4(b), especially the synchronous circuit part. By making one of them conductive, the horizontal synchronizing signal H
Switching between a mode in which 8YNC and vertical synchronization signal VIIYNC are output, that is, a mode in which the CRT display operation is performed at a cycle specific to the CRT controller, and a mode in which each of these synchronization signals is input from a television set, etc., in other words, a mode in which external synchronization is performed. is made possible.

First, in the former mode, that is, the mode in which each synchronization signal is output, the clock pulse CLK sent from the clock generator circuit 7 through the frequency divider circuit 8 shown in FIG. 23
1 as a count clock and are counted. The output of the horizontal counter 211 is input as count data to the comparator 213, and the horizontal period setting circuit 2
It is compared with the horizontal period setting value output from 12.

In addition, the output of the horizontal counter 211 is output from the horizontal synchronization generation circuit 21.
When the count value of the counter reaches a predetermined value, a horizontal synchronizing signal) (gyNc) is formed and sent to the CRT via the tri-state buffer 215.

Further, when the count value outputted from the horizontal counter 211 matches the horizontal period setting value outputted from the horizontal period setting circuit 212, the comparator 213 outputs one base pulse, and this i
The horizontal counter 211 is reset by the fourth pulse, and the *9 pulse is inputted to the vertical counter 221 as a count clock and counted. The output of the vertical counter 221 is input as count data to a comparator 223 and compared with the vertical cycle setting value output from the vertical cycle setting circuit 222.

Also, the output of the vertical counter 221 is output from the vertical synchronization generation circuit 22.
When the count value of the counter reaches a predetermined value, a vertical synchronizing signal VmYNC is formed and sent to the CRT via the tri-state buffer 225.

Furthermore, when the count value outputted from the vertical counter 221 matches the vertical period setting value outputted from the vertical period setting circuit 222, the comparator 223 outputs one nollus, and the vertical counter 221 is reset by this noyalse. .

Further, when both the comparators 213 and 223 output match signals, the memory address counter 231 is reset by the memory address counter control section 232. This causes the memory address counter 231 to read 1 of the video RAM.
Address signals ADD for accessing areas for storing image information for a screen are sequentially output.

Next, in the latter mode, that is, a mode in which external synchronization is performed using a synchronization signal from a television device, etc., the control signal CNT is set to L level and the tri-state buffer 2 is
15 and 225 are turned off, and tristate buffers 216 and 226 are turned on.

As a result, the horizontal and vertical synchronization signals from the television set are inputted to the horizontal synchronization position generation circuit 217 and the vertical synchronization position generation circuit 227 via the tristate buffers 216 and 226.

The horizontal synchronization position generation circuit 217 and the vertical synchronization position generation circuit 227 output the horizontal synchronization signal and vertical synchronization signal to the horizontal counter 211 and the vertical counter 221, respectively, when the horizontal and vertical synchronization signals are input from the television device. Load position. As a result, the horizontal counter 211 and the vertical counter 221 are set to predetermined count values at the positions of the horizontal and vertical synchronizing signals, respectively. In other words, both the horizontal counter and the vertical counter are initialized at each horizontal scanning period and vertical scanning period, respectively, and perform counting at a period synchronized with each synchronization signal of the television set.

In this way, the device shown in FIG. 3 enables external synchronization with a relatively simple configuration and can superimpose image signals from a television program. Because there is no phase synchronization between the horizontal synchronizing signal from the CRT controller and the clock pulses (supplied from the clock generation circuit) on the CRT controller side, a display shift occurs in the minimum display unit of the CRT controller. There was a problem in that the characters displayed on the television screen were misaligned (a sawtooth pattern) as shown in FIG. 6 (,).

[Problem that the invention seeks to solve]

The present invention has been made to solve the above problems,
By further improving the character image display control device capable of external synchronization as shown in FIG. This is to make the deviation so small that it can be ignored.

[Means for solving problems]

According to the present invention, a horizontal counter that counts clock pulses and a vertical counter that counts pulses that are output when the counted value of the horizontal counter matches a predetermined set value are provided, and the outputs of the horizontal counter and the vertical counter are In a raster scan type character image display control device that regulates a horizontal scanning period and a vertical scanning period, respectively, means for initializing the horizontal counter and the vertical counter for each horizontal scanning period and vertical scanning period, respectively, by an external synchronization signal; A character image display control device is provided, comprising means for pre-initializing a clock pulse supplied to the horizontal counter for each horizontal scanning period by a horizontal synchronizing signal from the outside.

[Effect]

In the above device, the phase interval between the horizontal synchronization signal and the clock pulse for each raster can be adjusted by initializing the clock pulse, that is, the character clock supplied to the horizontal counter, with the horizontal synchronization signal input from the outside. They can be arranged at almost constant intervals, and the deviation in character image display by this type of character image display control device, ie, CRT controller, is so small that it can be ignored.

〔Example〕

FIG. 1 shows the configuration of a character image display control device, that is, a CRT controller, as an embodiment of the present invention, in comparison with that of FIG. 3, and the differences from that of FIG. 3 are as follows.
A clock initialization circuit 24 is provided in which the clock signal CLK supplied from the clock generation circuit in the external synchronization mode is initialized by the horizontal synchronization signal H8YNC inputted through the tristate buffer 216.
The point is that the output of the clock initialization circuit 24 is supplied to the horizontal counter 211 and the memory address counter 231 as a count clock.

FIG. 2 shows a specific example of the clock initialization circuit 24. In FIG. 2 (,), the clock pulse CLK generated in the clock generation circuit is Or, as mentioned above, with a counter that divides the frequency of 0 Tsukunorusu by 100, for example,
(corresponding to the frequency divider circuit 8 in FIG. It is supplied to the address counter 231.

FIG. 5 shows the horizontal synchronization signal)fsyNc and the character clock CLK, !, which is supplied to the CRT controller 2. :
(1) is a horizontal synchronizing signal input to a CRT controller from a television set or the like for each raster. (b) shows the clock frequency supplied from the clock generation circuit, which is simply frequency-divided without any initialization.
The case where the clock is initialized as described above according to the present invention is shown in (,), and the clock is supplied to the controller.
The case where it is supplied to the controller is shown.

As is clear from the figure, clock initialization is not performed (b
), the horizontal synchronization signal HIYNC is applied for each raster.
The time interval between the falling edge of the clock and the rising edge of the next clock pulse changes sequentially as tl * j snow +..., and as a result, the characters displayed on the C17 screen are changed for each raster. A slight shift occurs, resulting in a sawtooth pattern as shown in FIG. 6(a).

In contrast, clock initialization is performed as in the present invention (c)
In this case, at the rising edge of the horizontal synchronizing signal, the clock signal is temporarily stopped and set to L level, and the operation of the frequency dividing circuit is resumed from the falling edge of the horizontal synchronizing signal. The time interval between the falling edge of the horizontal synchronizing signal and the rising edge of the next black pulse is made to be the same in the minimum unit of the divider. They are shown as being aligned at a time interval t. Therefore, as shown in FIG. 6(b), the characters displayed on the CRT screen do not suffer from any display shift, similar to when the above-mentioned PLL circuit is used.

However, as mentioned above, there is still the possibility of display deviation due to an error in the minimum unit of the splitter, but the display deviation caused by this is extremely small and does not pose any visual problem. In this case, increase the frequency of the clock generator (oscillator) by 2 times, 4 times, etc., and apply □ to the divider.
Therefore, by setting the frequencies to ■, ■, . . . , it is possible to further reduce the value of the minimum unit of the divider, thereby further reducing display deviation.

Further, FIG. 2(b) shows a second specific example of the black and red initialization circuit used in the present invention, in which the black and red signals are supplied from the black and red generation circuit (after being divided by a divider as necessary). )
The clock pulse CLK is passed through a phase circuit 242 (actually constituted by, for example, a delay line) to obtain various phases φl, φ2, . . . φ. The selection circuit 2 outputs those having
43, the horizontal synchronizing signal HIIYN(!) from the external device is input for each raster, so that the count clock is kept at Low level, and during that period, among the clock pulses having various phases, Using the falling edge of the horizontal synchronizing signal as a reference, only the clock pulse with the phase closest to it is selected and outputted as a count clock to the CRT controller.

As shown in the above two specific examples, by providing an initialization circuit inside or outside the CRT controller, in the external synchronization mode, the horizontal The phase interval between the synchronization signal and the clock/master pulse sent from the clock generation circuit can be made almost constant, and the above-mentioned display deviation problem can be avoided without using a complicated circuit configuration such as a PLL circuit. can be resolved.

〔Effect of the invention〕

According to the present invention, so-called external synchronization can be achieved with a relatively simple configuration without using a PLL circuit or the like.
This allows the image signal from the television viewing device to be connected to the CRT.
It is possible to display character image information from the controller side in a superimposed manner on the same screen, and furthermore, it is possible to visually display the character image information from the CRT controller side as being so minute that it can be ignored. can solve the problem.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a character image display control device as an embodiment of the present invention, and FIG.
) is a block diagram showing a specific example of the configuration of the black and white initialization circuit in the apparatus shown in FIG. 1, and FIG. 4(a) and 4(b) are block diagrams showing a video system using this type of character image display control device, and FIG.
The figure is a diagram illustrating the operation of the character image display control device according to the present invention in comparison with that according to the prior art, and FIGS. 6(a) and 6(b) show the case where the character image display control device according to the present invention is used. FIG. 3 is a diagram illustrating a displayed image in comparison with a case using the prior art. (Explanation of symbols) 1...CPU, 2...CRT controller, 3
...Video RAMX4.../? parallel serial conversion circuit, 5...CRT. 6...Telepino string device, 211...Horizontal counter, 212...Horizontal period setting circuit, 213...Comparator, 214...Horizontal synchronization generation circuit, 215.216...
- Tri-state buffer, 217...Horizontal synchronization position generation circuit, 221...Vertical counter, 222...Vertical layer period setting circuit, 223...Comparator, 224...Vertical synchronization generation circuit, 225. 226... Tri-state buffer, 227... Vertical synchronization position generation circuit, 231
. . . Memory address counter, 232 . . . Memory address counter control unit, 24 . . . Clock initialization circuit, 241 .

Claims (1)

[Claims] 1. A horizontal counter that counts clock pulses and a vertical counter that counts the pulses that are output when the count value of the horizontal counter matches a predetermined setting value, and the horizontal In a raster scan type character image display control device that regulates a scanning period and a vertical scanning period, means for initializing the horizontal counter and the vertical counter for each horizontal scanning period and vertical scanning period, respectively, by an external synchronization signal, and from the outside 1. A character image display control device comprising means for initializing in advance a clock pulse supplied to said horizontal counter for each horizontal scanning period by a horizontal synchronizing signal of said character image display control device.