JPH0553997A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide the microcomputer which can immediately deal with an interruption processing request. CONSTITUTION:A starting device 1 receiving an interruption request signal 101 selects and starts a central processing unit 4, for example, under stopping among central processing units 3 and 4. The other central processing unit 3 under operating continues an operation processing under processing at present without being stopped by inputting the interruption request signal 101. The central processing unit 4 started by the interruption request signal 101 is stopped by a stopping device 2 when there is no newly required processing operation condition after the interruption processing is completed. A storage device 5 is shared by the central processing units 3 and 4, and stored data are utilized at both central processing units 3 and 4 as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer.

[0002]

2. Description of the Related Art A conventional microcomputer is generally composed of an interrupt control circuit and a single central processing unit. In the case of this conventional microcomputer, when an interrupt request occurs in the process of executing the normal arithmetic processing in the central processing unit, the normal processing is temporarily suspended after the execution of the normal processing. Then, interrupt processing is executed using the same central processing unit. Therefore, a corresponding switching time is required at the time of switching from the normal processing to the interrupt processing or at the time of switching from the interrupt processing to the normal processing.

[0003]

In the conventional microcomputer described above, since the normal processing and the interrupt processing are executed by using the single central processing unit, the actual processing is performed after the interrupt request is generated. The time required for switching is required before interrupt processing is executed, and it is difficult to respond immediately even when high-speed response is required. Since the time until the interrupt processing is executed is not constant, it is impossible to execute the processing at accurate time intervals.

[0004]

A microcomputer according to the present invention is a microcomputer configured by being arranged on the same semiconductor circuit element, wherein a plurality of central processing units functioning as a processing unit and an interrupt input from the outside are provided. An interrupt processing control unit that receives a request signal and controls the execution of interrupt processing by the stopped central processing unit of the plurality of central processing units, and the operation stop after the end of the interrupt processing, and the plurality of central processing units. And a storage device shared by the devices.

The interrupt processing control means receives an interrupt request signal input from the outside, selects a stopped central processing unit among the plurality of central processing units, and responds to the interrupt processing. It may be configured to include a starting means for starting and a stopping means for stopping the operation of the central processing unit which is started by the starting means and ends the processing corresponding to the interrupt request signal.

Further, the interrupt processing control means receives an interrupt request signal inputted from the outside, selects one central processing unit from the plurality of central processing units, and starts up corresponding to the interrupt processing. May be provided, and an arbitrary central processing unit that selects and starts another stopped central processing unit in response to the starting instruction.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, in response to the interrupt request signal 101, the starting device 1 and the stopping device 2 are connected.
, Central processing unit (A) 3 and central processing unit (B) 4
And a storage device 5.

In FIG. 1, the activation device 1 receives the interrupt request signal 101, and selects one of the central processing units (A) 3 and 4 which is in a stopped state. Then, the central processing unit is activated. For example, when the central processing unit (A) 3 is operating and the central processing unit (B) 4 is stopped, the central processing unit (B) 4 is selected and activated by the activation device 1. It
Therefore, the other central processing unit in operation is not stopped by the input of the interrupt request signal 101, and the arithmetic processing currently being processed is continued. In this case, the central processing unit activated by the interrupt request signal 101 is stopped by the stop device 2 after the completion of the interrupt processing, if there is no newly required processing operation condition.
The storage device 5 is a storage device shared by the central processing units (A) 3 and (B) 4, and the stored data is also used by both central processing units.

Further, suppose that the central processing unit (A) is in operation.
When the activation device 1 issues a activation request to the device 3,
Central processing unit (B) which is stopped from the central processing unit (A)
4 is instructed to start, the central processing unit (B)
4 is activated. In this case, when the interrupt processing in the central processing unit (B) 4 is completed, the central processing unit (B) 4 informs the central processing unit (A) 3 that the processing is completed, and the central processing unit (A) 3 A) 3 stops the central processing unit (B) 4 via the activation device 2 in response to the end of the processing. On the contrary, the interaction in the central processing unit is the same when the starting device 1 requests the central processing unit (B) 4 in operation. The central processing unit (A) 3 is activated from B) 4.

[0011]

As described above, according to the present invention, by providing a plurality of central processing units, even when an interrupt request occurs, high-speed response is possible without stopping the operation processing currently in operation. There is an effect that it is possible to execute a highly efficient arithmetic process.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Starter 2 Stopper 3 Central Processing Unit (A) 4 Central Processing Unit (B) 5 Storage Device

Claims (3)

[Claims] 1. A microcomputer configured to be arranged on the same semiconductor circuit element, wherein a plurality of central processing units functioning as a processing unit and an interrupt request signal input from the outside are received, and the plurality of central processing units are operated. An interrupt processing control means for controlling the execution of interrupt processing by the central processing unit that is stopped in the apparatus and the operation stop after the completion of the interrupt processing; and a storage device shared by the plurality of central processing units. A microcomputer characterized in that. 2. The interrupt processing control means receives an interrupt request signal input from the outside, selects a stopped central processing unit among the plurality of central processing units, and responds to the interrupt processing. 2. The microcomputer according to claim 1, further comprising: a starting unit for starting and a stopping unit for starting the operation of the central processing unit which has been started by the starting unit and finished the processing corresponding to the interrupt request signal. 3. The interrupt processing control means receives an interrupt request signal input from the outside, selects one central processing unit from the plurality of central processing units, and starts up corresponding to the interrupt processing. 2. The microcomputer according to claim 1, further comprising: a start-up unit for instructing, and an arbitrary central processing unit for selecting and starting another stopped central processing unit in response to the starting instruction.