JPH0548668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an apparatus for recording television video signals and displaying and reproducing them as still images.

(b) Prior art As a device for recording and reproducing television video signals, for example, as described in the magazine "Television Technology", January issue, 1984, pages 20 to 30, there are devices that record and reproduce television video signals. There is a system in which a video signal for one field is stored in a storage device, read out repeatedly in a field period, and a still image is reproduced by interlaced scanning. Since the lines are displayed shifted up and down by one line, the image vibrates minutely and is reproduced as a screen that is extremely difficult to see. In addition, as another conventional example, as described in "Television Society 1982 National Conference Lecture Proceedings, P.425-P.428,
There is a method that stores one frame's worth of television video signals in a storage device and repeats the operation of sequentially reading out the signals to obtain a still image using interlaced scanning.
When a frame is recorded and reproduced, the image of a moving part of the reproduced still image is duplicated, which not only results in a screen that is difficult to change, but also requires a large capacity of the storage device used for it.

(c) Problems to be Solved by the Invention The present invention attempts to make it possible to obtain good still images while using less storage capacity.

(d) Means to solve the problem One field of television video signal is written to the storage device, and the video signal information of each line of this written one field is written at twice the writing speed. The storage device is controlled by the control means so that the operation repeated twice is repeated a plurality of times for one field.

(e) Effect By configuring as described above, a still image is reproduced in which the field frequency is the same as in the case of the interlaced scanning method and the number of lines is doubled.

(F) Embodiments Examples of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows a block circuit diagram of the still image recording and reproducing apparatus of the present invention, in which 1 is an A/D converter (analog-to-digital converter), 5 is a serial-to-parallel converter,
2 is a storage device such as a semiconductor memory, 6 is a parallel-to-serial converter, 3 is a D/A converter (digital-to-analog converter), 7 is a synchronous separation circuit, 8 is a phase comparison circuit, 9
is a voltage controlled oscillator circuit (VCO), 4 is a counter,
10 is an address generator composed of a counter, etc., 11 is a mode controller, and the storage device 2 is configured such that when N is the smallest integer larger than the ratio of the vertical scanning period to the horizontal scanning period of the input video signal, It is configured to have addresses for N lines.

The interlaced scanning composite video signal a after detection supplied from the outside is input to the A/D converter 1, where it is quantized by the sampling clock G given from the counter 4 and converted into parallel data. b is inputted to the serial/parallel converter 5 by the timing signal h. This converter 5 converts a serial signal into a parallel signal to suit the operating speed of currently available general-purpose dynamic memories, etc., thereby reducing the data transmission speed. The data slowed down in this manner is supplied to the storage device 2 by a timing pulse i, and an address data signal k that specifies the address of this storage device 2 and a write/read control signal (hereinafter referred to as "W/R signal"). ) j, and the written data is read out using the address data signal k and the W/R signal j. Details of the write and read operations of the storage device 2 and the changing operation of the write and read operations by the mode controller 11 will be described later.

The parallel data d output to the storage device 2 is
The data that is supplied to the parallel-to-serial converter 6 and parallel-to-serial converted there by the timing signal lm is converted into an analog signal in the D/A converter 3, and a video signal f whose horizontal frequency is twice that of the interlaced scanning method is generated. It is supplied to display devices such as CRTs.

On the other hand, the composite video signal a is also input to a sync separation circuit 7, and the circuit 7 extracts a horizontal sync signal o and a vertical sync signal n. This vertical synchronizing signal n is supplied to a vertical deflection circuit (not shown) and an address generator 10 of the display device. Further, the horizontal synchronization signal o
is supplied as one input to the phase comparator circuit 8,
The signal output from the VCO 9 is supplied to the counter 4 as a main clock signal, and the output signal r obtained by frequency-dividing the output s of the counter 4 by the address generator 10 is supplied as the other input of the phase comparator 8, A comparator 8 compares the phase with the horizontal synchronizing signal o. The output p obtained from this comparison result is then used as the control signal.
Supplied to VCO9. Due to the phase control loop (PLL) formed in this way, the VCO 9 operates as an oscillator that oscillates at a predetermined frequency that is in phase with the horizontal synchronization signal o, and thereby the divided output r is synchronized with the external synchronization signal o. This results in an internal synchronization signal with the same phase. Note that the address generator 10 outputs a signal t having twice the frequency of the external horizontal synchronization signal o, and this signal t is supplied as a horizontal synchronization signal to a horizontal deflection circuit (not shown) of the display device. The mode controller 11 applies control signals U and V to the storage device 2 and the address generator 10, respectively, in response to a mode switching signal w applied from the outside, and changes the manner in which addresses are generated. Set to one of the modes.

Next, an explanation of the operation of the device of this embodiment is given in Figures 2 to 4.
This will be explained with reference to the timing chart shown in the figure.

In Figures 2 to 4, A schematically shows a video signal waveform transmitted in the 2:1 interlaced scanning method, where the period H is one horizontal scanning period in the interlaced scanning method, and the period V is one vertical scanning period. During the scanning period, Hs indicates the horizontal synchronization signal, Vs indicates the vertical synchronization signal,
To simplify the explanation, the waveform of the vertical synchronizing signal is shown very schematically, and the ratio of the horizontal and vertical scanning periods is selected to be very small, 1:7.5.
The 2:1 interlaced scanning condition is satisfied, and in this case, two vertical scans, that is, two fields constitute one screen consisting of 15 scanning lines.

In addition, in FIGS. 2 to 4, B is a diagram showing the operation timing of the storage device 2, where the solid line shown in bold indicates the timing of writing data in the storage device 2, and the broken line shows the timing of reading data. It shows.

Next, the present apparatus will be explained separately in a scan conversion mode and a still image recording/reproducing mode.

() Scan conversion mode A mode switching signal w given from the outside instructs the scan conversion mode, and when this signal is applied to the mode controller 11, the controller 11 generates signals U and V, as shown in FIG. Operate the storage device as follows.

That is, the write operation of the storage device 2 is performed by writing the smallest integer larger than the ratio of the vertical scanning period to the horizontal scanning period of the input video signal to N (in this case, N=8).
As a result, the addresses of the storage device for eight runs are circulated, and the video signal information for each line of each field of the input video signal is sequentially written. On the other hand, to explain the read operation of the storage device 2 by taking the To (= 1H) period in FIG. 1 of the storage device.
While writing to the address for a line, 1H worth of video signal information b of the previous field (second field) that has already been written to the address for this one line is read out in the first half 1/2H, and then The video signal information C' written in the period To is read out in the latter half 1/2H. At this time, reading is performed at twice the writing speed. Since the memory device is controlled so that such an operation is repeated, the signals read out during the T1 period, for example, are b-c'-c-d'-d-e', and the signals of the two fields are The signals of each line are read out alternately every 1/2H and compressed on the time axis, thereby doubling the number of lines while keeping the field frequency the same as in the case of interlaced scanning (i.e., the number of lines is doubled (i.e., the number of lines is doubled). ) It is possible to obtain progressive scanning television video signals.

A high-definition image whose number of lines is doubled by being scan-converted in this manner is used, for example, as a monitor image when recording a still image.

() Still image recording and reproducing mode A mode switching signal w given from the outside instructs the still image recording and reproducing mode, and when this signal is applied to the mode controller 11, the signals U, which are generated from the controller 11,
V causes the storage device 2 to change from the scan conversion mode to the still image recording and reproducing mode as shown in FIG. 3 or 4.

As shown in FIG. 3, for example, when a signal instructing the still image recording/reproducing mode is generated at timing S in the first field, the storage device changes from the conventional scan conversion mode as follows.

First, the write address generated from the address generator 10 is initialized once at timing _R1 by the horizontal synchronization signal that is present after the vertical synchronization signal of the second field.
At the end of writing one field's worth of video signal information corresponding to one cycle of all addresses to the storage device 2 (timing E in FIG. 3), the writing operation of the storage device 2 is stopped. Note that stopping the write operation in this case simply means stopping the storage of data (video signal information), and the writing address is incremented cyclically with 8 lines as one cycle period.

On the other hand, for read addresses, the phase of the vertical synchronizing signal is 1/2H equal to the horizontal scanning period, as shown in Figure 3.
In the shifted field (second field), it is initialized at the center c of the horizontal scanning period 1H after the end of the vertical synchronization signal (timing R ₂ in Fig. 3), and as shown in the figure, the same line that has already been written is The operation of repeatedly reading out the video signal information twice at twice the writing speed is cyclically repeated multiple times in the cycle period of the storage device.

For example, to explain the operation of the storage device using period _{T 4} in _FIG . In 1/2H of the first half of period T ₃ , the operation of reading out the information a' written in period T ₂ is repeated, so the information on the same line is read out twice each time. be. Of course, in this case as well, each signal is read out after being compressed on the time axis.

Note that the next 1H period of the vertical synchronization signal V's is read out only once, but in the actual NTSC system, the horizontal period near the vertical synchronization signal does not contain valid video signal information ( In other words, it corresponds to the vertical blanking period), so there is no substantial problem in doing so.

Next, as shown in FIG. 4, when a signal instructing the still image recording/reproducing mode is generated at timing S' in the second field, the storage device 2 changes from the previous scan conversion mode as follows.

That is, as can be seen from this figure, the write operation of the storage device 2 is similar to the above case, and the write address generated from the address generator 10 is first generated by the horizontal synchronization signal that is present next to the vertical synchronization signal of the first field. It is initialized once at timing _R3 . Then, for the storage device 2,
At the end of writing video signal information corresponding to seven lines (timing E in FIG. 4), the writing operation of the storage device 2 is stopped.

On the other hand, in the field (first field) where the phase of the vertical synchronization signal matches the horizontal scanning period as shown in FIG.
Unlike the case shown in the figure, the read address is initialized at timing R ₃ by the horizontal synchronization signal that follows the vertical synchronization signal, and the information written between t ₀ and _{t 1} is transferred to t After _1, the operation of reading each line twice at twice the writing speed is repeated multiple times for one valid field of video signal information written in the storage device. be.

In this still image recording and reproducing mode, in the case of FIG. 4, only seven lines of video signal information were written, but there is no problem in doing so. This is because in the actual NTSC system, the horizontal period following the vertical synchronization signal does not contain valid video signal information (that is, it is within the vertical blanking period), and even in the case of Fig. 3, You may do so. If the storage device is used only in the still image recording/playback mode, the storage capacity is such that only the number of lines containing valid video signal information in one field can be written, and the information can be read out twice at a time. You may perform this repeatedly.

As described above, the video signal information read out after compressing the time axis has the same field frequency as in the case of interlaced scanning, the number of lines in one field image is doubled, and the same is true for the vertical synchronization signal. The image is reproduced as a high-definition still image at the same position on the display device.

As mentioned above, changing from the scan conversion mode to the still image recording/playback mode requires only a slight change in the manner in which addresses are generated, as can be seen from the timing diagrams in Figures 3 and 4, so such a change can be easily realized. I know what I can do. Further, although a detailed explanation will not be given, it is easily understood that the change from still image recording/reproducing mode to scan conversion mode can be restarted in the same manner.

In the case of FIG. 4, the information read in the first half of each run-in from t ₀ to t ₁ becomes information before t ₀ , and the contents of the instantaneous still image are disturbed, so the mode switching operation is performed in the third step. It is desirable to perform this in the second field as shown in the figure, and therefore it is better to provide the circuit of FIG. 1 with a field discriminator to automatically record and reproduce still images in the second field.

In addition, by intermittently performing the still image recording and reproducing operation as described above, it is possible to perform special effects such as so-called strobe action, and furthermore, it is possible to perform special effects such as so-called strobe action. It is also possible to output the information) to a printing device (printer) or the like.

In this embodiment, the case where one signal series is processed has been explained, but when there are multiple signal series such as a luminance signal and a color difference signal, such as a color television, the above-mentioned operation is performed for each series. You can configure it like this.

(G) Effects of the Invention According to the present invention, since the display content of the still image is a field image and its display position is fixedly at the same position on the screen of the display device, good still images can be reproduced. This has the advantage that the storage capacity of the storage device used for it can be reduced.

[Brief explanation of the drawing]

All drawings relate to the present invention,
FIG. 1 is a block circuit diagram showing one embodiment of the present invention, and FIGS. 2, 3, and 4 are diagrams for explaining its operation, respectively. 1...A/D converter, 2...Storage device, 3...
D/A converter, 4...Counter, 5...Series-parallel converter, 6...Parallel-serial converter, 7...Synchronization separation circuit, 8...Phase comparator, 9...Voltage controlled oscillator, 10 ...Address generator, 11...Mode controller.

Claims (1)

[Scope of Claims] 1. A storage device having an address capable of storing one field's worth of video signal information, and a control means for controlling writing and reading of this storage device, wherein the control means controls the storage of one field's worth of video signal information. writing video signal information to the storage device, and
The video signal information of each line for one field written in this storage device is repeatedly read twice at twice the writing speed, and the operation is repeated multiple times for one field. A still image recording and reproducing device which obtains a still image having the same field frequency as in the interlaced scanning method and twice the number of lines from each line of video signal information obtained.