JPS63287279A - Drive method for picture memory - Google Patents

Abstract

PURPOSE:To reduce the clock frequency at readout by dividing a picture memory into plural blocks, writing a signal in time series at write and reading the signal from each block at readout. CONSTITUTION:A line memory 102 consists of two blocks LA, LB and the blocks LA, LB store the video information-video data for the first half and the second half of one horizontal period. In case of writing a video data, the blocks LA, LB are connected in series and the data are read in parallel at readout. Thus, even when the number of picture elements of a picture display section is increased, the picture is displayed by not increasing the frequency of the readout clock of a picture memory, the increase in the power consumption is suppressed and the design margin due to the delay by the circuit element is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving an image memory in an image display device such as a television, when an image is displayed using image information stored in the image memory.

[Conventional technology]

Currently, in image display devices such as televisions, two driving methods are becoming mainstream in which image information is digitally processed using an image memory. In conventional technology, when image information is stored in an image memory and then read out in an image memo and displayed as an image, writing and reading out the image information to and from the image memory is done in chronological order. It is carried out according to

That is, image information is written into an image memory made up of a plurality of blocks by being serially updated, and similarly, image information is read out by serially reading out the information.

FIG. 2 shows the configuration of a conventional image display device.

In FIG. 2, 201 is an A/D humbator,
Sampling the input video signal using the sampling clock φ
Sampling and A/D conversion are performed by wJL.

The A/D converted video data is transferred to line memory 202, which is an image memory, via data bus 207. The line memory 202 stores video information-video data for one horizontal period (IH). STW is the video data write start symbol, STR is the read start signal, φW is the A/D conversion sampling clock and line memory write clock, and φr is the line memory read clock. .

The video data read from the line memory (L) 202 is sent to the signal side drive circuit (DD) via the data bus 208.
) 203. Signal side drive circuit I (DD) 20
3 has a shift register inside, the shift register is started by STR, and shift data is shifted by φ. The video data that is transferred from the line memory (L) 202 in time series using the transferred shift data is output to the display unit 205 as a signal-side drive signal that drives each signal line.

Reference numeral 204 denotes a scanning side drive circuit SD, which internally includes a register. The cyst register is started by DY, and the cyst data is cysted by φy. By the shifted shift data, the scanning side drive circuit (SD) 20
4, a scanning drive signal is output to the display unit 205 for each row.

205 is a display section configured using liquid crystal or the like.

206 is a timing controller, which has a PL inside.
Built-in L circuit generates various horizontal and vertical timing signals STW, STR, φwA based on the synchronization separation signal.
, φ,,DY, outputs φa.

The operation of FIG. 2 will be explained with reference to FIG. As mentioned above, the moving image information in the video signal is stored in the line memory (L) 20.
It is written in 2. The video data is transferred from the L202 to the DD203 in the second half of the IH and the first half of the next H.

The video data written to the DD 203 is output as a signal side drive signal to the display section 205 at the next H (for example, mH video data is ++m+t)H). DD20
The signal side drive signal from No. 3 is output every 1/2H during IH.

The scanning side drive signal as shown in FIG. 4 is outputted from the 5D 204 depending on the odd field and even field. That is, a scanning side drive signal that drives the same row, for example, Y*
n is 1 for even fields than for odd fields
/2H ahead. This allows display as shown in FIG. 3.

The timings for STW, STR, φwA, and φy are shown enlarged at the bottom of FIG. 4. Writing of video data to L202 is performed during the IH period, and reading is performed during the 1/2H period. It will be done. Therefore, the frequency of the read clock φ is the frequency of the write clock φw
The frequency is approximately twice that of A.

[Intermediate points that the invention attempts to solve]

In the conventional technology, writing and reading of video data to and from an image memory is performed in a time-series manner. That is,
Image memos are used for writing and reading.

Both are done in series. Now, focusing on the writing and reading times to the image memory, as shown in FIG. 4, writing is performed during one horizontal period, and reading is performed during 1/2 horizontal period. Therefore, since the read period is approximately half the time of the write period, the frequency of the read clock φr is approximately twice that of the write clock φWJL. Therefore, as the number of pixels in the image display section increases, the readout/clock frequency increases, power consumption increases, and at the same time, the design margin for delays caused by circuit elements decreases.

In view of the above-mentioned problems, the present invention has been developed to increase the frequency of the read clock of the image memory by considering the driving method of the image memory even when the number of pixels in the image display section increases. By displaying images, the purpose is to suppress increases in power consumption and increase design margins against delays caused by circuit elements.

[Means for solving problems]

In order to achieve the above object, the present invention has the following features: (1) a)
When dividing the effective video information during one horizontal period into N blocks, b) the N4! In an image memory configured to store video information, which is divided into blocks corresponding to each of i blocks of image information, C) the image of effective video information for one horizontal period. Writing to the memory is done serially in time, and d) reading of valid video information for one horizontal period from the image memory is done in parallel in time from the N blocks constituting the image memory. A method for driving an image memory is provided.

〔Example〕

(First Embodiment) FIG. 1 is a block diagram of a first embodiment of an image display device for realizing the method for driving an image memory according to the present invention. FIG. 5 is a time chart diagram of each part of FIG. 1.

In FIG. 1, 101 is an A/D''1 inverter, which converts the input video signal into a sampling clock signal φ.
sampling and A/D conversion are performed.

The A/D converted video data is sent via a data bus 107 to a line memory (L) 10 which is an image memory.
Transferred to 2. Llo2 consists of two blocks LALB. As shown in FIG. 5, LA and LB each store video information--video data of the first half and the second half of one horizontal period (IH). LA when writing video data,
! :LBs are connected in series, and read operations are performed in parallel during reading. (Llo2 will be described in detail later.) STW is a video data write start signal, ST
R is a read start signal, and φ is a clock signal for writing and reading.

The two blocks of video data read out in parallel from Llo2 are sent to the signal side drive circuit (D
D) Transferred to 103. The DD103 is a DDA that supplies signal-side drive signals to the left half and right half of the display section 105, respectively. : Consists of DDB. The video data read from LA and LB are DDA and DDB respectively.
will be forwarded to. The DD 103 internally has a shift register, and the shift register is started by STR, and shift data is shifted by φ. The video data that is transferred from Llo2 in time series as the transferred shift data is taken into the DD 103. The captured video data is serial-parallel converted and output to the display unit 105 as a signal-side drive signal for driving each signal line.

Reference numeral 104 is a scanning side drive circuit (SD), which has a shift register inside. The shift register is started by DY, and the shift data is shifted by φY. Based on the shifted shift data, the 5D 104 outputs a scanning drive signal to the display unit 105 for each row.

Reference numeral 105 denotes a display section configured using liquid crystal or the like.

10e is a timing controller, which has a PL inside.
Built-in L circuit, various horizontal and vertical timing signals STW, STR, φ, DY are generated based on the synchronization separation signal.
, outputs φy.

The operation of FIG. 1 will be explained with reference to FIG. As mentioned above, the first half of the moving image information in the video signal (for example, mm1 (TI
l+5) A) is in LA, the second half (e.g. mB, + rn+
t) B) is written to LB. Llo, 2 to D
Transfer of video data to D103 is from LA to DDA,
Both from LB to DDB are done in the second half of the IH and the first half of the next H. The video data written in the DD 103 is serial-parallel converted, and the next H (for example, m)l video data is outputted to the display section 105 as a signal side drive signal. DD
A. The signal side drive signal output from DDB is IH leap 1/
2 hours each.

A scanning side drive signal as shown in FIG. 5 is outputted from the 5D 104 for odd numbered fields and from even numbered fields. That is,
Regarding the scanning drive signals that drive the same row, for example, Y and n, the even field precedes the odd field by 1/2H. This enables display as shown in FIG. 3.

The timings for STW, STR, and φ are shown enlarged at the bottom of FIG. Since the reading of video data from LiO2 is done in parallel from LA and LB, the reading clock can be used in common with the writing clock, and the frequency is 1/2 of φr in FIG. 4 of the conventional column. That's fine.

An example of the configuration of the line memory L102 is shown in FIG. 6
01 is a shift register for writing, which starts with a shift register start signal STW and transfers STW with a clock φ.The shift register 601 has two stages, and the outputs of the first half stages (WO to Wk -1) is LAE302, and the second half output (Wk~W* h -v) is Ln2O.
Instruct to write 3.

La2O2 and La2O2 are memories with a bit configuration of 4 bits xk words=4. (1 word consists of 4 bits)
Each word is MAOO~MAO3 or M
It is as shown in BOO to MBO3. One bit has a latch configuration such as M A 00 or MBOO, and when φ=“H”, the LSB and Do of the video data are written. With this configuration, the first half of the IH effective video information is La2
The second half is written to Ln2O3.

The output of each memory bit is clock gate 6
It is connected to 06. The clock gates 60.6 correspond to the same bits of each word.
The outputs are connected in common.

604 and 605 are read shift registers corresponding to La2O2 and Ln2O3. The shift register 04.803 starts with the start signal STR of the shift register and transfers the STR with the clock φ.The shift register 04.803 is composed of each stage, and the output of each stage becomes the clock signal of the clock gate 606. ing. That is, as the data is shifted in the shift register Ei04.805, the video data is read out from each word of La2O2 and Ln2O3, and the data is read out from each word of La2O2, Ln2O3,
Output as DBS. LAG02. Reading of video data from Ln2O3 is done in parallel. Further, writing and reading of video data to the line memory L102 can be performed independently.

(Second Embodiment) FIG. 7 is a block diagram of a second embodiment of an image display device for realizing the method for driving an image memory according to the present invention.

FIG. 8 is a time chart of the numbered part in FIG.

The video data A/D converted by the A/D converter 701 is stored in the line memory 7 consisting of two blocks, LA and LB.
02 via the data bus 707. The line memories LA and LB each store video data for every other pixel, as shown in the video signal at the top of FIG. LA stores video data for odd-numbered pixels, and LB stores video data for even-numbered pixels.

The video data read from the line memories LA and LB are supplied to the signal side drive circuits (ODA) 703 and (DDB) 704'' via data buses 708 and 709, respectively. The input video data is serial-parallel converted and displayed on the display section 7.
A signal side drive signal is supplied to 06. DDA703. D
The DE 704 drives odd and even columns of the display section 708 in response to the supplied video data. Further, a scanning side driving circuit (SD) 705 supplies a scanning side driving signal to a display section 706 .

, 710 is a timing controller that generates various timing signals STW to φy based on the synchronization separation signal. The function of each signal is the same as in the first embodiment.

Next, the operation of the circuit shown in FIG. 7 will be explained based on FIG. 8. LA has video data of mA for each odd numbered pixel, 1m+1)A, and LBE has mB for even numbered pixels.

(Video data of m÷s+B is written. L702
The video data is transferred from the IH to the DDA 703 and DDB 704 in the second half of the IH and the first half of the next H. The transferred video data is serial-parallel converted and then
(mH video data is output at in++++H) to the display unit 706 as a signal side drive signal. DDA7
03, DDB704 outputs a signal side drive signal based on the same video data in 1/2H increments during IH (in +m+++H, mA and mB are output in 1/211 increments).On the other hand, from 5D705 In odd-numbered and even-numbered fields, the scanning side drive signal is outputted at a timing 1/2H earlier in the even-numbered field. As a result, in the odd field, mH video data is transferred to the Ygn-1 row, +m+*+H video data is transferred to the YI n row, and in the even field, mH video data is transferred to both the Y*T+ + 1 row and the YIT1 row. The display shown in FIG. 3 becomes possible.

Next, the writing and reading of video data in L702 will be explained from the timing of STW, STR, and φ. As shown in the time chart at the bottom of Figure 8, L702 is LA,
It is divided into LB and two blocks, and the reading of the video data is done in parallel, so the clock signal at that time can be the same φ as when writing.
The frequency is only 1/2 of φ in the figure.

An example of the configuration of the line memory L702 is shown in FIG. 9
01 is a shift register for writing, which is started by a shift register start signal STW, and STW is transferred by a clock φ. Each output We, W, of the shift register 901
, . . . Weng wHn-1+ . . . are supplied to each word of the line memory 902. Each word of the line memory 902 is composed of 4 bits, and each bit is composed of a latch as shown by MAoo. In each word, bit signals of the same video data are connected to bits of the same weight. DO to D3 are 4-bit video data.

For each word, the output of the shift register 901 is clocked φ
The line memory 902 writes video data with φ=rHJ, and the line memory 902 is divided into one block (7th block) with odd words.
LA in the figure), one block with even words (L in Figure 7)
It consists of two blocks: B).

The output of each word is input to clock gate 903. In addition, the clock gate 903 is configured for each LA and LB.
In other words, the outputs of the bits having the same weight in the odd and even words of the line memory 802 are commonly connected. 904 is a shift register A for reading video data from LA 1905 is a shift register B for reading video data from LB 0 Both are started by STR and sequentially transfer STR to shift with clock φ.

The output of each stage of the shift register A304 is connected to a clock gate 903 connected to an odd numbered word of the line memory 902.
The output of each stage of the 77 register B905 is the clock signal of the clock gate 80 connected to the even word.
3 clock signal. This allows line memory 9
In the two blocks (LA, LB) of No. 02, the stored video data is DAO to DA3. DBO to DBS are read out in parallel. Further, writing and reading of video data in the line memory 902 (or L702) can be performed independently.

As explained above in the first and second embodiments, although the readout period is 1/2H, which is the same as in the conventional example, when reading video data from the line memory, the frequency of the readout clock signal is l /2 can be set. This example! explained the case where the line memory is divided into two blocks, but it is equally possible to divide the line memory into multiple blocks, and in that case, the frequency of the read clock signal can be lowered (can be set). .A combination of Examples 1 and 2 is also possible.

In the present invention, the line memory has been described as the image memory, but even when field memory or frame memory is used, the memory can be divided into multiple blocks and video data can be read from the memory in parallel for each block. , it goes without saying that a similar driving method can be realized.

〔Effect of the invention〕

As explained above, according to the present invention, an image memory is divided into a plurality of blocks, and when writing, video information corresponding to each block is written in chronological order, and when reading, video information is written from each block in parallel. By reading, the clock frequency at the time of reading can be lowered in inverse proportion to the number of divided blocks. Therefore, (1) the frequency of the read clock signal can be lowered, so the required power consumption can be reduced.

■The frequency is low (as it can be done, the design margin for delays caused by circuit elements becomes large).

Even in the signal side drive circuit according to the present invention, for example, to which the video data read from the zero image memory is transferred, the signal system frequency can be lowered, leading to a reduction in power consumption and an increase in design margin.

The present invention has the following effects and is of great significance.

[Brief explanation of the drawing]

Fig. 1: A block diagram of a first embodiment of an image display device according to the present invention. Fig. 2: A block diagram of a conventional image display device. Fig. 3...
Display section explanatory diagram Figure 4...TJ2 diagram Time chart diagram of each part Figure 5.
. . . Time chart of the first drawing number section. . . . . . . . . . . . . . . . . . . . . . . . . Time chart figure 9 of figure number section...
・Line memory configuration diagram Figure 2 Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] (1) a) When valid video information during one horizontal period is divided into N blocks; b) Video information divided into blocks corresponding to each of the valid video information divided into the N blocks. In an image memory configured to store c) effective video information for one horizontal period is written into the image memory in a temporally serial manner, and d) effective video information for one horizontal period is written into the image memory. A method for driving an image memory, characterized in that reading from the memory is performed temporally in parallel from N blocks constituting the image memory.