JPH0547915B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data processing system, and more particularly, to a data processing system that transmits at least a portion of a plurality of data blocks, each of which includes synchronization data, address data for writing to memory, and information data. The present invention relates to a data processing system for writing to memory.

(Description of Prior Art) In general, in this type of data processing system, after transmission, for example, after recording and reproduction, it is necessary to perform processing such as correcting code errors and arranging information data. data back to ram
(random access memory), etc., must be written once. At this time, all data must be written to a predetermined location in the memory in accordance with the address data added in front of it.

However, since address data is transmitted in the same way as information data, code errors may occur due to dropouts, jitter, intersymbol interference, and the like. Therefore, constantly writing information data into memory in response to transmitted address data involves considerable risk.

Therefore, by counting the synchronization data in each data block at the same time as this address data, data similar to the address data is created.
There is also a method of controlling the writing position to memory using a so-called internal address counter. However, since the address counter also counts the transmitted synchronization data, there is a risk that the count value may become incorrect due to loss of synchronization data, noise, or the like. Particularly in this case, once a counting error is made, there is a risk that all data transmitted thereafter will become invalid.

(Objective of the Invention) In view of the above-mentioned drawbacks, it is an object of the present invention to provide a data processing system that can extremely accurately control the writing position in a memory.

(Explanation based on an embodiment) Hereinafter, a data processing system of the present invention will be described in detail using an embodiment in which the data processing system of the present invention is applied to a recording/reproducing system of a digital audio signal in a video tape recorder (VTR).

FIG. 1 is a schematic diagram showing a tape running system of a VTR according to an embodiment of the present invention. In FIG. 1, 1 is a rotating drum, 2 and 3 are rotating heads, 4 is a magnetic tape, and 5, 6, 7, and 8 are movable guide posts for pulling out the tape 4 from the cassette 10 and winding it on the drum 1. , 11, 12 are guide posts. Heads 2 and 3, which are arranged with a phase difference of 180° on drum 1 as shown in the figure, respectively transmit a digital audio signal while moving from point A to point B in the figure, and transmit a digital audio signal while moving from point B to point C in the figure. is the video signal, tape 4
Record while forming a helical track on the top.

FIG. 2 is a diagram showing the recording format on the tape 4 by the VTR of FIG. 1. In FIG. 2, 13 is an area where one field's worth of video signals is recorded, and 14 is an area where one field period's worth of digital audio signals are recorded. Area 14
The digital audio signal recorded on is, for example, a sampled audio signal converted into PCM,
It is assumed that the time axis is further compressed and FM modulation is recorded.

Next, an example of the data format of this digital audio signal will be explained with reference to FIG. The format shown in FIG. 3 is an audio signal for one field period, and the sampling frequency is 480V, where v is the field frequency. Third
In the figure, b0 to b119 indicate data blocks, respectively. Further, A0 to A119 are data words for address instruction, Q0 to Q119 and P0 to P1, respectively.
19 are error correction words, L0 to L.
479 is a data word of the L channel audio signal, and R0 to R479 are data words of the R channel audio signal. Each data block contains synchronization data for l1, a data word for addressing, 8 words of audio signal data, 2 words of error correction data, and l13.
Contains CRCC (Cyclic Redundancy Check Code). For example, l1 is 3 bits, l2~
l12 consists of 8 bits, and l13 consists of 16 bits. The above-described parity words are formed using the well-known cross-interleaving method, and of course, so-called word interleaving as shown in the figure is also used.

The data matrix obtained by the above-described format is sequentially transmitted in units of data blocks each having address data and synchronization data as shown in FIG. Then, one data matrix is recorded so as to fit into the area 14.
In other words, following the 3-bit synchronization data of b0,
0, Q0, L0, L60, L120, L180,
P0, L240, L300, L360, L42
0, B0 CRCC, b1 synchronization data, A1,
Q1, R0, R60... b119
Records up to CRCC.

If this is then to be played back, it is necessary to use the CRCC to detect errors in each data block and then search through the entire matrix using the parity word. Therefore, these must be stored in a memory such as RAM before processing. At that time, all 10 words of data are written to RAM according to the address data added immediately before.

FIG. 5 is a diagram showing the RAM written in this manner. The 10 words of data of each data block described above are recorded in areas on the RAM corresponding to each address A0 to A119. Also, after this, the part shown in Frag in Figure 5 corresponding to each block is
The error search result data corresponding to each word of the 10-word data is written. This data (flag data) is written as "0" or "1" to indicate whether each of words 1 to 10 is correct or incorrect. That is,
The Frag part must be at least 10 bits (for example, 2 bytes = 16
Bit) is good.

In this way, data corresponding to one field period's worth of audio signals is written onto the RAM, but before this, data errors are detected for each data block by the CRCC. At this time, when an error is detected in one data block by CRCC, it means that an error has occurred somewhere in the 10 word data or address data. In other words, it is possible that an error has occurred in the address data. Therefore, in this case, there is a great risk when writing address data to RAM as described above. In other words, if the address data is incorrect, not only will the data in that block become invalid, but it will also have an adverse effect on error detection for all data.

FIG. 6 is a block diagram showing a reproduction data processing system of a VTR as an embodiment of the present invention. In FIG. 6, 21 is reproduced by heads 2 and 3,
This is a terminal into which FM demodulated data is input.
The data input format at this time is as shown in FIG. This input data is supplied to a CRCC check circuit 22, a synchronization signal detection circuit 23, and a data separator 25. The circuit 22 separates the above-mentioned CRCC, the circuit 23 separates the synchronization data, and the separator 25 separates the address data and 10 word data. .

The data separator 25 operates based on the synchronization data detected by the synchronization signal detection circuit 23. On the other hand, this detected synchronization data is stored in internal counter 2.
By counting this synchronizing data with the counter 24, it is possible to know the address to which the currently input data block is to be written.

The output of the data separator 25 is supplied to an address sampling circuit 26, where the address data is separated. The address data thus obtained and the address value output from the counter 24 mentioned above are supplied to a comparison circuit 27, and it is determined whether or not these two data values match.
This discrimination output is supplied to the control circuit 28. The control circuit 28 is also supplied with the error detection output of each data block obtained from the CRCC check circuit 22. The control circuit 28 controls the data selector 29 based on these two pieces of information.

Based on the output of the control circuit 28, the data selector 29 determines the write address of 10 words of data to the RAM 30 according to the output of the internal counter 24 or the address data extracted by the address extraction circuit 26. Select. now,
If the check output of CRCC is an output corresponding to "positive", there is no error in the address data extracted by the address extraction circuit 26, so the address data via the A terminal of the selector 29 is used.
Write data to RAM30. However, if this address data and the output of the internal counter 24 match, either one may be used. on the other hand
If the check output of the CRCC is an output corresponding to "error", it is dangerous to use the address data extracted by the address extraction circuit 26, so it is desirable to use the output of the internal counter 24. In particular, at this time, if the comparison circuit 27 determines that the address data extracted from the address sampling circuit and the output of the internal counter 24 do not match, it is extremely likely that an error has occurred in the address data. The output of the internal counter 24 is set to B of the selector 29.
It is supplied to the RAM 30 via a terminal to control the write address. However, even in this case, if the extracted address data and the output of the internal counter 24 match, either one may be used. At this time, the extracted address data and internal counter 24
It is natural to assume that both outputs are error-free.

By determining the write address to the RAM 30 in accordance with the address value selected and output by the selector 29, it is possible to write to the RAM 30 using only the transmitted address data in the conventional system.
It is possible to mutually compensate for the drawbacks that occur when determining the write address to 30 or when determining this using only the output of the internal counter, and it is possible to extremely accurately determine the write position to memory such as RAM.

The 10-word data thus stored in the RAM 30 is added with flag data based on the parity word as described above, and after further error correction is performed, the data is expanded on the time axis and output as a reproduced audio signal.

As is clear from the description of the above embodiment, if the comparison circuit 28 is not provided and the output of the CRCC check circuit 22 corresponds to "positive", writing to the RAM will be performed according to the output of the address extraction circuit 26. conduct,
A similar effect can be obtained even with a simple configuration in which "error" is handled according to the output of an internal counter.

Furthermore, although the above embodiment takes as an example an audio signal recorded and played back using PCM on a VTR,
It goes without saying that similar effects can be obtained by applying the present invention when transmitting a plurality of data blocks including synchronization data, address data, and information data.

(Description of Effects) As described above using the embodiments, according to the data processing system of the present invention, it is possible to accurately determine a write address to a memory.

Therefore, it is possible to prevent invalidation of data due to a write address error as much as possible, and it has become possible to perform extremely stable data transmission and data error correction after transmission.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a tape running system of a VTR according to an embodiment of the present invention, FIG. 2 is a diagram showing a recording format on a tape by the VTR of FIG. 1, and FIG.
The figure shows an example of the data matrix format, Figure 4 is a timing chart showing the data transmission order, Figure 5 is a diagram showing the state of data written on the RAM, and Figure 6 is a diagram showing the data transmission order of the present invention. As an example
FIG. 2 is a block diagram showing a reproduction data processing system of a VTR. 22 is a CRCC check circuit as an error detection means, 23 is a synchronization data separation circuit, 24 is an internal address counter, 25 is a data separator, 2
6 is an address extraction circuit, 27 is a comparison circuit, 28 is a control circuit, 29 is a data selector, 30 is a RAM as a memory, A0 to A119 are address data, Sync is data for synchronization, b0 to b119
each indicates a data block.

Claims (1)

[Scope of Claims] 1. A data stream that is transmitted in units of data blocks including synchronization data, address data, main information data, and an error detection code, and that includes a plurality of data blocks sequentially, A data processing system for storing information data in a memory, comprising: a synchronization detection means for detecting synchronization data in the data string; an address counter for counting the number of synchronization data detected by the synchronization detection means; error detection means for detecting code errors for each data block; address separation means for separating the address data from the data string; and a count value of the address counter and the address separation means according to the output of the error detection means. and selecting means for selectively outputting the address data separated by the address data as a write address of the memory.