JPH0542482Y2 - - Google Patents

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a power switch circuit for electronic equipment, particularly a power switch circuit for a DC voltage stabilizing circuit.

"Prior art and its problems" As shown in FIG.
The output means 40 adjusts the output according to the magnitude of the error voltage (error between the reference voltage and the voltage obtained by dividing the output voltage) detected. Also,
If only these two methods are used, the following power switch 11'
Immediately after being turned on, a large load is suddenly applied,
Since the load on the output means becomes large, a shunt means 60 is inserted in parallel with the output means.

In order to supply power from a power supply to such a voltage stabilizing circuit, conventionally, a power switch 1 is connected before and after the voltage stabilizing circuit in series with the voltage stabilizing circuit.
1' had been inserted.

However, according to this configuration, the load current (for example, 1A to 2A in the case of a portable TV) flows directly through the power switch 11', so the capacity must be designed to be large, and the durability and
In terms of reliability, conventional devices have had to be able to withstand large currents, resulting in high cost and large size.

"Purpose of the invention" This invention was proposed in view of the above-mentioned conventional circumstances, and the purpose is to obtain a power switch circuit for a voltage stabilization circuit that can be realized using a small capacity and low cost switch. It is something to do.

"Means for achieving the purpose" In order to achieve the above purpose, this invention employs the following configuration. That is, in the power switch circuit for the voltage stabilizing circuit described above, which is equipped with an output means, a comparison means, and a shunt means, first, an opening/closing drive means consisting of a series circuit of a bias resistor and a power switch is connected in parallel with the power supply. Then, based on the switching control voltage obtained from the bias resistor,
A bias switching means is provided for controlling the opening and closing of a bias circuit that applies a bias to the output means and the comparison means, and further a shunt circuit is provided for controlling opening and closing of the shunt circuit that is controlled based on the output of the bias switching means. The main feature is that an opening/closing means is provided.

The bias switching means can take various configurations, but for example, it may include a first transistor that is controlled to turn on and off based on a switching control voltage circuit obtained from the bias resistor, and a
A configuration can be considered that includes a second transistor that turns the bias circuit ON and OFF as the bias circuit turns ON and OFF.

Also, various configurations can be considered as the shunt switching control means, but for example, a switching transistor is inserted in series between the shunt resistor and the output side,
It is possible to consider a configuration in which ON/OFF of the switching transistor is controlled by the output of the bias switching means.

"Embodiment" FIG. 1 shows an embodiment of this invention. Power is supplied via a DC jack 13 and a fuse 12, and a voltage stabilizing circuit is connected in series and directly (ie, without a switch) to the power supply and the output. Here, the voltage stabilizing circuit consists of an output means 40, a comparison means 50 for giving an error voltage to the output means 40, and a shunt means 60 for reducing the initial load on the output means 40, and its basic configuration is conventional. Since it is exactly the same as
Here, we will explain the contents to the extent necessary to explain the idea.

The output means 40 has an output control transistor 3 and an error amplification transistor 2 connected in Darlington, and a bias resistor 9 connected to the error amplification transistor 2 with a comparison means 50 as shown below.
The bias is given by . The comparison means 50 compares the reference voltage given by the Zener diode 4 and the output voltage (more precisely, the voltage obtained by dividing the output voltage by the voltage dividing resistors 6 and 8 and the output adjustment resistor 7), and calculates the difference by using the comparison transistor 1. The signal is detected and applied to the error amplification transistor 2. The bias resistor 9 is grounded via the comparison transistor 1 and the Zener diode 4, and biases both the comparison transistor 1 and the error amplification transistor 2. Further, the shunt means 60 is composed of a shunt resistor 61 connected in parallel with the output control transistor 3.

The configuration of the voltage stabilizing circuit is exactly the same as the conventional one, but in this invention, a small capacity switch 11 is further connected to the power source in parallel via bias resistors 17 and 18 to form the opening/closing drive means 10. are doing. The output of the bias resistor on the ground side among the bias resistors 17 and 18 controls the bias switching means 20 described below.

The resistor 9 for applying a bias to the error amplification transistor 2 of the output means 40 and the error detection transistor 1 of the comparison means 50 is the bias switching means 2.
0 to the +B line, and when the switch 11 is turned on and a bias voltage is generated across the resistor 18, this bias switching means 20 is turned on.
It is becoming a state.

Furthermore, between the shunt resistor 61 constituting the shunt means 60 and the output side, the shunt resistor 61 is turned ON at the time of starting.
A shunt switching means 30 is connected in series, and the shunt switching means 30 is controlled so as to turn on when the bias switching means 20 turns on.

FIG. 2 shows a circuit diagram showing the bias switching means 20 and the shunt switching means 30 in more detail.

The bias switching means 20 first includes a first transistor 14, which is an NPN transistor whose emitter is grounded, and whose base voltage is the output of the bias resistor 18. Further, a second transistor 15 is connected between the +B line and one end of the bias resistor 9.
Barrel PNP transistors are connected in series,
Further, the collector of the first transistor 14 and the base of the second transistor are connected through a bias resistor 19. As a result, switch 1
1 is turned on, the first transistor 14 is turned on.
state, and then the second transistor 15 also
When turned ON, the bias resistor 9 and the +B line are connected, and a bias is applied to the comparison transistor 1 and the error amplification transistor 2.

The shunt switching circuit has a shunt resistor 61 and a switching transistor 16 inserted in series between the output side and the shunt resistor 61.
The bias resistor 31 is composed of an NPN transistor and a bias resistor 31 that applies a bias to the base of the switching transistor 16.
is connected to the output side of the bias switching means 20. As a result, the bias opening/closing means 20 is
At the same time as the switching transistor 16 turns on, the switching transistor 16 also turns on, and the starting current is applied to the output side via the shunt resistor 61, so that unnecessary power is not consumed during non-operation.

When the power switch circuit is configured as described above, it is sufficient to flow through the power switch 11 a current sufficient to generate a bias voltage sufficient to turn on the bias switching means 20 in the bias resistor 18, for example, several + mA. .

``Effects of the invention'' As explained above, this invention has a configuration in which the power switch is not inserted in series with the load, so the current flowing through it is small, and therefore the switch circuit is small, durable, and reliable. There is an effect that can be obtained.

Furthermore, since a switching means is also provided for the shunt resistor, unnecessary power is not consumed during non-operation.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a circuit diagram showing the block part of Fig. 1 in more detail, and Fig. 3 is a circuit diagram showing a power switch for a conventional voltage stabilizing circuit. It is a circuit diagram of a circuit. In the figure, 10...output means, 20...comparison means,
30... Diversion means, 40... Bias opening/closing means,
50... Diversion switching means, 11... Power switch,
17, 18...Bias resistance.

Claims (1)

[Claims for Utility Model Registration] (1) An output means connected in series between an input and an output, a comparison means for applying an error voltage to the output means, and a method for reducing the initial load of the output means. In a power switch circuit for a voltage stabilizing circuit equipped with a shunt means, the power switch is connected in parallel to the power supply via a bias resistor, and the above bias voltage is obtained from the bias resistor. bias switching means for turning ON a bias circuit for applying bias to the output means and the comparison means; and a bias switching means inserted in series between the shunt means and the output side, and controlled by the output of the bias switching means. A power switch circuit consisting of a shunt switching means and a power switch circuit. (2) The bias switching means includes a first transistor that turns on and off based on the bias voltage applied by the bias resistor, and a first transistor that turns on the bias circuit for the output means when the first transistor is in the ON state. 2. A power switch circuit according to claim (1) of the utility model registration claim, which comprises the following transistors. (3) A utility model in which the shunt switching means is a switching transistor inserted in series between the shunting means and the output side, and whose base is connected to the output side of the bias switching means via a bias resistor. A power switch circuit according to registered claim (1).