JPH053625B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to image processing, and more particularly to feature extraction circuits for digital images.

[Background of the invention]

In digital image processing, calculations of various feature amounts are performed. For example, there is a process of determining the frequency distribution of density values of each pixel over the entire screen. The results are used for optimizing threshold settings when binarizing an image, converting the density distribution of an image to make it easier to see, etc.

A circuit for determining the density value frequency distribution is realized, for example, as shown in FIG.

In the circuit shown in the figure, when calculating the density value frequency distribution, the switch 4 is turned to the input line 10 side, and image data is successively added from there.
A clock signal is applied to input line 11 in synchronization with this image data. Image data and clock signals are generated externally, for example as shown in FIG.

In FIG. 2, 21 is an image memory,
It is assumed that an image has been previously written by the function of another circuit, which is omitted in the figure. The clock generation circuit 23 outputs a clock signal for reading out the image, and the address counter 2 receives the clock signal.
2 generates an address for sequentially scanning the area containing images in the image memory 21. In this way, the sequentially scanned image data, that is, the density value of each image, is output to the output line 30, the clock signal synchronized with this is output to the output line 31, and the image address is output to the output line 32. .

Now, returning to FIG. 1, the image data that has passed through the switch 4 is added to the memory 2 as an address. On the other hand, the read/write control circuit 3 has
Since the clock signal is applied, the memory 2 can be controlled in synchronization with the image data. Specifically, the following operations are executed with the help of the read/write control circuit 3. First, when new image data arrives, this image data (density value) is the address of the memory 2, so the contents of the memory 2 corresponding to the density value are read out, and this is added to the plus 1 circuit 1. Here, the number becomes larger by 1 and returns to the data input side of the memory 2. The read/write control circuit 3 knows when the image data has arrived based on changes in the clock signal, so it outputs a write pulse 12 to the memory 2 after an appropriate delay time, and then outputs the write pulse 12 as described above. The data is written back to the same address in memory 2.

When the above operation is repeated over the entire area of the input image, the contents of the memory 2 at the address corresponding to the density value of the image data will be incremented by 1 one after another, and finally, the contents of the memory 2 will be filled with the density value of the image. This means that the frequency distribution of values has been found. Of course, all contents of the memory 2 must be cleared to 0 before starting the series of operations described above, but the additional circuit for this purpose is omitted in FIG. 1 to make the explanation easier to understand.

When reading out the frequency distribution obtained in this way, switch 4 is switched to the input line 13 side, and the read addresses are sequentially added to the output line 13.
4, the corresponding frequency value is read out.

Incidentally, the circuit shown in FIG. 1 has only a single function despite its large circuit scale. Because it has the advantage of being able to perform high-speed calculations, it is rarely incorporated into practical machines, but in most cases, microcomputers that can handle more functions are used to perform the same processing using software. It was structured like this. However, in that case, it would be about 100 times slower.

[Purpose of the invention]

The present invention aims to obtain an image processing circuit with unprecedented multifunctionality by appropriately adding several arithmetic circuits and input switching circuits to the configuration for determining the density value frequency distribution as described above. It is something to do.

[Summary of the invention]

Specifically, the plus 1 circuit 1 in Figure 1 is replaced with an arithmetic circuit that can perform addition, MAX operation, MIN operation, etc., and a new input line is provided to input the image address. The feature is that the image data input line and the image address input line can be switched and supplied to the arithmetic circuit and memory.

With these, it is possible to eliminate waste in circuit configuration and realize a compact and high-performance image processing device. In addition, by appropriately combining input switching circuits, the number of input lines to this circuit can be reduced to a small number, which has the effect of simplifying the overall circuit configuration.
Furthermore, when realized as an LSI (high-density integrated circuit), the number of pins is small and it can be housed in a small package, making it possible to obtain an IC that is multifunctional and highly economical.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Similarly to 2, 42 is a memory in which various calculation results are stored. 411 with output data 63 of memory 42 as one input is MIN/MAX
Similarly, 412 is an adder circuit, and 413 is a selector (C), which calculates and selects the result 5.
0 is written back to memory 42. Select signal (C) 53 determines which calculation result is selected, 51 or 52.
controlled by. Further, the MIN/MAX switching signal switches between the MIN calculation and the MAX calculation, and the addition/plus-1 switching signal 55 controls whether the addition circuit 412 executes addition or plus-1. Here, the MIN operation means that the smaller of two inputs is output, and the MAX operation means that the larger of two inputs is output. What is addition?2
The output is the sum of the two inputs, plus 1
This means that the output is the sum of the input at the top in the figure plus 1.

The selector (A) 44 functions to set one input 56 of the calculation units 411 and 412 as image data 57 or as an image address 58,
Controlled by select signal A59. On the other hand, the selector (B) 45 selects the address 60 of the memory 42,
In addition to being used as image data 57 and an image address 58, it also functions as an external address 61 if necessary, and is controlled by a select signal 62.

The read/write control circuit 43 creates a write pulse 64 to be applied to the memory 42 from the clock signal 63 as in the example shown in FIG. It also functions to switch the external write pulse 65 to be applied to the memory 42 if necessary.

As can be seen from the above explanation, the circuits used in the embodiment shown in FIG. 3, such as the adder circuit and the selector, are all available as commercially available ICs, and therefore will not be described in further detail.

The functions that can be performed with this embodiment have an extremely wide repertoire, as shown in FIG.
In this figure, the column number 5 of selector A is as follows:
The meaning is the same no matter which one you choose. Also, MIN/MAX in the item number 1 column of selector C is
MIN or MAX depending on the MIN/MAX switching signal 54
This is based on the premise that addition in the columns 2 to 4 and 6 and selection of plus 1 in the column 5 are made by the addition/plus 1 switching signal 55. Note that for items for which external addresses are selected in the column of selector B, this is a case where this is set as a fixed value and the results are accumulated only at specific addresses in the memory 42.

In the function column, item number 5 corresponds to the calculation of the conventional density value frequency distribution, and items 1 to 3 correspond to the extraction of the maximum (minimum) density value and the calculation of the sum of density values to find the average density value, respectively. , is an operation for determining the area of a binary image. When a binary image is input, the values are only "1" and "0", so if these are directly integrated, the area of the figure can be found as the number of pixels.

In item No. 4, it is necessary to add the binary image data 66 as an input to the read/write control circuit 43, but if you do this and set only the X or Y component of the image address to be input with selector A, 2 The first moment of a value image can be easily found. This principle will be explained next. At this time, the read/write control circuit 43 is gated by the binary image data 66 and operates so as not to output a write pulse if the binary image data is not "1". In this way, the X or Y coordinates are integrated over the entire portion where the binary image exists (that is, it is "1"). By dividing this by the area (number of pixels) of the binary image determined by item number 3, the first moment in the X or Y direction as defined can be obtained. Since the final division is done only once,
Even if the process is executed by an external microcomputer, the overall processing speed will be extremely high.

Note that the signal line 66 also works effectively during calculations of other item numbers in FIG. For example, prepare another set of image memory equivalent to the image memory shown in Figure 2, and store the multivalued image in one and the binary number of strokes obtained by processing this in the other. By synchronously reading out the binary image and inputting this binary image to the signal line 66, it is possible to obtain the result calculated only in the portion where the binary image exists (by applying a mask).

In addition, in Figure 4, 1 of the binary image in the column of function item number 4
The next moment is obtained when a binary image is added to the input of the read/write control circuit 43, or as a result of dividing the input by the area of the image later.

FIG. 5 shows the arithmetic unit 41 indicated by the broken line in FIG.
An example will be described in which the following is slightly changed. Here, we are planning to share the circuit,
Instead of the MIN/MAX circuit 411, a comparator 421 which is a part thereof and an EOR circuit 43 following it
Only 1 is used. The output line 500 of 431 is connected to the comparator 4 according to the MIN/MAX switching signal 54.
The result of comparison 21 is inverted, and it is determined whether the contents of memory 2 (read out to signal line 63) or the data given to signal line 56 (via selector (A) 44) It appears as a signal indicating whether to choose. Inside the MIN/MAX circuit 411 described above, there is a selector that selects data according to this signal, and its output appears on the signal line 51. Here, this selector is omitted, taking advantage of the fact that when the contents of memory 2 are selected, writing them back to the memory is the same as not writing them. That is, the output line 500
By controlling the write pulse 64 to the signal memory 2 that appears at the time, the contents of the memory 2 will be updated only when necessary, and the same result will be obtained. Therefore, in this embodiment, an OR circuit 433 and an AND circuit 434 are added in the middle of the write pulse signal line 64.

Furthermore, the selector 413 is also omitted here, and the selector signal C53 is connected to the OR circuit 433 instead. In this way, the selector signal C
53 is "1" and addition (or plus 1) is selected, the output 501 of the OR circuit 433 becomes "1", and the write pulse 64 is output from the AND circuit 43.
4 and appears as it is on the signal line 641, and writing to the memory 2 is performed in the same way as in the previous embodiment. On the other hand, when the MIN (MAX) operation is selected (the signal 53 is "0"), the signal line 501 becomes "1" and "0" according to the signal line 500.
Memory updates are performed only when necessary. At this time, it is necessary that the input 56 other than the memory content 63 of the comparator 421 appears on the signal line 50, but this is due to the action of the AND circuit 432, so that the input on the opposite side of the adder circuit 422 becomes 0. This is achieved by becoming.

In addition, as a further modification of the present invention, the selector
Although the number of inputs of (A) 44 and selector (B) 45 is increased, the operation and effect can be easily inferred, so a description thereof will be omitted.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a high-speed and multifunctional image processing circuit although it is a simple circuit. In addition, it is possible to suppress the increase in the number of input/output pins, making it a highly economical IC.
It can be realized as

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of the prior art;
5 and 5 are block diagrams of the embodiment, and FIG.
It is a functional explanatory diagram of the circuit shown in the figure. 41... Arithmetic unit, 42... Memory, 43... Read/write control circuit, 44, 45... Selector.

Claims (1)

[Scope of Claims] 1. A memory means for storing calculation results; a first selection means for selecting either image data or an image address; and selecting one of the image data, the image address, or an external address. a second selection means for setting the address of the memory means; a comparison means for comparing the selection result of the first selection means with the data read from the memory means and outputting one of the results; an addition means for adding the selection result of the selection means 1 and the data read from the memory means, or adding 1 to the data read from the memory means; and either the comparison means or the addition means. An image processing circuit comprising: means for writing back the output of to the memory means; 2. In claim 1, the comparison means performs a MIN operation that outputs the smaller of the selection result of the first selection means and the data read from the memory means, or the first selection. An image processing circuit comprising MIN/MAX means for performing either a MAX calculation which outputs the larger of the selection result of the means and the data read from the memory means. 3. The image processing circuit as set forth in claim 1, wherein the write-back means comprises third selection means for selecting the output of either the comparison means or the addition means. 4. In claim 1, the writing back means includes means for prohibiting writing back to the memory means when the comparing means outputs the data read from the memory means. An image processing circuit characterized by: