JPH05322978A - Test condition setting device for ic tester - Google Patents

Abstract

PURPOSE:To enable an arbitrary IC element to allocate an arbitrary pin number in simultaneous measurement. CONSTITUTION:In the position of device pin number belonging to a pin group number in a table 14 during a single element measurement, flag '1' is given. On the other hand, in a pin definition table 26 for simultaneous measurement, 256 bit registers of the device pin number, 256, are provided and in each register, flag '1' is given to the position the device pin number is allocated for the same device pin as the device pin number. Only registers in the table 26 corresponding to the flag '1' positions in the data read out of the pin group table 14 are read out. Logical summation of corresponding bit of the read out data and the read out data of the table 14 are set in a pin selection register 19 and a pin data table 15 in the flag '1' part in the output of the register 19 becomes enable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test condition data setting device for setting test condition data corresponding to each pin in a semiconductor integrated circuit, an IC tester for testing a so-called IC element.

[0002]

2. Description of the Related Art FIG. 5 shows an outline of a conventional test condition data setting device. Depending on each IC device under test, the I data is written in the selector data description section 12 of the device test program 11.
When testing the C element, those that perform the same operation as the device pin number of the IC tester are collected as a pin group, the pin group is numbered, and which device group belongs to each pin group number. It is attached. That is, in FIG. 5, four device pin numbers P1, P3, P5, and P256 belong to the pin group 1 as performing the same operation. In the pin group 2, the device pin numbers P2 and P11 to P15 form the group. Similarly, the device pin numbers belonging to each pin group are described below.

Further, in the program 11, for the timing data which is a test condition, for example, the timing data description section 13 describes which edge of which pin group is to be set at which timing. In this example, the timing of the first edge (edge 1) of pin group 1 is described as 10 nS, and the timing of edge 1 of pin group 2 is described as 20 nS. Thereafter, the test condition data is sequentially set in this manner. Usually, conditions for a plurality of edges are set for each pin group. Further, not only the pin groups having the same timing but also, for example, the voltage level is set for each pin group. Various other test condition data are set for each of the same pin groups.

In this way, the device test program 11
Various kinds of data are described in the pin group table 1 by reading out the selector data description part 12 to determine what device pin number belongs to each pin group.
Register in 4. Next, the timing table description unit 13 is sequentially read. That is, in this example, first pin group 1,
The edges 1 and 10 nS are read, and the pin group table 14 is read by the read pin group 1, that is, the device pin numbers belonging to the pin group 1, P 1, P 3, P 5, P 256 in this example.
The pin data table 15 is provided with a register for storing the timing of each edge so that a plurality of edges can be set for each device pin number, that is, for each of the pins P1 to P256 in this example. There is. In this example, the device pin numbers P1 and P belonging to the pin group 1 are read from the pin group table 14.
3, P5, P256 and the edge 1 of the edge number read from the timing data description unit 13 selects the corresponding register in the pin data table 15 and reads it from the timing data description unit 13 10 nS which is the generated timing information is written respectively.

FIG. 6 shows a more specific hardware configuration of the conventional apparatus shown in FIG. That is, the pin group table 14 is assigned 1 bit for each device pin number for each pin group (number) 1, 2, 3 ..., That is, in this example, the maximum value of the device pin number is P256,
256 bits are allocated respectively. Then, in each of the 256 bits, "1" is set to the bit corresponding to the device pin number belonging to the pin group. In this example, for the pin group (number) 1, "1" is set for each of the first bit, the third bit, the fifth bit, and the 256th bit, and the others are set to "0".

The pin group number in the data read from the timing data description section 13 is stored in the pin group number register 16, and the pin group table 14 is read by the output of this register 16. The edge number read from the timing data description unit 13 is stored in the edge number register 17, and the read timing data is stored in the data register 18. Information (data) indicating the device pin number belonging to the pin group number read from the pin group table 14 is latched in the pin selection register 19. Each "1" in the data latched in the pin selection register 19 enables the pin data table 15 of 1 to 256 corresponding to the position, and the contents of the edge number register 15 are pinned through the address bus 21. Data table 1
5, the storage area of the corresponding edge number, that is, the area of the edge (number) 1 in this example is selected, and the data (10 nS) from the data register 18 is enabled through the data bus 22. It is written in the area selected by the address of the address bus in the pin data table 15.

Conventionally, a single IC tester is used for a plurality of I's.
The C element was also measured at the same time. For example, when the number of device pins is 256, when four IC elements are measured simultaneously, up to 64 IC elements can be simultaneously measured. In that case, the pins of each IC element can be measured. The device pin number was sequentially assigned to the number, that is, the device pin number. That is, as shown in FIG. 7A, the device numbers are 1, 2, 3,
When testing this IC element 4 of 4, the device pin numbers P1 to P64 are assigned to the device pin numbers 1 to 46 for the device number 1, and the device pin numbers 1 to 1 of the IC element of the device number 2 are assigned. Device pin numbers P65 to P128 are assigned to 64, and device pin numbers P129 to P1 are assigned to device pin numbers 1 to 64 for the IC element of device number 3.
92 are assigned respectively, and device pin numbers P1 to P1 are assigned to device pin numbers 1 to 64 of the IC element of device number 4.
93 to P256 are assigned respectively. In this way, the device pin numbers P1 to P256 are divided into four, and each of them is connected to the 64-pin IC element, and four ICs are simultaneously formed.
The device was being tested.

[0008]

In the case of simultaneously measuring a plurality of IC elements in the conventional IC tester,
Since the device pin numbers are assigned in order as shown in FIG. 7A, the connection between each pin of each IC socket of the performance board in which four IC sockets are arranged and the device pin terminal on the performance board are duplicated. In addition, since the wiring is long, that is, the test pin terminals on the performance board are fixedly arranged in a predetermined order, the wiring for connecting to the device pin terminal that is away from the IC element socket is also performed. Is complicated, which is not preferable.

In order to solve such a problem, it is sufficient that the device pin number can be arbitrarily assigned to each device pin number of each device number. For example, as shown in FIG. 7B, for device pin number 1 of device pin numbers 1 to 64 of device numbers 1 to 4, device pin numbers P1, P16, and P are assigned to device numbers 1, 2, 3, and 4.
35 and P45 are assigned respectively, and device pin number 2 is assigned device pin numbers P2, P17, P36, and P50, respectively.
It is possible to facilitate the connection between the C socket pin and the device pin terminal.

However, if the device pin number is arbitrarily assigned to each device pin number of each IC element for simultaneous measurement, it becomes difficult to set the test condition data for the pin group. That is, it is necessary to recreate the device pin number belonging to each pin group. For example, when the device pin numbers P1, P3, P5, and P25 are assigned to the pin group 1 and the device pin numbers are assigned to the device pin numbers of each IC element as shown in FIG. 7B,
Since the same data needs to be assigned to each of the pin device numbers 1, 2, 3, and 4, the device pin P1 indicating the device pin number 1 of each element corresponding to the device pin number P1 belonging to the pin group 1, P16, P35, P
45 and device pin numbers P3, P18, and P3 indicating the device pin number P3 of each element corresponding to the device pin number P3
7, P55, and device pin numbers P5, P19, and P3 indicating the device pin number 5 corresponding to the device pin number P5.
8, P60, and device pin numbers P256, P20, P40, P7 indicating device pin numbers corresponding to P256.
16 device pin numbers 0 to 0 belong to pin group 1 as shown in FIG. 7C. Similarly, for other pin group numbers, it is necessary to rewrite, that is, redefine, the device pin numbers belonging thereto.

From the affiliation of the device pin number to each pin group when testing one element in this way,
It takes a relatively long time to generate the affiliation to each pin group in the case of simultaneously testing a plurality of IC elements by software based on the assignment of the device pin number at the time of simultaneously measuring a plurality of IC elements. On the other hand, a pin group table showing the affiliation of each device pin number with respect to the pin group number when testing a single device, and a redefinition table showing the affiliation of the device pin number with respect to each pin group when testing a plurality of IC devices When using and, it is necessary to make both of these tables always resident in the main memory on the CPU, and the memory capacity on the CPU is reduced accordingly. Further, there is a process for distinguishing which of these two tables is used, which makes the process as a whole complicated.

[0012]

According to the present invention, there is provided a simultaneous measurement pin definition memory that determines which device pin number is assigned to which IC device for each device pin number of an IC device during simultaneous measurement of a plurality of devices. .. When setting the test condition data, the information indicating the device pin number belonging to this is read from the pin group table by the pin group number, and the simultaneous measurement pin definition table is set by each of the read device pin numbers. The test condition data for the pin group number that is read out and set to the read pin data table for each device pin number is set.

The simultaneous measurement pin definition table is composed of registers having the same number of bits as the number of all device pin numbers for each device pin number. Alternatively, the simultaneous measurement pin definition table is composed of a memory, and each bit indicating the position of the device pin number read from the pin group table is encoded in a predetermined order by the priority encoder to read the simultaneous measurement pin definition memory. .. Thus, when the simultaneous measurement pin definition memory and the priority encoder are used, when the simultaneous measurement pin definition memory is first read for the pin group number, the read device pin number is used, and The device pin number is stored in the redefinition memory in association with the pin group number. When the pin group number is read from the simultaneous measurement pin definition memory for the second time or later, the device pin number belonging to the pin group number is read from the redefinition memory. In any of the above cases, the data read from the pin group table and the data read from the simultaneous measurement pin definition table are ORed bit by bit to select the corresponding pin data table. To be done.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the basic concept of an embodiment of the present invention. In the device test program 11, the selector data description unit 12 and the timing data description unit 1 are used as in the conventional case.
3 and the like are provided, a simultaneous measurement pin data description section 25 is provided in the present invention.
When C devices are measured simultaneously, device pin numbers that are treated the same, that is, device pin numbers assigned to each of the four IC devices for the same device pin number are described. For example, the relationship is as shown in FIG. 7B. In this example, device pin numbers P1, P16, P35, P
45 is the same device pin number 1, and device pin numbers P2, P17, P38 and P50 are the same device pin number 2. The description of the simultaneous measurement pin data description section 25 is registered in the simultaneous measurement pin definition table 26. Similarly to the conventional case, the device pin numbers corresponding to the pin group numbers of the selector data description unit 12 are registered in the pin group table 14, respectively.

Thereafter, the data is sequentially read from the timing data description section 13, that is, the pin group number, the edge number and the timing data are read. The pin group table 14 is read by the read pin group number, number 1 in this example, that is, the device pin numbers P1, P3, P5, and P256 are read. Further, the read device pin numbers P1 and P
3, P5, and P256 read the simultaneous measurement pin definition table 26, respectively. That is, device pin number P1
, P1, P16, P35, and P54 are read, and device pin number P3 is read as P3, P18,
P37 and P55 are read.

Similarly, P5 and P256 are read out in the same manner, 16 device pin numbers are read out as a whole, and these read device pin numbers and edge numbers read out from the timing data description section 13 are read. In this example, the edge 1 corresponds to the test apparatus pin number in the pin data table and is 10 nS which is the timing data read to the register corresponding to the edge (number) 1.
Are stored at the same time.

FIG. 2 shows a more specific example of FIG. 1, and parts corresponding to those in FIG. 6 are designated by the same reference numerals. Also in this case, the pin group number read from the device test program 11 is stored in the pin group number register 16 as in the conventional case, and 256 bits corresponding to the pin group number in the pin group table 14 are stored by the pin group number. Data is read in parallel.
On the other hand, the simultaneous measurement pin definition table 26 is a case where each device pin number P1 to P256 is composed of a register of 256 bits, and the same device pin corresponding to the device pin number is stored in each register. For a device pin number that is a number, for example, the device pin number P1, "1" is set in each of the 16th, 35th, and 45th bit positions, and the others are set to "0". Similarly, for the register for the device pin number P2, "1" is set only for each of the 17th, 36th, and 50th bit positions.

The register of the simultaneous measurement pin definition table 16 corresponding to the position of "1" in the data read from the pin group table 14 is read at the same time, that is, P3 for the pin group (number) 1, P
5, the registers for P256 are read simultaneously.
The OR circuit 27 logically ORs the read data and the data read from the pin group table 14 in a bit-corresponding manner, and the total 256-bit output is stored in the corresponding bit position of the pin selection register 19. To be done. Therefore, in the pin selection register 19, according to the examples shown in FIGS. 5 and 7B, “1” is set at the bit position corresponding to each device pin number shown in FIG. 7C for the pin group (number) 1. It becomes a state. Only the corresponding device pin number in the pin data table 15 is enabled by the fact that each "1" of the data in the pin selection register 19 is set, and the edge address is designated by the edge (number) 1 from the address bus 21. Then, the timing data (10 nS) from the data bus 22 is written in the addressed area.

FIG. 3 shows the essential parts of another embodiment of the present invention. In this embodiment, the data read from the pin group table 14 is stored in the read register 29. The data stored in the reading register 29 is encoded by the priority encoder 31 in the order from the highest pin number to the bit number for which "1" is set, and the code defines the simultaneous measurement pin definition table 26.
Is read. In this case, the simultaneous measurement pin definition table 26 is composed of a readable / writable memory, and is read with the code from the priority encoder 31 as an address. The memory 26 has device pin numbers P1 to P2.
The device pin number P for each address for 56
1 to P256 are assigned one bit at a time, that is, one word is composed of 256 bits, and "1" is set at the position of each device pin number belonging to the same device pin number at the time of simultaneous measurement for each address.

Bits in which "1" is set are read from the read register 29 in descending order of number, one word in the memory 26 is read correspondingly, and read from the memory 26. The data and the data read from the pin group table 14 by the OR circuit 27 are bitwise ORed and stored in the buffer register 32. When the reading of one "1" from the read register 29 to the memory 26 is completed, the output code of the priority encoder 31 is also stored in the register 33, which is decoded by the decoder 34 and encoded in the read register 29. Delete the "1" you made and "0"
Convert to. In this way, the sequential reading register 29
The number (position) of the bit in which "1" is set is encoded, and the stored data of the address of the memory 26 corresponding to the code is read out and taken into the buffer register 32. When the loading in the buffer register 32 is completed in this way, the contents of the buffer register 32 are stored in the pin selection register 19. The subsequent processing is the same as in the case of FIG.

In FIG. 3, each pin group table 1
It takes a relatively long time to read the simultaneous measurement pin definition table 26 for each “1” in the data read out from No. 4. From this point, as shown in FIG. 4 by attaching the same reference numerals to the portions corresponding to FIG. 3, a redefinition area 36 is added to the pin group table 14, and when the pin group table 14 is read by the pin group number, When the pin group number is the first read, the pin group table 14 is read, but when the pin group number is the second or later read, the redefined area 36 is read by the pin group number. When the pin group number is the first read, the buffer register 3
The contents stored in No. 2 are transferred to the pin selection register 19, and at the same time, are transferred to the redefinition area 36 via the buffer 37.
The pin group number at that time is written as an address.

That is, in the redefinition area 36, the device pin numbers of the pin group numbers redefined for simultaneous measurement are stored, and therefore the contents shown in FIG. 7C are stored.
When the pin group number to be read is the second time or later, the redefinition area 36 is read according to the pin group number, so that each bit in the read register 29 in which "1" is set is sequentially read from the simultaneous measurement pin definition table 26. Compared to the case, it is possible to read all at once, and the setting time of the test condition data is shortened accordingly.

In the above description, each pin group table 1
Since the OR circuit 27 ORs the data read from No. 4 and the data read from the simultaneous measurement pin definition table 26 by the OR circuit 27, the data for the simultaneous measurement pin definition table 26 is written. At this time, it is not necessary to write the data corresponding to the data read from the pin group table 14 in the simultaneous measurement pin definition table 26, and the write time and the processing to the simultaneous measurement pin definition table 26 can be shortened accordingly. .. However, this is not always necessary, and the OR circuit 27 may be omitted and “1” may be set in the simultaneous measurement pin definition table 26 for all device pin numbers for the same device pin number for each device pin number. ..

Although the timing data is set as the test condition data for each pin group in the above description, the present invention can be applied to the case of setting other test condition data such as the voltage level for each pin group.

[0025]

As described above, according to the present invention, the device pin numbers belonging to the same device pin number at the time of simultaneous measurement are stored in the simultaneous measurement pin definition table and read out from the pin group table. By reading the simultaneous measurement pin definition table with the data, it is possible to relatively easily obtain the redefined device pin number belonging to the pin group number at the time of simultaneous pin measurement. This can be achieved in a shorter time than when done by software, and the pin can be compared with the case where a pin group table for single element measurement and a redefined pin group table for simultaneous measurement are provided. The operation of the pointer or the like for the group table is not complicated, and the processing can be easily performed. Moreover, the device pin number and the device pin number for each IC element at the time of simultaneous measurement can be arbitrarily associated with each other, so that the wiring of the performance board at the time of simultaneous measurement can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a block diagram showing an embodiment of the invention of claim 2;

FIG. 3 is a block diagram showing an embodiment of the invention of claim 3;

FIG. 4 is a block diagram showing an embodiment of the invention of claim 4;

FIG. 5 is a block diagram showing a basic configuration of a conventional device that sets test condition data for each pin group.

FIG. 6 is a block diagram showing a specific configuration of a conventional test condition data setting device.

FIG. 7A is a diagram showing allocation of each device pin number and device pin number of each IC element in conventional simultaneous measurement, B is a diagram showing an example in which the allocation is arbitrarily performed, and C is redefinition in simultaneous measurement. It is a figure which shows the formed pin group.

Claims (5)

[Claims] 1. A pin group that holds a set of device pin numbers that perform the same operation during a single measurement as a pin group, assigns a number to each pin group, and holds information indicating the device pin numbers that make up the group. A table is provided, and the test condition data given by the pin group number above can be
In the test condition data setting device of the IC tester that refers to the pin group table with the pin group number and sets the pin data table for each device pin number that belongs to that pin group, each device of the IC element at the time of multiple simultaneous measurement Regarding pin numbers, the pin definition table for simultaneous measurement that defines which device pin number is assigned to which IC element, and each device pin number read from the above pin group table with that pin group number when setting the test conditions Means for reading the simultaneous measurement pin definition table according to the information shown, and setting test condition data in the pin data table for each read device pin number. Data setting device. 2. The simultaneous measurement pin definition table is configured by a register having, for each device pin number, the same number of bits as the device pin number. IC tester test condition data setting device. 3. The measurement pin definition table is a readable / writable memory, and each bit indicating the device pin number position read from the pin group table is encoded by a priority encoder in a predetermined order to simultaneously read the bits. 2. The test condition data setting device for an IC tester according to claim 1, wherein the measurement pin definition memory is read. 4. A redefinition memory in which data read from the simultaneous measurement pin definition memory is stored in association with the read pin group number, and a pin group number from which the pin group data is read is the second time. 4. The IC tester test condition data setting device according to claim 3, further comprising means for reading the redefinition memory with the pin group number in the subsequent cases. 5. An OR circuit is provided for ORing bit by bit the data read from the pin group table and the data read from the simultaneous measurement data. Item 5. A test condition data setting device for an IC tester according to any one of items 1 to 4.