JPH05298192A - Information processor - Google Patents

Abstract

PURPOSE:To improve the reliabilty of a memory by executing the copying of the memory content for a separate memory moduel by the other normal memory module when a fault occurs in one of the duplexed memory module and constitutin the duplexed memory module with the separate memory module. CONSTITUTION:When a duplex control circuit 11-1 in a master module 3-1A does not receive the signal from salve module 3-1B within a certain time, the circuit judges that a fault occurs and notifies it to a memory control circuit. The memory control circuit reads out the storage content from a corresponding memory array and transfers the storage content to a memory module 5 for back-up use via a system bus 2 after the circuit notifies the occurrence of the fault to the memory module 5 for back-up use. Thus, when the memory content of a normal module is copied on the memory module 5 for back-up use, the memory processes the access from a processor module as a new duplex module.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which redundant memory modules communicate read / write requests from processors with each other and execute the read / write requests.

[0002]

2. Description of the Related Art A conventional device of this type is shown in FIG. This figure is a block diagram shown in JP-A-57-6956, in which 1-1 to 1-m are processors, 52-A and 52-B are shared memory control units,
53-A and 53-B are shared memories, 55-A and 55-B
Is a priority selection circuit, 56-A, 56-B operation designation circuit, 5
7-A and 57-B are selection circuits, 59-A and 59-B are parity check circuits, 510-A, 510-B and 5
11-A and 511-B are crossing circuits. In addition, between the common memories, the priority selection result of the system designated in advance is used in both systems. It is assumed that the selection result of the priority selection circuit 55-A is used in both systems.

Next, the processor 1-1 uses the common memory 53.
The operation when accessing -A and 53-B will be described. The priority selection circuit 55-A receives an access request from the processor 1-1, and the common memory control circuit 52-A controls writing and reading from the processor 1-1 to the common memory 53-A, and at the same time, the common memory control device 52. -B
To the common memory control device 5
The 2-B also controls the write / read operation from the processor 1-1 in the same manner as the common memory 53-B.

The processor 1-1 uses the common memory 53-A,
When simultaneously accessing 53-B, parity check of addresses and data is performed by the parity check circuits 59-A and 59-B. For example, when the parity check circuit 59-A detects a parity error, the operation designating circuit 56-A of its own system is prohibited from writing / reading to / from the common memory 53-A through the crossing circuit 510-A. In parallel with the instruction, the processor 1-1 is notified of the detection of the parity error via the interface circuit 54A-1. At the same time, the parity error is notified to the common memory controller 52-B of the other system.

At this time, the common memory controller 52-B is
In response to a signal from the common memory control device 52-A, it may be instructed to prohibit writing and reading in the common memory 53-B, or it may operate as a single system. The common memory control device and the common memory are collectively called a memory module.

A conventional device of this type is shown in US Pat. No. 4,860,333. It has a central memory controller, which manages the memory blocks and is duplicated with two memory blocks. When a failure occurs, another block is newly allocated and duplicated by the configuration processor. At this time, the memory contents are copied from the normal memory block to the new memory block. This copy is executed on a dedicated bus built into the central memory controller and is independent of the system bus.

[0007]

Since the conventional fault-tolerant computer is configured as described above, if one of the duplicated memory modules fails, the repair is completed because it operates as a single system. Until then, there were problems that the reliability of the memory decreased and the system went down.

In another conventional example, in order to copy normal memory contents to a new memory block, it is necessary to provide a dedicated configuration processor and a copy bus, which causes a large amount of hardware and cannot be constructed at low cost. There was a point.

The present invention has been made to solve the above problems, and an object thereof is to obtain a memory configuration which can maintain a dual memory configuration even if a single failure occurs in the memory.

It is another object of the present invention to realize a copy of memory contents required for reconfiguring a dual memory with a small amount of hardware without using a dedicated bus.

[0011]

In an information processing apparatus according to the invention of claim 1, information processing in which a duplicated memory module communicates read / write requests from processors with each other and executes them synchronously In the device, a memory module different from the duplicated memory module and a failure detection of the other duplicated memory module in the memory module, a memory content transfer with the other memory module, and a signal communication of the response are performed. A redundant control circuit and a memory control circuit for controlling the operation of the memory and transferring the memory contents to the another memory module in accordance with the signal of the redundant control circuit are provided, and when a failure occurs in one of the redundant memory modules. , The other normal memory module performs a copy of the memory contents to said another memory module, To form a memory module and duplex serial another memory module is obtained to work.

In the information processing apparatus of the invention according to claim 2, in the information processing apparatus in which the duplicated memory modules communicate read / write requests from the processors with each other and execute them synchronously, A memory control circuit that controls the operation of the memory array, a refresh control circuit that controls the refresh operation of the dynamic memory, and a copy control circuit that controls the transfer of the memory contents to other memory modules in synchronization with the memory refresh cycle. When a failure occurs in one of the duplicated memories, the other normal memory module executes the copy of the memory contents to the other memory module in synchronization with the refresh cycle of the memory to configure and operate the duplicated memory module. It was done.

In the information processing apparatus according to the third aspect of the present invention, in the information processing apparatus including a processor, a dual memory module, and a dual system bus connecting these, the memory module transfers information to and from the dual system bus. A bus interface for controlling and a copy control circuit for copying memory contents to another memory module are provided, and one side of the duplex system bus is used to transfer the memory contents for copying.

[0014]

In the information processing apparatus configured as described above, when a failure occurs in one of the duplicated memory modules, the other normal memory module forms a duplicated memory module with another memory module and operates. Therefore, it is possible to avoid deterioration of reliability of the memory.

Further, the copy control circuit performs a small unit copy to another memory module in synchronization with the refresh cycle of the refresh control circuit.

Further, the copy control circuit and the bus interface 2 copy the memory contents using one side of the duplicated system bus in parallel with normal access.

[0017]

【Example】

Example 1. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1-1 to 1-m are the same as in the conventional example. Reference numeral 2 is a system bus, 3-1 to 3-n are memory modules, 4-1A and 4-1B are communication lines between the memory modules, and 11-1 and 11-2 are redundant control circuits for controlling communication between the memory modules. Reference numeral 5 is a backup memory module, and 12-A and 12-B are a transmission line and a reception line between the backup memory module and the active memory module, respectively. In addition, the memory module 3-
It is assumed that xA and 3-xB (where x is 1 to n) hold the same memory contents, and that the response to the processor is predetermined to be executed by 3-xA with priority (hereinafter Then the module to be executed with priority is called the master module, and the other is called the slave module). Transmission line 12-A between the backup module and another memory module
Are connected to the outputs of the memory modules 3-1 to 3-n of the active system by an open collector type signal driver.

Next, the operation when the processor 1-1 accesses the memory module 3-1 will be described.
Master module 3-1A and slave module 3-1
B receives the requests separately and upon successful completion of the process,
Communication is performed using the transmission line 4-1A. The duplication control circuit 11-1 notifies the memory control circuit (not shown) of the communication from the other module. When the master module 3-1A learns from the duplex control circuit 11-1 that the slave module 3-1B is operating normally, it responds to the processor 1-1. The slave module 3-1B does not operate, knowing from the duplex control circuit 11-1 that the master module 3-1A is operating normally.

If the duplicated control circuit 11-1 in the master module 3-1A does not receive the signal from the slave module 3-1B within a fixed time, it is determined that there is a failure and the memory control circuit is notified. The memory control circuit informs the response to the request of the processor and the occurrence of the failure by the signal from the duplex control circuit 11-1. At the same time, in order to notify the backup memory module 5 of the occurrence of a failure, the duplication control circuit 11-2 is instructed to transmit.

When the signal from the master module 3-1A is not received within a certain time, the duplicated control circuit 11-1 in the slave module 3-1B judges it as a failure and notifies the memory control circuit. After that, the slave module 3-1B becomes a master and returns a response to the processor 1-1 and a failure occurrence. At the same time, the backup memory module 5 is notified of the failure occurrence via the transmission line 12-A.

The duplication control circuit 11-2 which has received the response from the backup memory module 5 notifies the memory control circuit of the reception. The memory control circuit reads the stored contents from the corresponding memory array and transfers the stored contents to the backup memory module 5 via the system bus 2. The backup memory module 5 writes the transferred storage contents in the same manner as writing to a normal memory. At this time, the duplication control circuit 11-2 synchronizes the transfer instruction and its response with the signal lines 12-A and 12-B, and informs the memory control circuit. The memory control circuit transfers all the stored contents to the backup memory module 5 while receiving the signal from the duplication control circuit 11-2. When the backup memory module 5 is notified of a failure and no response is returned, it operates as a single system.

Example 2. FIG. 2 is a block diagram showing another embodiment of the present invention. In the figure, the case where there are three memory modules is illustrated. In the figure, 1-1 to 1-m,
Is the same as the conventional device, and 2, 3-1 and 5 are the same as those in the first embodiment. Reference numeral 21 is a duplex control circuit for controlling communication with other memory modules, and 22 is a communication line between the memory modules. The memory module can be paired with any memory module in the system configuration. Each pair of memory modules has a redundant control circuit 21.
, And the duplication control circuit 21 monitors only the communication from the memory module pair.

In FIG. 2, 3-1A and 3-1B are in the relationship of master and slave, respectively, and hold the same memory contents. The duplication control circuit 21 in the memory module 3-1A transmits to the communication line 22-1, and monitors only the signal of the communication line 22-2. The duplication control circuit 21 in the memory module 3-1B transmits to the communication line 22-2,
Only the 2-1 signal is monitored.

Next, the operation when the processor module 1-1 accesses the memory module 3-1 will be described. The duplication control circuit 21 in the master module 3-1A transmits a signal to the communication line 22-1 and monitors the communication line 22-2 when the processing is normally completed. Similarly, the duplex control circuit 21 in the slave module 3-1B is
When the processing is completed normally, a signal is transmitted to the communication line 22-2 and the communication line 22-1 is monitored. The duplication control circuit 21 of each module notifies the memory control circuit (not shown) of the signal of the duplicated counterpart module. When the master module 3-1A detects a normal operation, it returns a response to the processor module 1-1. The slave module 3-1B does not operate even if the normal operation is detected.

When the duplication control circuit 21 in the master module 3-1A or the slave module 3-1B does not receive a signal from the slave module 3-1B or the master module 3-1A within a certain time, it is judged as a failure and the processor Notify the module of the response and the occurrence of a failure.
When the processor module 1-1 detects a failure occurrence, the processor module 1-1 replaces the failed module with the backup module 5 with information for identifying the other party to the normal control module and the redundant control circuit 21 in the backup module 5. To send. After that, the memory contents of the normal module are copied to the backup memory module, and the access from the processor module is processed as a new duplex module.

Example 3. FIG. 3 shows an embodiment for copying the memory contents. In the figure, 2-1
2-2 is a duplicated system bus, 30-A, 30-
B is a memory module, 31 is a copy control circuit which notifies the refresh control circuit of the copy mode, and controls transfer of memory contents to another memory module in synchronization with the refresh operation in the copy mode, 32 is a bus interface, and 33 is A memory array using a dynamic memory, 34 is a refresh control circuit having a function of monitoring a time of 16 μs, reading a single word and detecting an error, and correcting and writing back if there is an error, 35 is a data Control and memory array 3 for error detection and correction of
A memory control circuit having a function of controlling the operation of 3;
-A and 36-B are signal lines for synchronizing the memory modules. The memory array 33 has a matrix structure,
Periodic refresh is required, and the refresh cycle is performed row by row at intervals of 16 μsec on average.

The operation of the refresh control circuit 34 will be described with reference to FIG. The refresh control circuit 34 determines whether it is the normal operation mode or the copy mode (step S1). In the normal operation mode, the time of 16 μs is monitored (step S2), a single word is read and an error is corrected, and if there is an error, a process of correcting and writing back is performed (step S4). Next, the row address is incremented, and when it overflows, the next column address is incremented by one (step S5). In mode judgment (step S
1) The refresh control circuit 34 uses the copy control circuit 31.
When the operation mode is changed to the copy mode by the command 311 from (3), the current refresh address is stored in the internal register (step S6). Then, the time of 16 μsec is monitored (step S7), the reading of the copy unit and the error detection are performed, if there is an error, the process of correcting and writing back is performed, and the copy cycle 341 is transmitted to the copy control circuit 31 (step S8). ). Refresh control circuit 34
Advances the row address next, and advances the next column address by one when it overflows (step S9). The refresh control circuit 34 determines whether or not the refresh address has completed a cycle of copying the contents of the memory array 33 (step S10). If the copy is not completed, the next copy unit is transferred after waiting 16 μs.
When the copy is completed, an end signal 342 is generated for the copy control circuit 31 (step S11), and the process returns to the mode determination.

Next, the operation of copying the memory contents from the memory module 30-A to the memory module 30-B will be described. The copy control circuit 31 in the memory module 30-A transfers the memory contents to the memory module 3
When transferring to 0-B, the copy mode is designated to the refresh control circuit 34 by the command 311. The refresh control circuit 34 transfers the data in copy units at 16-second intervals to the bus interface, transmits a copy cycle 341 to the copy control circuit 31, and sequentially advances the address. Upon receiving the copy cycle 341 from the refresh control circuit 34, the copy control circuit issues a transfer request to the bus interface 32 via 313 to transfer the address and data on the bus. Memory module 30
-B receives the address and data transferred from the memory module 30-A, and writes them in the memory array 33.
The memory module 30-A outputs a synchronization signal to the signal line 36-A in row address units. Memory module 30-B
When receiving the signal line 36-A, starts the normal refresh operation for the corresponding row address, and at the same time,
A sync signal is output to the signal line 36-B. Memory module 3
0-A transfers all the memory contents of the memory array 33 while confirming that the memory module 30-B is normally executing the refresh operation. When the copy operation is completed, a copy end signal 341 is output to the refresh control circuit 34 to cancel the copy mode. After that, the memory module 30-A and the memory module 30-B operate as a duplicated memory module. Since the copy unit transfer is performed in synchronization with the refresh cycle as described above, it can be used for normal memory access between the copy unit transfer and the next copy unit transfer. The copy mode setting conditions are, for example, those in the first embodiment. As described above, a memory duplication control circuit may be provided and set when one memory module fails. Further, the function of the system bus 2 may be used without using the signal lines 36-A and 36-B.

Example 4. Further, the copy control circuit 31 controls the bus interface 32 by the signal line 313 so that the normal memory access is executed by one side 2-1 of the duplex system bus and the copy is executed by using the other side 2-2. , Can be copied without disturbing normal processing.

By the way, in the above description, the case where the present invention is applied to the fault tolerant computer is illustrated, but it goes without saying that the present invention can be applied to an apparatus having a duplicated memory such as a controller for control or a communication device.

[0031]

Since the present invention is configured as described above, when a failure occurs in one of the duplicated modules, the communication means of the normal memory module communicates with other memory modules to ensure normal operation. Since the other memory module executes the copy of the memory contents and configures and operates the redundant module, the reliability of the memory can be improved.

Further, since the copy control circuit performs copying in small units in synchronization with the refresh cycle of the memory, the time between copying can be used for normal memory access.

Furthermore, since the memory contents are transferred using one side of the duplicated system bus, copying can be performed with little interruption to normal access.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing another embodiment of the present invention.

FIG. 3 is a configuration diagram of a third embodiment of a fault tolerant computer according to the present invention.

FIG. 4 is an operational flowchart for explaining a third embodiment of the fault tolerant computer according to the present invention.

FIG. 5 is a configuration diagram of a conventional device.

[Explanation of symbols]

1-1 to 1-m processor module 2 system bus 4-1A, 4-1B, 12-A, 12-B, 22 communication line 3-1 to 3-n memory module 5 backup memory module 11-1, 11-2, 21 Duplication control circuit 31 Copy control circuit 32 Duplication bus interface 33 Memory array 34 Refresh control circuit 35 Memory control circuit 36-A, 36-B Signal line

Claims (3)

[Claims] 1. An information processing apparatus in which a duplicated memory module communicates read / write requests from processors with each other and executes them synchronously, in a memory module different from the duplicated memory module and a memory module. Is a duplicated control circuit for detecting the other failure of the duplicated memory module, for transferring the memory contents to the other memory module, and for signal communication of its response, and for controlling the operation of the memory and the signal of the duplicated control circuit, A memory control circuit for transferring memory contents to another memory module is provided, and when one of the duplicated memory modules fails, the other normal memory module copies the memory contents to the other memory module. Run and configure a redundant memory module with another memory module to operate An information processing device characterized by: 2. In an information processing device in which a duplicated memory module communicates read / write requests from processors with each other and executes them synchronously, the memory module includes a memory control circuit for controlling the operation of a memory array and a dynamic control circuit. It has a refresh control circuit that controls the memory refresh operation and a copy control circuit that controls the transfer of memory contents to other memory modules in synchronization with the memory refresh cycle. An information processing apparatus, wherein the other normal memory module executes copying of memory contents to another memory module in synchronization with a refresh cycle of the memory to configure a redundant memory module to operate. 3. In an information processing device comprising a processor, a redundant memory module, and a redundant system bus connecting these to each other, the memory module has a bus interface for controlling the exchange of information with the redundant system bus, and memory contents to other memory modules. An information processing apparatus comprising a copy control circuit for copying, and transferring a memory content for copying using one side of a duplex system bus.