JPH04195646A - Multiplexed system - Google Patents

Abstract

PURPOSE:To copy data between memory devices without placing a load on CPUs by providing each memory device with a means which initiates read access to the other memory device and a means which writes data read out of the other memory in its memory. CONSTITUTION:All devices such as CPUs 3a and 3b, memory devices 4a and 4b, are disk controllers 5a and 5b are doubled around system buses 1a and 1b. In dual-system operation, the CPU 3a, memory device 4a, and disk controller 5a perform output operation to the system bus 1a and input operation from both the system buses 1a and 1b. Further, the CPU 3b, memory device 4b, and disk controller 4b perform output operation to the system bus 1b and input operation from both the system buses 1a and 1b. The memory devices 4a and 4b initiate read access to the opposite memory devices and write data, read out of the opposite devices, in their memories. Consequently, data can be copied between the memory device without any load on the CPUs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiplexing system, and particularly to a technique for matching memory data.

[Background Art] In recent years, there has been an increasing demand for fault-tolerant computing, high data integrity, and online maintenance and expansion, and multiplexing systems have been cited as a technology for realizing these requirements.

As a typical example of this multiplex system, FIG. 2 shows the configuration of a duplex system having dual system buses (la and lb).

The illustrated system has all devices duplicated, which guarantees the continuation of online operation in the event of a failure in one system, and also enables maintenance during online operation.

In this system, if a failure occurs in the memory device 4a and maintenance is performed, the subsequent memory device 4a and the memory group [
Since the data in memory device 4b do not match, it is necessary to copy the data in memory device 14b to memory device 4a before restoring the duplex operation.

Conventionally, the technology for realizing this copying was that the CPU was used as a memory device! 4b is read, and the data is read from memory device i4a.
It used the technique of writing in.

In addition, as other techniques, the memory group M4a and the memory device 4 are
There is a technology that connects memory devices 4a and 4b with a dedicated bus and realizes copying using this dedicated bus, or a technology that uses two memories, memory device 4a and memory device 4b, in common, such as the technology described in Japanese Patent Application Laid-open No. 2-9386. A technique is known in which a common control unit is provided for controlling the data, and a dedicated bus within the common control unit is used to realize copying.

[Problems to be Solved by the Invention] Among the above-mentioned conventional techniques, the technique in which a CPU performs data copy between memory devices has a problem in that the load on the CPU is extremely large and affects real-time processing.

In particular, in recent years, memory devices have become larger in capacity, and the actual copying time reaches several tens of seconds. If the system is time-divided so as not to affect real-time processing, the time required for maintenance will be enormous, and during this time it cannot be expected to operate as a normal duplex system.

In addition, the technology of connecting memory devices using a dedicated bus has the disadvantage of conflict between online system bus access and dedicated copy bus access. , there is a risk that both systems will go down due to a failure in the dedicated copy bus, and a complicated control mechanism is required to avoid this.

Furthermore, in the technique of providing a common control unit, since the CPU controls data copying between memory devices, the load on the CPU is extremely large and affects real-time processing.

Furthermore, a dedicated bus for copying is still required, and there is a risk that both systems will go down due to a failure in the common control unit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multiplexing system that can copy data between memory devices after maintenance of the memory devices without imposing a load on the CPU and with a small amount of hardware.

Means for Solving the Problem] To achieve the above object, the present invention provides a processor, a plurality of multiplexed memory devices, and a bus connecting the processor and the multiplexed memory devices. A multiplexing system comprising:

Each of the memory devices is connected to any other memory device via the bus.
A first multiplexing system is provided, comprising issuing means for issuing a read access to the above memory device, and writing means for writing read data read from another memory by the read access into its own memory.

The present invention also provides a method for connecting a processor and a plurality of multiplexed memory devices, which can be attached to the multiplexed system while the system is in operation, and a processor and a plurality of multiplexed memory devices. A multiplexing system having a bus.

Each of the memory devices includes a detection means for detecting the attachment;
and means for copying data from one or more other memory devices to its own memory via the bus, which is activated when the detection means detects attachment. provide.

Note that in the first multiplex system, each of the memory devices can be installed in the multiplex system while the system is in operation, and a detection means for detecting attachment to the own system; the issuing means for issuing a read access to one or more other memory devices via the bus for data shared in multiple systems; and the writing means for writing the read data read into the own memory.

In this case, the first processor, the multiplexed memory devices, and the first bus connecting the first processor and the multiplexed memory devices;
and a second said processor.

The plurality of multiplexed memory devices and a second bus connecting the second processor and the multiplexed memory devices may be provided.

Further, the detection means may be a means for detecting power-on.

Further, in the first multiplex system, each of the memory devices can be installed in the multiplex system while the system is in operation, and a detection means detects attachment to the system, and the detection means detects attachment. will be activated if the issuing means for issuing a read access to one or more other memory devices via the bus over an address space shared by the multiplexed memory devices;

The memory device may further include the writing means for writing data read from another memory by the read access into the same address space of the own memory as the read address space.

[Function] According to the first multiplexing device according to the present invention, each memory device issues a read access to one or more other memory devices via the bus, and receives read access read from other memories. Write to write data to own memory. Accordingly,
Data copying between memory devices can be realized without providing a dedicated bus or placing any load on the CPU.

Further, according to the second multiplexing system according to the present invention, each memory device detects its own attachment while the multiplexing system is operating and activates the copying means, so there is no need to stop the system. , perform maintenance on memory devices, and
It is possible to automatically copy data between memory devices and return to a multiplexed state.

[Example 1] An example of a multiplexing system according to the present invention will be described below.

First, FIG. 2 shows the configuration of a multiplexing system according to this embodiment.

As shown in the figure, the multiplex system according to the present embodiment has system buses 1a and 1b as the center, and CPU 3a
, 3b, memory devices 4a, 4b, disk controllers 5a, 5b, disk devices 6a, 6b, etc., are all duplicated.

During dual system operation, the CPU 3a, memory device i4a, and disk controller 5a output to the system bus 1a, and receive input from both system buses 1a and 1b.

Further, the CPU 3b, memory device 4b, and disk controller 4b output to the system bus 1b.

Input is from both system buses 1a and 1b.

Inputs from both systems to each device are checked by the input check circuit of each device, and the normal input side is selected and used.

The CPs 03a and 3b process commands based on data from the memory devices 1i4a and 4b, and the disk controller 5a
, 5b are disks 6a, 6b and memory device 4a, respectively.
Controls data transfer with 4b.

A control signal 14a between the disk controllers 4a and 4b,
The reference numeral 14b communicates the completion of data transfer between the disks 5a and 5b and the disks 6a and 6b, and is used to synchronize the startup of the system bus.

BCs 2a and 2b are mechanisms that supply clocks to the respective system buses 1a and 1b and also control the buses, and control signals 7a and 7b are for synchronizing the clocks.

Next, FIG. 1 shows the configuration of the memory devices 4b, 4b.

In the figure, a power-on detection circuit 401 is a circuit that notifies the controller 402 by a signal 412 that power has been supplied to the memory device.

The input selector 405 converts the inputs from the system buses 1a and 1b of both systems into judgment results 424-. 425.

The copy completion flag 403 is set when the copy is completed and when the power is restored to the entire system, and is cleared while the copy is not completed after being installed during online operation, and is connected to the controller 402 by a signal 413.

A signal 413 is an interface that communicates the status from the copy completion flag and set and reset requests from the controller.

When the ECC circuit 408 writes the data signal 416 to the memory array 409, it generates a redundant code and outputs it to the signal 426 together with the generated signal and the data signal. This is an error check and correction circuit that receives redundant codes and read data, corrects 1-bit errors, and outputs the signal 416.

Address generation circuit 407 receives request signal 419 from controller 402, generates and updates an address for read data during copying, and outputs signal 423.

The controller 402 is a circuit that controls the entire memory device, and receives control signals 41 from the system bus.
4, it executes the read/write process of the memory array, and also controls the copy operation when the attachment is detected.

Control signals from the controller 402 to the system buses 1a and 1b include a signal 421, an output sofa 410,
411.

The output sofas 410 and 411 are buffer circuits whose outputs are controlled by signals 420 and 422.

Memory array 409 is a storage circuit, and address signal 4
15, data signal 426. It is also connected to a read/write and refresh control signal 418 .

Next, FIG. 3 shows the configuration of the CPUs 3a and 3b.

As shown in the figure, the CPUs 3a and 3b include a processor 301, an address translation mechanism 302, a cache memory mechanism 303, and the like.

Since the CPUs 3a, 3b are not directly related to this embodiment, detailed description thereof will be omitted.

The multiplexing system according to this embodiment will be explained below.

A data copy operation between memory devices after memory device maintenance will be described.

FIG. 4 shows a control flow of copy processing by the controller (402 in FIG. 1) in the memory devices 4a and 4b. below,
The operation will be explained according to this flowchart.

In FIG. 1, when the memory device is installed in the system after maintenance and power is supplied, the power-on detection circuit 401
This is detected and notified to the controller 402 by a signal 412.

Upon receiving the notification, the controller 402 performs step (
41), the address generation circuit 407 is caused to generate the start address of the pre-allocated address space via the signal 419. A pre-allocated address space refers to a space that includes at least an address space that stores data that is shared with other memory devices. Usually, this address space that stores data that is shared with other memory devices is It is allocated to two memory devices and shared by the two memory devices.

Next, in step (42), the system bus use request included in the signal 421 is turned on, and the signal 420
．． The system bus use request gate included in 422 is enabled and output to both systems.

Step (43) waits for a response to the system bus use request issued in step (42).

The right to use the system bus is controlled by BC in FIG.

The same type of BC responds to the system bus use request when it responds to the request.

If there is a response from both systems, the controller 402 proceeds to step (44) and turns off the system bus use request signal.
L, read access command included in signal 421
At the same time, the address signal 423 is output to the system buses 1a and 1b of both systems.

In FIG. 2, the other memory device that receives the read access responds by outputting the data to the system bus that received the read access.

Note that after maintenance, the installed memory device returns an error response to read access until data copying is completed. Also.

It is assumed that normal operation is performed for write access.

Step (45) is waiting for a response to the read access command issued in step (44).

If there is a response, the read data input from the system bus is sent to the memory array 409 via the input selector 405 and the ECC circuit 408 in step (46).
write to.

Also, at this time, the address is signal 41 in the memory array.
5, the write timing signal is input via signal 418.

Step (47) is to check whether the address generated by the address generation circuit 407 is the final address of the space allocated in advance for data copying.

Step (48) is to update the output of the address generation circuit via the signal 419. Ste 4 tubes (49
) causes the copy completion flag 403 to be set via the signal 413.

By setting this completion flag, data copying between memory devices is completed, and the multiplexing system according to this embodiment is restored to a duplex state. The completion flag is used for system state management, etc.

As described above, according to this embodiment, when performing maintenance and replacement of memory devices, it is possible to automatically match the data contents of multiple memory devices simply by placing a load on the processor and installing the memory devices. .

Although this embodiment has been described with respect to a dual multiplex system, it can be similarly implemented in a triplex or higher multiplex system.

[Effects of the Invention] As described above, according to the present invention, multiplexing is possible that allows data copying between memory devices after maintenance of the memory devices to be performed without imposing a load on the CPU and with a small amount of hardware. system can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the overall configuration of a multiplexing device, FIG. 3 is a block diagram showing the configuration of a CPU, and FIG. 2 is a flowchart showing a control procedure for data copy processing by the controller of the memory device. 4a, 4b... Duplex memory device, 402... Controller controlling copy processing and read/write processing, 407... Address generation circuit, 401... Power-on detection circuit, 403... Copy Completion flag. Applicant Hitachi Co., Ltd. Urasakusho Agent Patent Attorney Tomi 1) Interest Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A processor, a plurality of multiplexed memory devices,
A multiplexing system comprising a bus connecting a processor and a plurality of multiplexed memory devices, wherein each memory device connects to any other one via the bus.
A multiplexing system comprising: issuing means for issuing a read access to the above memory device; and writing means for writing read data read from another memory by the read access into its own memory. 2. A multiplexed system comprising a processor, a plurality of multiplexed memory devices that can be attached to the multiplexed system during operation, and a bus that connects the processor and the multiplexed memory devices. Each of the memory devices includes a detection means for detecting attachment of the memory device to the multiplex system, and one or more other memory devices connected to the bus via the bus, which is activated when the detection means detects the attachment. 1. A multiplexing system comprising: means for copying data in a memory device to its own memory. 3. The multiplexing system according to claim 1, wherein each of the memory devices is capable of being installed in the multiplexing system while the system is in operation, and further comprising a detection means for detecting attachment to its own system. , the issuing means for issuing read access to any one or more other memory devices via the bus for data shared in multiple systems, which is activated when the detection means detects attachment; 1. A multiplexing system comprising: the writing means for writing read data read from another memory into its own memory. 4. The multiplexing system according to claim 1, wherein each of the memory devices is attachable to the multiplexing system while the multiplexing system is in operation, and includes detecting means for detecting attachment to the system; the issuing of a read access to any one or more other memory devices via the bus over an address space shared by the multiplexed memory devices, which is activated when the means detects attachment; and the writing means for writing read data read from another memory by the read access into the same address space as the read address space of the own memory. 5. The multiplexing system according to claim 3, wherein the first processor and the multiplexed memory devices are connected, and the first processor and the multiplexed memory devices are connected. a first bus, a second processor, a plurality of multiplexed memory devices, and a second bus connecting the second processor and the multiplexed memory devices; A multiplexing system comprising: 6. The multiplexing system according to claim 3, wherein the detection means is means for detecting power-on.