JPH05298097A - Information processor - Google Patents

Abstract

PURPOSE:To improve the processing capability of a processor by providing a computer having the pipeline instruction processing function with the score boarding function to limit instructions up to the position, where dependence on the data flow occurs, and again inserting an instruction at the rear of this position to continue the processing without erasing contents of a pipe and performing the processing without waiting for several cycles till reading of data into a cache. CONSTITUTION:In the process of processing of an instruction pipeline, dependence on the data flow of plural instructions on a prefetch queue 2 and the pipeline is recorded in a score board 8 by a comparator 7. When a cache miss detector 9 detects the occurrence of a cache miss with respect to a certain instruction set, this instruction set is temporarily stored in a queue 11 only for saving use to process the next instruction. During this time, a selector 12 checkes the score board 8 to detect positions of the instruction where the cache miss occurs and the instruction where dependence on the data flow occurs, and the progress of instructions is adjusted by a timing circuit 14 to insert the former instruction before the position of the instruction where dependence on the data flow occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for accelerating processing in a computer having a pipeline processing function by moving an instruction causing a cache miss backward in the pipeline.

[0002]

2. Description of the Related Art Generally, in a 32-bit microprocessor, a pipeline system is used as a means for speeding up. The interior of the processor is made up of stages of several functional blocks, with each block processing an input and passing the result to the next block. As a conventional example, FIG. 4 shows a block diagram of the pipeline, and FIG. 5 shows an outline of the pipeline processing. This FIG. 4 and FIG.
2 Bit Microprocessor Introduction "(written by Munehiro Minami, CQ Publishing Co.).

In FIG. 5, 1 is a bus interface (BCU), and 2 is a prefetch for storing instructions.
A queue (PFU) 3 is a decoder unit (IDU) that decodes an instruction. Reference numeral 4 is a stage (EAG) for generating and converting an address. 5 is an execution stage (EXU).

Next, an outline of the flow of the pipeline is shown in FIG. The instructions read by the bus access by BCU1 are accumulated in the prefetch queue of PFU2, and IDU
3 and is decoded. Then, the address information is passed from the decoder to the EAG 3, the address is generated and converted, and the EXU 5 executes the address. Here, it is assumed that a number of consecutive instructions are accumulated in the prefetch queue 2 in order.

FIG. 6 shows the state of the pipeline in the case where instructions 1 are sequentially accessed. 60
1 to 608 correspond to one cycle each. In cycle 601, the instruction 1 is read by the bus access 1. Next, in cycle 602, the instruction 1 is passed to the decoder 3, and at the same time, the instruction 2 is read by the bus access 1. In cycle 603, instruction 1 and instruction 2 move to the next stage, respectively, and a new instruction 3 is fetched. And cycle 604,
Each instruction is simultaneously processed in each stage in order as in cycle 605. In this way, the function of dividing one instruction into several stages and simultaneously processing a number of processes in each stage is called a pipeline control function.

However, in the actual processing flow, there are variations in the processing time of each stage of the instruction, so that the reading / writing of the operand, the insertion of the memory-referenced bus cycle in the address calculation, and the data -Processing does not simply flow as in Fig. 6 due to the occurrence of cache misses in fetching.

In the prior art, when a cache miss occurs, when instruction 1 detects a cache miss at cycle 603 in FIG. 5, the flow of the pipeline stops there and waits until the data is read from the memory into the cache. After being read into the cache from the memory, it is possible to prevent the contents of the pipeline from being erased by shifting to the same state as the cycle 604 when the processing is smoothly performed.

[0008]

SUMMARY OF THE INVENTION In the prior art means,
Although it has the effect of preventing the contents of the pipeline from being erased, the flow of the pipeline must be stopped when a cache miss occurs until data is read from memory into the cache. Also, loading the data from memory can take a considerable amount of time, which causes the process to wait many cycles, wasted during that time.

The present invention has been made in order to solve the above problems, and when the cache miss occurs, the processing flow is performed without stopping as much as possible, and as a result, the processing performance of the pipeline control function is improved. The purpose is.

[0010]

An information processing apparatus according to the present invention is a comparison means for comparing addresses of register operands and memory operands designated by all a plurality of instructions stored in a prefetch queue and an instruction pipeline. And a recording means for adding the same order as the execution order of the instructions to the operand and recording the same when an instruction specifying the same operand is detected from the output of the comparing means, and an instruction on the instruction pipeline. Detecting means for detecting whether or not a cache miss has occurred in the instruction by comparing with the cache at the stage of generating and converting the address, and receiving the output of the cache miss detecting means, pipeline the instruction when the cache miss occurs. The removing means for removing from above and the cache miss occurrence instruction removed from the instruction pipeline by the removing means By referring to the storage means to be stored and the record obtained by the recording means, the position on the pipeline of the instruction stored by the storage means and the instruction in which the data flow dependency occurs is detected and the pipeline position is detected. Selection means for selecting the position to be returned to, the advance of the instruction pipeline at the position of the instruction removed from the instruction pipeline at the time of occurrence of a cache miss, and the pipeline at the position for inserting the instruction separately stored in the instruction pipeline. A timing adjusting means for adjusting the advance and a returning means for returning an instruction separately stored on the pipeline adjusted in advance by the timing adjusting means to the position selected by the selecting means are provided. ..

[0011]

In this invention, when a cache miss is detected by the cache miss detecting means, the instruction is removed from the pipeline by the output signal by the removing means and stored in the storing means. At the same time, the output signal of the detecting means is received and selected. The means refers to the recording means, determines on the pipeline the position at which the instruction stored in the storage means is returned, the progress of the pipeline is adjusted by the timing adjustment means, and the stored instruction is returned by the return means to the pipeline. Turn it back on.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Further, in FIG. 1, the same reference numerals are used for the same or corresponding parts as in the conventional example of FIG. In the present embodiment, it is assumed that a cache miss has occurred at the first instruction (instruction 1) in the instruction pipeline, and instruction 1 has a data flow dependency with instruction 4 which is three instructions behind.

In FIG. 1, 1 is a bus interface (B
CU), 2 is a prefetch queue (PFU), 3 is a decoder (IDU), 4 is address generation / conversion (EA).
G) and 5 are the stages of execution (EXU), respectively.
The processing flow is also as described above. 6 is a data fetch stage, which is a stage for fetching data based on the address generated and converted by the EAG 4. Reference numeral 7 is a comparator for comparing the register operands and memory addresses of all the instructions read by the bus access and checking which instruction read so far and which data flow dependency has occurred. Reference numeral 8 is a scoreboard that holds the result of examination by the comparator 7. 9
Checks the address generated / converted by EAG4 to see if a cache miss has occurred. Reference numeral 10 denotes a remover that receives an output signal from the cache miss detector 9 and sends a miss instruction to the storing means to remove the instruction from the pipeline when a cache miss occurs in the EAG 4. 11
Is a miss instruction save queue for storing the instructions removed from the pipeline by the remover 10. 1
A selector 2 receives the output signal from the cache miss detector and checks the scoreboard 8 to detect the position on the pipeline of the miss instruction and the instruction having the data flow dependency. Reference numeral 13 is a means for receiving the output signal of the selector 12 and returning the miss instruction stored in the miss instruction save queue 11 to the designated position on the pipeline. Reference numeral 14 denotes a timing adjusting circuit which receives the output signal of the selector 12 and gives a position where the stored instruction is returned to the pipeline from the position where the preceding instruction is advanced by one and the following instruction is stopped to return the miss instruction.

FIG. 2 is a structural diagram of the scoreboard used in the embodiment of FIG. In FIG. 2, prefetch queue 2
It is assumed that 5 instructions are stored in, but naturally the number can be increased as much as possible. In FIG. 2, 201 is EAG.
The data indicating the occurrence of the data flow dependency between the 4th instruction and the 4th instruction in the rear, the 201st row and the 211th column is the previous instruction, the 201st row and the 212th column is the second previous instruction, and the 201th row and the 216th column is the sixth previous instruction. Data representing the occurrence of a data flow dependency during is recorded by the output of the comparator. In the embodiment of FIG. 2, the data is 0, 0, 1, 0, 0, 1 in order, and the instruction in the EAG 4 is the instruction 2 and the PF which is the second from the beginning of the PFU 2, which is three instructions before.
Indicates that the instruction at the end of U2 and data flow dependency have occurred. That is, if the instruction causing the cache miss in the EAG4 is the instruction 1, it indicates that the instruction 1 has the data flow dependency with the instruction 4 and the instruction 7. Data is updated every time an instruction is read by bus access, and in FIG. 2, the flag is shifted downward and a flag indicating a data flow dependent state with the newly read instruction is set. At this time, column 216 in FIG. 2 is updated over all rows. The range in which the occurrence of data flow dependency can be recorded is the instruction whose head is in EAG4, and the last is the last in PFU2, and the occurrence of more data flow dependency is not recorded.

Next, the operation of the processing performed when a cache miss occurs in the pipeline and the score board configured as described above will be described with reference to the flowchart of FIG.

If a cache miss occurs, step 30
At 1, the cache miss detector refers to the scoreboard and does nothing if the instruction and the dataflow dependency occur between the n + 1th instruction. If not, a signal is sent to the remover in step 302 to switch the instruction flow and the nth instruction is sent to the miss instruction save queue 10.

In step 303, the selector 11 refers to the scoreboard 8 to check which instruction after the removed instruction has the miss instruction save queue and the data flow dependency. If there is, the selector determines the insertion position in response to the output signal of the cache miss detector 9 in step 304, and receives the output signal of the selector to determine the timing circuit 1.
4 is inserted by means 13 for advancing the preceding instruction from that position by one, stopping the instruction behind it, and returning the instruction stored on the pipeline to the empty position. If an instruction that causes data flow dependency is not detected on the scoreboard, advance all instructions on the pipeline by one, stop reading instructions by bus access, and execute PF.
Returns the instruction stored at the end of U2.

Next, an example of instruction movement when a cache miss occurs will be described with reference to FIG. 401 of FIG.
.About.407 correspond to one cycle, respectively. FIG. 4 is a diagram in the case where the instruction 1 causes a cache miss and causes an instruction 1 and data flow dependency to be the instruction 4.

When a cache miss occurs in the instruction 1 in the cycle 403, the cache miss detector 11 refers to the scoreboard to check whether the data flow dependency with the instruction 2 has occurred. In this example, instruction 1 and instruction 2
In the cycle 404, the instruction 1 receives the output signal of the cache miss detector, and the remover 10 removes the instruction 1 in the pipeline where the miss occurs from the pipeline. It is stored in the instruction save queue 11. The instructions on the other pipelines each go one step forward. The selector 12 receives the output signal of the cache miss detector 9 and refers to the scoreboard to PFU2.
Also, the miss occurrence instruction 1 and the data flow dependent instruction 4 are detected from the IDU 3 to determine the insertion position of the stored instruction. When the insertion position is determined, the next cycle 405
The timing circuit 14 moves to the selector 1
In response to the output signal from the instruction 3, the instruction before the instruction 4 is advanced by one, the instruction after the instruction 5 is stopped, and the insertion position of the instruction 1 stored in the miss occurrence save queue is created. Similarly, the means 13 for returning to the pipeline receiving the output signal from the selector 12 inserts the following instruction 1 stored in the miss instruction save queue before the instruction 4 in the cycle 405.

As can be seen from FIG. 4, even if a cache miss occurs, the instruction is delayed for only one cycle.

[0021]

As described above, according to the present invention, when a certain instruction causes a cache miss, the selecting means refers to the recording means obtained from the comparing means in accordance with the output signal of the detecting means, which detects the cache miss, and then outputs the data. By finding the position of the instruction where the flow dependency occurs and adjusting the progress speed of the instruction on the pipeline by the timing adjusting means, the instruction is moved backward to the position where the data flow dependency occurs in the next cycle, and the cache is cached. The pipeline processing of instructions can be continued by simply wasting one cycle processing without waiting until the data is read in, thereby improving the processing capacity of the computer with the pipeline function. Becomes

[Brief description of drawings]

FIG. 1 is a block diagram of a pipeline configuration according to an embodiment of the present invention.

FIG. 2 is a structural diagram of a scoreboard according to the present invention.

FIG. 3 is a flow chart of the operation in the present invention.

FIG. 4 is a schematic diagram of pipeline processing when a cache miss occurs in the present invention.

FIG. 5 is a block diagram of a conventional pipeline.

FIG. 6 is a schematic diagram of pipeline processing according to a conventional technique.

[Explanation of symbols]

 7 Comparing Means 8 Recording Means 9 Cache Miss Detecting Means 10 Instruction Removing Means 11 Cache Instruction Storing Means 12 Selecting Means 13 Saving Instruction Returning Means 14 Timing Adjusting Means

Claims (1)

[Claims] 1. A computer system comprising a cache memory, a prefetch queue for prefetching instructions to be executed in advance, and an instruction pipeline, and in a computer system for performing pipeline processing of instruction execution, all stored in the prefetch queue and the instruction pipeline. Comparing means for comparing addresses of register operands and memory operands designated by a plurality of instructions, and when an instruction specifying the same operand is detected from the output of the comparing means, the same order as the execution order of the instructions is detected. Recording means for adding and recording to the operand, and detection means for detecting whether or not a cache miss has occurred in the instruction by comparing the address of the instruction on the instruction pipeline with the cache at the stage of generation and conversion. When the cache miss occurs in response to the output of the detecting means, the instruction is pipelined. Removing means for removing the cache miss instruction from the instruction pipeline by the removing means, and a record obtained by the recording means, and stored by the storing means. And the selection means for detecting the position on the pipeline of the instruction that has the data flow dependency and the position for returning to the pipeline, and the position of the instruction removed from the instruction pipeline when the cache miss occurs. The timing adjustment means for adjusting the advance of the instruction pipeline and the advance of the pipeline at the position where the instruction separately stored in the instruction pipeline is inserted, and the way of advancing by the timing adjustment means to the position selected by the selecting means. An information processing apparatus, comprising: a return unit for returning an instruction separately stored on the adjusted pipeline.