JPH05289990A - Method for transferring data - Google Patents

Abstract

PURPOSE:To provide a data transfer method allowing a controller to use only an output port, a target, or an input port for a/BSY signal indicating the transmission of a data frame. CONSTITUTION:When a target 11, 12, or 13 receiving a token to itself tries to transfer a data frame, the controller 10 transits a data line 1 to a low level before outputting the succeeding token. At the time of checking the low level of the data line 1 by the output timing of the token, the controller 10 aborts the output of the token, asserts a/BSY signal and outputs a clock necessary for the transfer of the data frame to a clock line 2. The target 11, 12, or 13 informs the transfer end of the data frame to the controller 10 by holding the data line 1 at a high level. When the data line 1 is in the high level based upon the output timing of the clock, the controller 10 negates the/BSY signal and restarts the distribution of tokens.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method for serially transferring a data frame between a plurality of devices.

[0002]

2. Description of the Related Art Data transfer methods are roughly classified into parallel transfer using a parallel data bus and serial transfer using a serial data bus. Although parallel transfer is suitable for high-speed data transfer, it leads to an increase in the number of pins of devices such as microprocessors and ICs. A one-chip microprocessor used in audio-video equipment and household appliances uses serial transfer, which leads to a reduction in the number of pins, because serial transfer is sufficient in terms of transfer speed. 2. Description of the Related Art In recent years, as devices have become more sophisticated, a plurality of microprocessors have been built in one device, such as a video tape recorder and a camera-integrated video. These microprocessors do not operate independently, but operate while performing data transfer with each other using a serial data bus. Further, not only a microprocessor but also various ICs and LSIs can be connected to this serial data bus.

As a conventional data transfer method by serial transfer in a device, Japanese Patent Application No.
-102444 "Data Transfer Method" is available. In the above application, in addition to the data line and the clock line, a control line (hereinafter referred to as a / BSY line) indicating whether the data being transferred through the data line is a token or a data frame.
Is used. The device that is the controller is / BS
When the Y line is at a high level (hereinafter abbreviated as high), the tokens are sequentially distributed to the devices connected to the bus. The device that receives the token, acquires the right to use the bus, and tries to output the data frame becomes the master by driving the / BSY line to a low level (hereinafter abbreviated as “low”), and uses the bus. Notify other devices. If the / BSY line changes to low, the controller stops the token output and outputs the clock required for data frame transfer. The master starts transferring the data frame according to this clock. The master returns the / BSY line high when the data frame transfer is complete. The controller detects that the / BSY line has transitioned high and begins token distribution again.

According to this method, there is provided a data transfer method in which no transfer collision occurs, no modulation is required for transfer, and a data frame having an arbitrary pattern can be transferred.

[0005]

However, the above-mentioned data transfer method (Japanese Patent Application No. 3-102444) has the following problems.

The / BSY line is driven low by the master device and all devices are / BS
Since it is necessary to monitor the Y line, there is a problem that all devices connected to the bus must reserve an input / output port for the / BSY line.

In particular, when a device other than the controller (hereinafter referred to as a target) monitors the / BSY line with an external interrupt, two ports, an external interrupt input port and an output port, are necessary for the / BSY line. There was a problem called.

When the device checks the level of the / BSY line by the serial reception interrupt without using the external interrupt, the master receives the / BSY line between the generation of the serial reception interrupt and the checking of the level. There is a problem that the level of the / BSY line may be erroneously recognized by operating.

As a method for avoiding this erroneous recognition, the master operates the / BSY line after a certain period of time has passed after the transfer of one transfer unit is completed, and devices other than the master are within a certain period after the serial reception interrupt is generated. A possible method is to check the / BSY line. That is, erroneous recognition of the / BSY line is avoided by defining the operation timing of the / BSY line. However, since this method requires checking the / BSY line within a fixed period, the serial reception interrupt must be accepted even during execution of other interrupt processing. Also,/
A hardware timer or a software timer is required to determine the operation timing of the BSY line. As described above, the method of preventing erroneous recognition by defining the operation timing of the / BSY line has a problem that there are many restrictions in system design.

The present invention solves the above-mentioned conventional problems. The controller uses an output port for the / BSY line, the target uses an input port for the / BSY line, and the / BSY line is interrupted by an external interrupt. An object of the present invention is to realize a data transfer method that does not require an output port even when monitoring with a port and does not have the above-mentioned restrictions even when the / BSY line is monitored with a serial reception interrupt.

[0011]

In order to achieve this object, in the data transfer method of the present invention, the controller detects the level of the data line at a predetermined detection timing, and the data line is detected at a high level at the detection timing. If so, the control line is kept at the false level and the token is transmitted until the next detection timing, and if the data line is at the low level at the detection timing, the control line is kept at the true level until the next detection timing and the clock line is changed to the clock line. 1
The transfer clock for the transfer unit is output. On the other hand, when the target receives the token addressed to itself and starts the transfer of the data frame, it waits until the next detection timing until the transfer of each data forming the data frame is completed. Is changed to a low level, and the data frame is transferred using the data line in synchronization with the transfer clock output from the controller.

[0012]

According to the present invention, when the target that has obtained the token serves as a master to transfer the data frame by the above-described method, the controller detects the level of the data line during the transfer of the data frame. Output a low level on the data line. If the data line is at the low level at the detection timing, the controller does not transmit the token and outputs the clock necessary for the transfer of the data frame of one transfer unit to the clock line. The target that has become the master uses this clock to transfer data frames.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a system for performing data transfer using the data transfer method according to an embodiment of the present invention. In FIG. 1, a microprocessor 10,
Reference numerals 11, 12, and 13 are one-chip microprocessors, which are connected to each other via a bus composed of three signal lines: a data line 1, a clock line 2, and a / BSY line 3. The data line 1 is a signal line for transferring serial data, and is commonly connected to the data input port 16 and the data output port 17 of each microprocessor. The data output port 17 is an open drain type output port so that a plurality of microprocessors may simultaneously drive the signal lines. Microprocessor 10
Outputs a clock for inputting / outputting serial data to the clock line 2 from the clock output port 18, and the other microprocessor receives this clock at the clock input port 15. The / BSY line 3 is a signal line for the / BSY signal. This signal is a negative logic signal and is output by the microprocessor 10 at the request of the microprocessor which starts the transfer of the data frame. If the / BSY signal is high, no microprocessor is transferring data frames. When the / BSY signal is low, data frames are being transferred between the microprocessors. The / BSY signal is input to the microprocessor 11, the microprocessor 12, and the microprocessor 13.

Regarding the operation example when the data transfer method of the present invention is implemented in the system configured as described above,
This will be described below.

First, the timing of serial data and clock will be described with reference to FIG. FIG. 2 is a timing diagram showing signals on the data line 1 and the clock line 2. As shown in FIG. 2A, the serial data transferred on the data line 1 is output at the falling edge of the clock. When capturing serial data, capture at the rising edge of the clock. The clock cycle is Ta. Transfer is performed intermittently in 8-bit units. Eight clocks required for transfer of 8-bit data are defined as byte clocks.
As shown in FIG. 2B, the byte clock is output intermittently at a cycle of Tb.

Many 1-chip microprocessors have 8
The hardware implements the function of serially transferring data bit by bit. Here, this hardware is called a shift buffer. The shift buffer is composed of a shift register and peripheral circuits, and is used for inputting data using a clock supplied from outside the microprocessor (hereinafter referred to as an external clock) or a clock generated inside the microprocessor (hereinafter referred to as an internal clock). Output. When serial data is output, MSB is sequentially output at the falling edge of the clock, and when serial data is input, MSB is sequentially input at the rising edge of the clock.

The output port of serial data output from the shift buffer is the data output port 17, and the input port of serial data input to the shift buffer is the data input port 16. The clock port of the shift buffer does not have independent input and output, only a clock input / output port. This port functions as an output port when the shift buffer transfers data with an internal clock, and as an input port when it transfers data with an external clock. Since the microprocessor 10 needs to output a clock,
It operates on an internal clock and the other microprocessors operate on an external clock. Therefore, the clock input / output port is the clock output port 1 in the microprocessor 10.
8 and as a clock input port 15 in other microprocessors.

Next, terms used in this embodiment will be described. “Master”: A microprocessor that acquires the bus usage right and starts transferring a data frame is called a master. Any of the microprocessors 10, 11, 12, and 13 can be a master, but a plurality of microprocessors cannot be masters at the same time.

"Slave": A microprocessor designated by a master as a data frame transfer partner is called a slave. The data frame is transferred from the master to the slave. When the master transfers data frames to multiple microprocessors (broadcast),
There are multiple slaves. If the / BSY signal is high, there is no master or slave in the system.

"Controller": Among the microprocessors connected to the bus, the microprocessor that outputs a clock is called a controller. There is only one controller in the system. In the system of FIG. 1, the microprocessor 10 is the controller. The controller also outputs the token described later.

"Target": A microprocessor connected to the bus, and a microprocessor other than the controller is called a target. In FIG. 1, the microprocessor 1
1, microprocessor 12, microprocessor 13
Is the target.

"Token": 1-byte data output by the controller to arbitrate the right to use the bus.
The microprocessor that receives the token has the right to output a data frame using the bus, ie to become the master.

"Data frame": The minimum unit of data transfer is called a data frame. Data frame is header,
It consists of user data, check bytes, and reception response data.

Next, the format of the token will be described with reference to FIG. FIG. 3 is a format diagram of a token. The token is composed of 1 byte and is output by the microprocessor 10, which is a controller. bit6
~ ADR of bit4 is the destination address of the token, and describes the address of the destination microprocessor of the token. A unique address (0 to 7) is assigned to each microprocessor connected to the bus.
The allocation of this address is shown in (Table 1).

[0026]

[Table 1]

As shown in (Table 1), four kinds of addresses 0 to 3 are actually used among addresses 0 to 7, but a maximum of eight microprocessors are provided on this bus. It is possible to connect. Format number (FMT) is recorded in bit3, bit2, bit1, and LSB. The format of the data frame described later differs depending on the format number. Here, the format number is "0
000 (binary display) ".

Next, the format of the data frame will be described with reference to FIG. FIG. 4 is a format diagram of a data frame. The data frame is address data 60,
Control data 61, user data 62, error detection code (check byte) 63, reception response data 64
Consists of. The master has address data 60, control data 61, user data 62, error detection code 63.
When the output of is completed, the slave outputs 1-byte reception response data 64 at the next byte clock.

The address data 60 is data for designating a slave. The address data is bit-assigned, and each bit corresponds to one microprocessor. The correspondence between the bit pattern of the address data and the slave microprocessor is shown in (Table 2).

[0030]

[Table 2]

In Table 2, x is "1" or "0".
But it doesn't matter. The address bit of the microprocessor whose address is N (N = 0 to 7) is
It is bit N. Therefore, the master microprocessor can selectively designate the slave device. That is, the master microprocessor may output address data 60 in which the address bit of the microprocessor designated as the slave is true (1) and the address bit of the microprocessor not designated as the slave is false (0). .. For example, the microprocessor 11 is the microprocessor 1
2 and the microprocessor 13 to send a data frame, the address data 60 may be "00001100 (binary display)". At this time, the bit indicating the address of the master itself is set to "0". The microprocessor other than the master detects the first 8-bit data received as the address data after the / BSY signal is asserted, and if the address bit of its own is true (1), it is designated as the slave. Recognize and receive the data frame.

MSB, bit6, bit of control data 61
The 4 bits of 5 and bit 4 indicate “(byte number) −1” of the user data 62. Since the pattern "0000-1111 (binary display)" is possible, the user data 6
The number of bytes of 2 can take any value of 1 to 16. The slave microprocessor uses this value to obtain the number of bytes in the entire data frame, and after receiving the data frame, outputs the reception response data 64 described later. User data 6 with bit 3 of control data 61
Indicates whether the content of 2 is a command or data. When this bit is "0", the user data 62 is data, and when this bit is "1", the user data 62 is a command. Bit 2, bit 1, and LSB of the control data 61 are master addresses, and the address of the master microprocessor is described in the same rule as (Table 1).

The user data 62 is data or commands actually sent from the master to the slave.

The 1-byte error detection code 63 is a byte for error check, and the odd parity for each bit from the first byte (address data 60) of the data frame to the last byte of the user data is recorded. The master performs an exclusive OR operation in byte units from the beginning of the data frame and inverts the result to create the error detection code 63. On the other hand, the microprocessor that has received the data frame performs an exclusive OR operation in byte units from the beginning of the data frame to the check byte, and the result is FFh.
If it is (hexadecimal display), it can be confirmed that it was possible to receive without error.

The master outputs the address data 60, the control data 61, the user data 62, and the error detection code 63, while the reception response data 64 is output by the slave. The reception response data 64 consists of 1 byte. The bits forming the reception response data 64 are each assigned to the reception response bits of one microprocessor.
The reception response bit of the microprocessor whose address is N (N = 0 to 7) is the bit N of the reception response data 64. The slave that has received the data frame detects the presence or absence of a data error using the error detection code 63, and if there is no error, outputs the reception response data 64 in which only its own reception response bit is set to low on the data line 1.

Reception response data 6 of each microprocessor
4 is shown in (Table 3).

[0037]

[Table 3]

In Table 3, "0" indicates high on the data line and "1" indicates low. Since the data line 1 is wired-OR connected, when a plurality of slaves output the reception response data, the result of the logical sum operation is sent to the master.

Next, the distribution of tokens performed prior to the transfer of data frames will be described.

FIG. 5 is a timing chart showing how tokens are distributed by the microprocessor 10. The token 30, token 31, token 32, and token 33 are tokens for the microprocessors 10, 11, 12, and 13, respectively. When none of the microprocessors transfers the data frame, the microprocessor 10 sequentially distributes the tokens to all the microprocessors at the time interval of Tb. For example, when sending a token to the microprocessor 12, the microprocessor 10 outputs the token of “10100000 (binary display)” on the data line 1.

Each microprocessor has the right to become a master and transfer a data frame when it receives a token addressed to itself. When the target transfers the data frame, the data line 1 is transited to low before the controller checks the level of the data line 1 after receiving the token addressed to itself.

In FIG. 5, all targets (microprocessor 11, microprocessor 12, microprocessor 13) keep the data line high,
Moreover, the controller (microprocessor 10) is not transferring the data frame either. Microprocessor 1
As a result of 0, the tokens are sequentially output to each microprocessor. As a result, if none of the microprocessors transfers the data frame, the token output is stopped at that stage. When none of the microprocessors including the controller becomes the master, the tokens are output to the respective microprocessors at regular intervals (Tc).

Next, the operation when the microprocessor, which is the target receiving the token, transfers the data frame will be described with reference to FIGS. 6, 7 and 8.

FIG. 6 is a timing chart when the microprocessor 12 serves as a master and transfers a data frame with the slave microprocessor 11. In FIG. 6, 100 indicates the signal level of the / BSY line 3. Reference numeral 101 denotes a byte clock output by the microprocessor 10. 102,10
3, 104 and 105 are microprocessors 1 respectively
0, microprocessor 11, microprocessor 1
2, the signal output from the microprocessor 13 on the data line is shown. Since the data output of each microprocessor is connected to the data line 1, it is wired-and-on the data line 1 and, as a result, the signal shown at 106 flows on the data line 1. Reference numeral 107 indicates a detection timing at which the microprocessor 10 detects the level of the data line 1. The time indicated by the arrow on 107 is the detection timing. The microprocessor 10 generates a timer interrupt at a time interval Tb, and detects the level of the data line 1 in a timer interrupt processing routine (hereinafter referred to as timer interrupt processing).

FIG. 7 is a schematic flowchart of the timer interrupt processing performed by the microprocessor 10. If the microprocessor 10 is neither a master nor a slave, FIG.
The operation according to the flowchart shown in is performed. At time t2, t4, t6, ..., T14 in FIG.
Is executed.

FIG. 8 is a schematic flowchart of a serial transfer interrupt processing routine (hereinafter referred to as serial interrupt processing) performed by the target. The target generates a serial transfer interrupt (hereinafter referred to as a serial interrupt) when transmitting or receiving 1 byte, and
The operation shown in is performed. Times t1, t3, t5, ...
.. At t15, the target generates a serial interrupt and starts the serial interrupt processing shown in FIG.

First, when the microprocessor 10 outputs the token 31 to the microprocessor 11, the microprocessor 11, the microprocessor 12, and the microprocessor 13 generate a serial interrupt at time t1, and the serial interrupt processing shown in FIG. To start.
After receiving the token, the microprocessor 11 proceeds to step 22.
At 0 / BSY Check line 3 level. / BS
Since the Y line 3 is high, it is detected in step 221 that the token 31, which is the token addressed to itself, is received. However, since there is no data frame to be transferred, step 222 is executed and the serial interrupt processing is terminated.
Similarly, the microprocessor 12 and the microprocessor 13 also detect in step 220 that the level of the / BSY line 3 is high, but since it is not a token addressed to itself, step 221 is executed and the serial interrupt processing ends.

At time t2, the microprocessor 10 detects the level of the data line 1 in step 200. Since data line 1 is high, / BSY line 3 is kept high at step 201 and token 32 is output at step 202.

At time t3, the target generates a serial interrupt. The microprocessor 11 and the microprocessor 13 only execute steps 220 and 221 to end the serial interrupt processing. On the other hand, since the microprocessor 12 receives the token 32,
After executing steps 220 and 221, step 222 is executed. Microprocessor 12 outputs a row on data line 1 in step 223 to transfer the data frame to microprocessor 11. Further, in step 224, the address data 60, which is the first byte of the data frame, is written in the shift buffer to complete the 1-byte transfer preparation. The value of the address data 60 is “00000010 (binary display)”, which indicates that the data frame is transmitted to the microprocessor 11 having the address value of 1.

At time t4, the microprocessor 10 detects that the level of the data line 1 is low (step 200), and makes the / BSY line 3 low at step 204. Then, in step 203, the byte clock is output. With this byte clock, the address data 60 in the shift buffer of the microprocessor 12 is output onto the data line 1.

In the serial interrupt processing started from time t5, the microprocessor 11 and the microprocessor 13 detect that the / BSY line 3 is low (step 220), and since they are not masters (step 225), 227 will be executed. In step 227, since this serial interrupt is the first serial interrupt after the falling edge of / BSY line 3,
It is determined that the data frame received in the shift buffer is the address data 60. The microprocessor 11 recognizes that the address data 60 has been designated as a slave because bit 1 of the address data 60 is 1, and proceeds to step 228.
Since t3 is 0, it is recognized that the slave has not been designated, and the serial interrupt process ends. Step 22
At 8, the microprocessor 11 writes the address data 60 in the receive buffer prepared in the internal RAM area. On the other hand, the microprocessor 12 recognizes that the / BSY line 3 is low in the serial interrupt process started at time t5 (step 220) and executes the step 226 because it is the master itself (step 225). To do. Since the microprocessor 12 has not finished transferring the data frame yet, steps 223 and 22 are executed.
4 is executed to write the control data 61 in the shift buffer. Microprocessor 12 has time t5
The same processing is also performed in the serial interrupt processing at times t7 and t9.

At time t6, the microprocessor 10 detects that the level of the data line 1 is low (step 200), the / BSY line 3 is output low in step 204, and then the byte clock is output in step 203. .. The microprocessor 10 performs the same operation at times t8, t10, and t12.

In the serial interrupt process started at time t7, the microprocessor 11 and the microprocessor 13 go through the same steps as at time t5, and then step 22.
Execute 7. At the previous execution of step 227, the microprocessor 11 recognizes that itself is designated as a slave, and therefore the process proceeds to step 228 and the received data is written in the reception buffer. The microprocessor 11 performs the same processing at time t9. Since the microprocessor 13 recognizes that it has not been designated as a slave at the previous execution of step 227, it terminates the serial reception interrupt without reading the received data. The microprocessor 13 also performs the same processing at times t9, 11, and 13.

Through the above procedure, the microprocessor 1
The error detection code 63 output by 2 is transferred.

In the serial interrupt processing at time t11,
Since the error detection code 63 has already been transmitted, the microprocessor 12 writes "00H (hexadecimal notation)" in the shift buffer in step 224. On the other hand, the microprocessor 11 writes the reception response data 64 in the shift buffer when the data frame can be received without error in step 228. At this point microprocessor 11 is no longer a slave. These data are at time t
It is output onto the data line 1 by the byte clock output from the microprocessor 10 in the timer interrupt processing of 12. Since the shift buffer outputs the data on the data line 1 by the negative logic, the reception response data 64 output by the microprocessor 11 is received by the microprocessor 12 at this byte clock.

In the serial interrupt at time t13, the microprocessor 12 receives the reception response data 6 in step 226.
4 is checked, and since the data frame transfer is completed, the serial interrupt process is completed. On the other hand, since the microprocessor 11 is no longer a slave, it executes step 227 and ends the serial interrupt process. Therefore, the data line 1 is not driven low in the serial interrupt processing at time t13.

When the microprocessor 10 detects that the level of the data line 1 is high at the time t14, it makes the / BSY line 3 high at step 201 and distributes the token again. Last token distribution was token 3
Since it is 2, the token 33, which is the token for the microprocessor 13, is output in step 202.

In the above description, step 223 and step 224 are described as being performed as separate steps, but they can be performed in one step by using a shift buffer capable of serial transfer with a start condition. Hereinafter, a detailed description will be given with reference to FIG.

FIG. 9 is a timing chart of serial transfer with a start condition of a one-chip microprocessor (for example, MN18888: manufactured by Matsushita Electronic Industrial Co., Ltd.). In the case of performing transfer under the condition of an external clock and a start condition. The timing is shown.
When the output of serial data is ready (time t1),
That is, when the data to be transmitted is written in the internal shift register, the data output port shifts from the high impedance state to the low state. When an external clock input is started in this state (time t2), 1-byte data is output from the MSB in order from the data output port.
After the output of the LSB ends (time t3), the data output port shifts to high. Further, when a predetermined period has elapsed, the data output port again shifts to the high impedance state (time t4). The original purpose of the start condition is to synchronize the transfer side and the receiving side in byte units. That is, prior to the transfer of data, the receiving side can reset the clock counter by shifting the data line to low when the clock line is high, and as a result, the transmitting side and the receiving side can be synchronized in byte units. Is. As described above, the start condition is intended to prevent bit shift of transfer due to noise. By using the function of the start condition, the target can drive the data line 1 in a row by only writing the transfer data in the shift buffer. That is,
Steps 223 and 224 of FIG. 8 will be performed simultaneously.

When a microprocessor for performing serial transfer at the timing shown in FIG. 9 is used, since the data output port is a ternary output port, an open collector output is provided between the data output port 17 and the data line 1. Insert the gate.

As described above, according to the present embodiment, the controller detects the level of the data line at the predetermined detection timing, and if the data line is at the high level at the detection timing, the control line is set until the next detection timing. If the data line is at the low level at the detection timing while maintaining the false level and the token is transmitted, the control line is maintained at the true level until the next detection timing and the transfer clock for one transfer unit is output to the clock line. Then
On the other hand, when the target receives the token addressed to itself and starts the transfer of the data frame, it waits until the next detection timing until the transfer of each data forming the data frame is completed. To a low level, and by transferring the data frame using the data line in synchronization with the transfer clock output by the controller, the controller prepares the output port and the target prepares the input port for the / BSY line. Just do it. In addition, the / BSY signal is manipulated immediately before the byte clock is output, so a serial interrupt
Even if the BSY line is monitored, erroneous recognition of the / BSY signal does not occur.

Next, a second embodiment of the present invention will be described with reference to the drawings. In the present embodiment, unlike the first embodiment, the microprocessor 11, the microprocessor 12, and the microprocessor 13 monitor the / BSY line 3 with the external interrupt input port. Since the format of the token and frame and the token distribution procedure are the same as those in the first embodiment, the description thereof will be omitted, and the operation when the microprocessor which is the target receiving the token transfers the data frame will be described with reference to FIG. 11, 12, and 1
3 will be used for explanation.

FIG. 10 is a timing chart when the microprocessor 12 serves as a master and transfers a data frame with the microprocessor 11 which is a slave. In FIG. 10, 100, 101, 102, 10
3, 104, 105, 106 and 107 are the same as those in FIG. Reference numerals 113, 114, and 115 respectively show states of interrupt processing performed by the microprocessor 11, the microprocessor 12, and the microprocessor 13 in time series. The interrupt process indicated by Ex is an external interrupt process activated at the rising or falling of the / BSY line 3. Further, the interrupt process indicated by Sr is a serial interrupt process.

FIG. 11 is a schematic flowchart of the timer interrupt processing performed by the microprocessor 10. When the microprocessor 10 is neither a master nor a slave, it operates according to the flowchart shown in FIG. Figure 10
At time t2, t4, t6, ..., t16, step 2
00 is executed.

FIG. 12 is a schematic flowchart of the serial interrupt processing performed by the target. In the serial interrupt processing, the processing executed differs depending on the interrupt mode. There are four interrupt modes: "wait for token", "master", "address detection", and "slave".
In "wait for token", it is determined whether the received token is addressed to itself. The "master" transfers the data frame as the master. In "address detection", it is determined whether or not the slave itself has been designated. The "slave" performs a data frame transfer process as a slave. When interrupt mode is "waiting for token" / BSY
Line 3 is high, but low in all other interrupt modes.

FIG. 13 is a schematic flowchart of the external interrupt processing performed by the target. Target is / BSY
An external interrupt is generated at the rise of line 3 or at the rise, and the processing shown in FIG. 13 is executed.

In the initial state, it is assumed that the microprocessors in which the data frame transfer request is issued are the microprocessor 12 and the microprocessor 13. Therefore,
The microprocessor 12 and the microprocessor 13 are in interrupt mode = “wait for token” and serial interrupts are permitted. Further, the microprocessor 11, the microprocessor 12, and the microprocessor 13 are / BS.
Falling interrupt on Y line 3 is enabled.

In this state, the microprocessor 10 outputs the token 31 to the microprocessor 11. Since the microprocessor 11 has not issued a data frame transfer request, no serial interrupt occurs. Microprocessor 12 performs serial interrupt processing 1
At 30 the process shown in FIG. 12 is performed. First, step 25
At 9, the current interrupt mode is determined. Since the interrupt mode = “waiting for token”, it is determined in step 221 whether or not the received token is addressed to itself. However, since the token 31 is addressed to the microprocessor 11, the serial interrupt processing ends. The microprocessor 13 also performs the same process as the serial interrupt process 130 in the serial interrupt process 140.

At time t2, the microprocessor 10 detects the level of the data line 1 in step 200. Since data line 1 is high, step 251 determines if it is outputting a high on / BSY line 3. At time t2, high is being output, so step 2
In 02, the token 32 is output.

At time t3, the microprocessor 12 and the microprocessor 13 generate a serial interrupt.
The microprocessor 13 uses the serial interrupt processing 141
Then, the same processing as the serial interrupt processing 140 is performed. The microprocessor 12 executes the serial interrupt processing 131. Since the microprocessor 12 has received the token 32, it executes steps 259 and 221 and then step 250 to set the interrupt mode to “master”.
Change to. In step 258, at time t5 / BSY
The external interrupt is prohibited in order to prevent the external interrupt from being generated by the fall of the line 3. Further, steps 223 and 224 are executed in the same manner as in the first embodiment.

At time t4, the microprocessor 10 detects that the level of the data line 1 is low (step 200), and determines at step 250 whether or not it is outputting a low to the / BSY line 3. Since high is being output at time t4, low is output to the / BSY line 3 in step 204 (time t5).

At time t5, the microprocessor 11 and the microprocessor 13 generate an external interrupt due to the fall of the / BSY line 3. External interrupt processing 12
At 0, first, the interrupt factor of the external interrupt is checked in step 274 of FIG. Since the falling interrupt has occurred at time t5, the interrupt mode is set to “address detection” in step 272. Further, in step 273, the serial interrupt is enabled. The microprocessor 13 executes the same processing as the interrupt processing 142.

At time t6, the microprocessor 10 detects that the level of the data line 1 is low (step 200), and determines at step 250 whether or not it is outputting a low to the / BSY line 3. Since the row is being output at the time t4, the byte clock is output to the clock line 2 in step 203. The address data 60 written in the shift buffer by the microprocessor 12 in the serial interrupt processing 131 is output onto the data line 1 by this byte clock. The microprocessor 10 performs the same processing as at time t6 at times t8, t10, t1.
Repeat 2

At time t7, the microprocessor 11 and the microprocessor 12 respectively execute serial interrupt processing 1
21 and the serial interrupt processing 143 is started.
Both microprocessors have an interrupt mode of "address detect", so in step 252 it is determined whether they have been designated as slaves. The microprocessor 11 recognizes that the address data 60 is designated as a slave because bit 1 of the address data 60 is 1, and proceeds to step 253.
Since bit3 is 0, it is recognized that the slave has not been designated, and the process proceeds to step 251. At step 253, the microprocessor 11 sets the interrupt mode to “slave”.
Change to. Further, in step 228, the address data 60 is written in the receive buffer prepared in the internal RAM area as in the first embodiment. Then step 25
In step 4, it is determined whether or not the reception is completed. However, since the reception of the data frame is not completed yet, the serial interrupt processing 121 is ended as it is. The microprocessor 11 repeats the same processing until the error detection code 63 is received.
On the other hand, the microprocessor 13 not designated as the slave determines in step 251 whether or not there is a transfer waiting frame. Since the frame transfer request has been generated, the microprocessor 13 sets in step 256 that an external interrupt is generated at the rising edge of the / BSY line 3, and then in step 257, disables the serial interrupt and executes the serial interrupt processing 143. finish.
Therefore, the microprocessor 13 does not generate the serial interrupt until the serial interrupt is permitted by the external interrupt processing. On the other hand, the microprocessor 12 recognizes that the interrupt mode is "master" in the serial interrupt processing 132 started at time t7 (step 25).
9), execute step 226. Since the microprocessor 12 has not yet completed the transfer of the data frame, it executes steps 223 and 224 and writes the control data 61, which is the second byte of the data frame, in the shift buffer. The microprocessor 12 performs the same process as the serial interrupt process 132 until the error detection code 63 is written in the shift buffer.

Serial interrupt processing 134 at time t11
Then, since the error detection code 63 has already been transmitted,
The microprocessor 12 sends "00H" at step 224.
(Hexadecimal notation) "is written in the shift buffer. on the other hand,
The microprocessor 11 uses the serial interrupt processing 123.
In step 228, if the data frame can be received without error, the reception response data 64 is written in the shift buffer. At this point, the microprocessor 11 finishes the reception process, and therefore the process proceeds to step 251 to check the existence of the transfer wait frame. Since there is no transfer waiting frame, the microprocessor 11 proceeds to step 255 and permits the falling interrupt so that an external interrupt is generated at the falling of the / BSY line 3. Further, in step 257, the serial interrupt is prohibited and the serial interrupt processing 123 is ended. Therefore, the microprocessor 11 will ignore the bus until another microprocessor changes the / BSY line 3 from high to low. Of course, if a data frame transfer request is generated when the / BSY line 3 is high, the microprocessor 11 may set the interrupt mode to "wait for token" and allow the serial interrupt.

The reception response data 64 written in the shift buffer by the serial interrupt processing 123 is sent to the microprocessor 12 by the byte clock output by the microprocessor 10 in the timer interrupt processing at time t12, as in the first embodiment. Sent.

Only at the microprocessor 12 is the serial interrupt generated at time t13. In the serial interrupt processing 135, the microprocessor 12 checks the reception response data 64 in step 226, and since the data frame transfer is completed, the process proceeds to step 251. Since no new data frame transfer request has been issued to the microprocessor 12, steps 251, 255,
257 is executed. As a result, similarly to the microprocessor 11, the serial interrupt processing 135 is terminated with the falling interrupt enabled and the serial interrupt disabled. At this point, the data frame has been transferred, so
Data line 1 remains held high.

At time t14, the microprocessor 10 detects that the level of the data line 1 is high (step 200), and determines at step 251 whether or not it is outputting a high level to the / BSY line 3. Time t14
Since low is being output, in step 201 / BS
High is output to the Y line 3 (time t15).

At time t15, the external interrupt caused by the rising edge of the / BSY line 3 is the microprocessor 13
Occurs in. In this external interrupt processing 144, processing is performed according to the flowchart shown in FIG. First,
In step 274, the interrupt factor of the external interrupt is checked. Since the rising interrupt has occurred at time t15, the interrupt mode is set to "wait for token" in step 271. Further, in step 273, the serial interrupt is enabled.

The microprocessor 10 performs the same processing as at time t2 by the timer interrupt processing at time t16, and outputs the token 33 at step 202.

Upon receipt of the token 33 addressed to itself in the serial interrupt processing 145 at time t17, the microprocessor 13 performs the same processing as that executed by the microprocessor 12 in the serial interrupt processing 131, and the data line 1
Drive low.

Also in the second embodiment described above, similarly to the first embodiment, if a shift buffer capable of serial transfer with a start condition is used, steps 223 and 224 can be executed in one step.

In the target serial interrupt process shown in FIG. 12, the process of inhibiting the serial interrupt is performed in step 257 in order to make the explanation easy to understand. However, when an interrupt occurs in a general one-chip microprocessor, the interrupt is not generated next time unless the interrupt is permitted in the interrupt process. Therefore, in actual programming, instead of step 257, a step of enabling a serial interrupt is required when the interrupt processing ends without executing step 257.

As described above, according to the present embodiment, the controller detects the level of the data line at the predetermined detection timing, and the data line is at the high level and the true level is output to the control line at the detection timing. When it is in the middle, it starts outputting the false level to the control line, and when the data line is high level and the false level is being output to the control line at the detection timing, the token is transmitted and detected. When the data line is low level and the false level is being output to the control line at the timing, the output of the true level to the control line is started,
When the data line is low level at the detection timing and the true level is being output to the control line, the transfer clock for one transfer unit is output to the clock line, while the target is the token addressed to itself. When receiving the data and starting the transfer of the data frame, until the transfer of each data forming the data frame is completed,
By shifting the data line to the low level by the next detection timing and transferring the data frame using the data line in synchronization with the transfer clock output from the controller, the controller outputs the / BSY line to the output port. The target only needs to prepare an input port. Further, since the operation of the / BSY signal and the transmission of the byte clock and the token are performed completely independently, even if the / BSY line is monitored by the serial interrupt, the / BSY signal is not erroneously recognized.

Further, the target monitors the control line at the external interrupt input port, prohibits the serial interrupt when the data frame transfer request is not generated, and when the control line is at the false level, the control is performed. By permitting the serial interrupt in the line falling interrupt process, the serial interrupt process for token reception can be prohibited when the data frame transfer request is not generated.

Further, the target can reduce the number of serial interrupt processing when the control line is at a low level by prohibiting the serial interrupt when the data frame is being transferred between the microprocessors other than itself. it can.

When a data frame transfer request is generated while data frames are being transferred between microprocessors other than itself, the target transfers data by enabling a serial interrupt at the rising edge of the control line. It is possible to minimize the number of serial interrupts from request generation to token acquisition.

Although a general-purpose microprocessor is used as a device in the above two embodiments, the device connected to the bus is not limited to the microprocessor. For example, it is possible to connect an LSI such as a DSP.

In the above two embodiments, the master transmitted the data frame and the slave received it. However, the master instructs the slave to output the data frame, and the slave outputs the data frame. May be. In this case, the format of the data frame may be changed by changing the format number of the token.

[0090]

As described above, according to the invention, the controller detects the level of the data line at a predetermined detection timing, and if the data line is at the high level at the detection timing, the control line is false until the next detection timing. If the data line is low level at the detection timing while keeping the level, and the data line is at the low level at the detection timing, the control line is kept at the true level until the next detection timing and the transfer clock for one transfer unit is output to the clock line, On the other hand, when the target receives the token addressed to itself and starts the transfer of the data frame, it waits until the next detection timing until the transfer of each data forming the data frame is completed. To the low level and the data line is synchronized with the transfer clock output from the controller. By performing the transfer of data frames using a / controller for BSY line target output port effect that it is only necessary to provide an input port is obtained. Further, since the operation of the / BSY signal is performed immediately before the output of the byte clock, it is possible to obtain the effect that the erroneous recognition of the / BSY signal does not occur even if the / BSY line is monitored by the serial interrupt.

When the data line is at the high level at the detection timing and the true level is being output to the control line, the controller starts outputting the false level to the control line, and at the detection timing, the data line is output. Is high level and is outputting a false level to the control line, a token is transmitted, and when the data line is low level and a false level is being output to the control line at the detection timing, When the output of the true level to the control line is started and the data line is at the low level at the detection timing and the true level is being output to the control line, the transfer clock for one transfer unit is supplied to the clock line. By outputting, the controller only needs to prepare an output port and the target an input port for the / BSY line. Effect can be obtained. Further, since the operation of the / BSY signal and the transmission of the byte clock and the token are performed completely independently, even if the / BSY line is monitored by the serial interrupt, there is an advantage that the erroneous recognition of the / BSY signal does not occur.

Further, the target monitors the control line at the external interrupt input port, disables the serial interrupt when the data frame transfer request is not generated, and when the control line is at the false level, the control is performed. By permitting the serial interrupt in the line falling interrupt process, it is possible to inhibit the serial interrupt process for token reception when the data frame transfer request is not generated.

Furthermore, the target can reduce the number of serial interrupt processes when the control line is at a low level by disabling the serial interrupt when the data frame is being transferred between the microprocessors other than itself. The effect that can be obtained is obtained.

Further, when a data frame transfer request is generated while data frames are being transferred between microprocessors other than itself, the target transfers by permitting a serial interrupt at the rising edge of the control line. This has the effect of minimizing the number of serial interrupts from request generation to token acquisition.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a system for performing data transfer using a data transfer method according to a first embodiment and a second embodiment of the present invention.

FIG. 2 is a timing chart showing a relationship between signals on a data line 1 and a clock line 2 in the first and second embodiments.

FIG. 3 is a schematic diagram showing a format of a token in the first and second embodiments.

FIG. 4 is a schematic diagram showing a format of a data frame in the first and second embodiments.

FIG. 5 is a timing chart showing how tokens are distributed by the microprocessor 10 in the first and second embodiments.

FIG. 6 is a microprocessor 1 according to the first embodiment.
2 is a master and is a timing chart when transferring a data frame with the microprocessor 11 which is a slave

FIG. 7 is a schematic flowchart of timer interrupt processing executed by the controller according to the first embodiment.

FIG. 8 is a schematic flowchart of serial interrupt processing executed by the target in the first embodiment.

FIG. 9 is a timing chart of serial transfer with a start condition of the microprocessor according to the first embodiment.

FIG. 10 is a timing chart when the microprocessor 12 serves as a master and transfers a data frame to and from the slave microprocessor 11 in the second embodiment.

FIG. 11 is a schematic flowchart of timer interrupt processing executed by a controller according to the second embodiment.

FIG. 12 is a schematic flowchart of serial interrupt processing executed by a target according to the second embodiment.

FIG. 13 is a schematic flowchart of an external interrupt process executed by a target according to the second embodiment.

[Explanation of symbols]

 1 data line 2 clock line 3 / BSY line 10, 11, 12, 13, microprocessor 14 / BSY signal input port 15 clock input port 16 data input port 17 data output port 18 clock output port 19 / BSY signal output port 60 address Data 61 Control data 62 User data 63 Error detection code 64 Received response data

Claims (8)

[Claims] 1. A device that is a controller and a device that is a controller.
A data transfer method for transferring a data frame between a plurality of devices including one or more target devices, wherein each device is bidirectional in which serial data of one transfer unit is intermittently transferred between the devices. Data line, a clock line that supplies the serial data transfer clock from the controller to the target, and the controller that indicates to the target that the master device is transferring the data frame. Connected to each other by three signal lines, the controller detects the level of the data line at a predetermined detection timing when the controller itself is not the master, and the controller detects that the data line is high at the detection timing. If at least the next detected timing 1 device using the data line and the clock line with up to keep the control line to the level of sham
When the data line is at the low level at the detection timing, the control line is kept at the true level and the clock line is transferred for one transfer unit at least until the next detection timing. Outputting a clock, and if the target receives serial data through the data line and the clock line when the control line is at a false level, the target determines that the received serial data is a token and receives it. When the token is addressed to self-confidence, and when the master becomes the master and starts the transfer of the data frame, the next detection timing until the transfer of each data forming the data frame is completed. The data line to the low level and the transfer clock output from the controller. A data transfer method characterized in that a data frame is transferred using the data line in synchronization with the clock. 2. A device that is one controller and one device.
A data transfer method for transferring a data frame between a plurality of devices including one or more target devices, wherein each device is bidirectional in which serial data of one transfer unit is intermittently transferred between the devices. Data line, a clock line that supplies the serial data transfer clock from the controller to the target, and the controller that indicates to the target that the master device is transferring the data frame. Connected to each other by three signal lines, the controller detects the level of the data line at a predetermined detection timing when the controller itself is not the master, and the controller detects that the data line is high at the detection timing. At the same time as the If a false level is being output to the control line, the output of the false level to the control line is started, and at the detection timing, the data line is at a high level and itself is outputting a false level to the control line. In some cases, the clock line and the data line are used to send a token to one of the devices, and the data line is at a low level at the detection timing and itself is outputting a false level to the control line. In the case where the output of the true level to the control line is started, the data line is at the low level at the detection timing and the device itself is outputting the true level to the control line, the clock line The transfer clock for one transfer unit is output to the target, and the target is connected to the data line and the clock when the control line is at a false level. When serial data is received via the line, the received serial data is determined to be a token, the received token is addressed to itself, and the master becomes the master to start the data frame transfer. In addition, until the transfer of each data forming the data frame is completed, the data line is transited to the low level by the next detection timing, and in synchronization with the transfer clock output from the controller. A data transfer method, wherein a data frame is transferred using the data line. 3. A device is assigned a unique device address, the token includes an address identifier for identifying the device address, and the target identifies the address identifier included in the received token. The data transfer method according to claim 1 or 2, wherein it is determined whether or not the received token is addressed to itself. 4. A data frame is transferred between a master and one or more slaves, which are devices designated by the master as a transfer partner, and the master identifies the slave at the beginning of the data frame. The device outputs data, and the device other than the master recognizes the serial data first received as the identification data after the control line transits from the false level to the true level, and uses the identification data to identify itself as a slave. 3. The data transfer method according to claim 1, wherein it is determined whether or not it is designated. 5. The target detects the level of at least a control line in a serial transfer interrupt processing routine that is activated each time one transfer unit of serial data is received or transmitted.
Data transfer method described in. 6. The target monitors at least an external interrupt input port for a control line, and executes a serial transfer interrupt processing routine that is activated each time serial data of one transfer unit is received or transmitted. When a transfer process is performed and a data frame transfer request is not generated, and the control line is at a false level, the serial transfer interrupt is prohibited, and when the control line transitions to the true level, the external 3. An interrupt is generated and a serial transfer interrupt is enabled by an external interrupt processing routine.
Data transfer method described in. 7. The data transfer method according to claim 6, wherein the target prohibits a serial transfer interrupt when a data frame is being transferred between devices other than itself. 8. The target generates an external interrupt when the control line transitions to a false level when a data frame transfer request occurs while data frames are being transferred between devices other than itself. 8. The data transfer method according to claim 7, wherein the serial transfer interrupt is enabled by the external interrupt processing.