JPH05197678A - Device and method for data transfer - Google Patents

Abstract

PURPOSE:To provide the data transfer device capable of normal data transfer even though the operation of signal lines related to the hand shaking is performed during clock input and output. CONSTITUTION:At the time of data transfer, a chip select signal is outputted to a reception microcomputer through a D latch 305 of a terminal control means 30 by receiving a chip select instruction. Based on the clock from a clock supply means 111, the data of a transmission buffer 107 is serially transferred through a data line 103. During the transmission, the output of an instruction is not sent to the reception microcomputer 102 even though the instruction stopping the chip selection comes and the chip selection is stopped at the end of a unit of data transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a microprocessor,
In a device such as an LSI, when attempting to manipulate the output state of a terminal during serial data transfer, it is possible to wait until the end of serial data transfer and then manipulate the actual output state of the terminal. And a data transfer device.

[0002]

2. Description of the Related Art Data transfer methods are roughly classified into parallel transfer using a parallel data bus and serial transfer using a serial data bus. Although parallel transfer is suitable for high-speed data transfer, it leads to an increase in the number of pins of microprocessors, ICs and the like. One-chip microprocessor used in audio-video equipment and home appliances (hereinafter,
Microcomputer is called) because serial transfer is sufficient in terms of transfer speed, so serial transfer is used which leads to a reduction in the number of pins. 2. Description of the Related Art In recent years, a plurality of microcomputers have been built in one product like a video tape recorder and a camera-integrated video as the functions of devices have become higher. These microcomputers do not operate independently, but operate while performing data transfer with each other using a serial data bus. Further, not only a microcomputer but also various ICs and LSIs can be connected to this serial data bus.

The operation of the above-mentioned inter-microcomputer communication will be described below by taking a microcomputer as an example of a conventional data transfer device. FIG. 5 is a block diagram of the above-described conventional data transfer device using a microcomputer and a system for performing serial data communication. In FIG. 5, the transmitting side microcomputer 101 and the receiving side microcomputer 102 are an example of the above-mentioned conventional data transfer device. These data transfer devices are connected by a data line 103, a clock line 104, and a chip select line 105 which is one type of control line. The data line 103 and the clock line 104 constitute a serial bus 106, and other microcomputers (not shown) are also connected. The transmission buffer means 107 receives the data output instruction 114 and fetches parallel data of one transfer unit (one transfer unit is defined as 8 bits in this example) from the data bus 110 inside. The transmission buffer means 107 is a clock supply means 111.
The clock supplied from the CPU is input, the data of one transfer unit, which is taken in internally, is serially output to the data output terminal 112, and the output completion notification 135 is output to an internal central processing unit (CPU) not shown. When the data output instruction 114 is input, the clock supply means 111 outputs a unit clock for one transfer unit to the transmission buffer means 107 and the clock output terminal 128. The terminal output means 116 is, for example, an RSFF to which the chip select command 118 and the chip select stop command 119 are input, and outputs the terminal control signal 120 to the chip select signal output terminal 129.

On the other hand, the receiving side microcomputer 102 is provided with a receiving buffer means 122. In the reception buffer means 122, the chip select signal is input to the chip select signal input terminal 13
When input from 0, the serial data from the data input terminal 132 is taken in based on the clock input from the clock input terminal, and the data for one transfer unit is written to the data bus 134.

The operation of the data transfer device configured as described above will be described. FIG. 6 shows a timing chart of inter-microcomputer communication in FIG. Transmission side microcomputer 101
In order to transfer serial data to the receiving side microcomputer 102, first, the right to use the serial bus 106 is acquired by some arbitration means (not shown). Next, the chip select instruction 118 is output to the terminal output means 116 (time t ₁ ). Receiving this chip select command, the terminal output means 116 outputs the output 120 as a chip select signal and outputs the L level from the output terminal 129 (time t ₁ ).
On the other hand, when the L level signal is input from the chip select signal input terminal 130, the reception buffer means 122 becomes ready to receive serial data from the serial bus 106.

Next, the CPU in the transmitting side microcomputer 101 outputs a data output command 114. Data output instruction 114
The transmission buffer means 107 which has received the data bus 110
It takes in one transfer unit of data from and stores it internally.
The clock supply means 111 receives the data output instruction 114 and outputs the unit clock 202 for one transfer unit to the transmission buffer means 107 and the clock output terminal 128 as shown in FIG. 6B. Then, the transmission buffer means 107 synchronizes the data 201 for one transfer unit stored therein in synchronization with the unit clock 202, as shown at times t _{2 to} t ₃ in FIGS. 6A and 6B. Output to the output terminal 112. When the transmission buffer means 107 finishes outputting the unit data 201 for one transfer unit, it outputs an output completion notice 135 at time t ₃ .

On the other hand, the receiving buffer means 122 of the receiving side microcomputer 102 synchronizes with the unit clock 202 input from the clock input terminal 131, and the data input terminal 132.
The unit data 201 is input. Output completion notification 135
The CPU (not shown) of the transmitting side microcomputer 101 which has received the
If there is data to be transmitted to the receiving-side microcomputer 102, the data is continuously output similarly. If there is no more data to be transmitted, the chip select stop command 119 is output to the terminal output means 116 as shown in FIG. 6 (e) (time t ₄ ). The terminal output means 116 that has received the chip select stop instruction 119 is shown in FIG.
As shown in (f), the chip select signal output terminal 129
To H level. Chip select signal input terminal 130
After that, the receiving buffer means 122 which has input the H level to the I level ignores the serial bus 106 until the L level is input again from the chip select input terminal 130. As described above, the receiving side microcomputer 102 is the transmitting side microcomputer 1
Serial bus 10 except when receiving data from 01
The data can be received without being interfered by 6.

[0008]

However, in the above-mentioned conventional data transfer device, the CP of the transmitting side microcomputer 101 is used.
The timing at which the U outputs the chip select stop command is not free. That is, consider a case where the chip select stop command is issued between the issuance of the data output command and the end of the data output of one transfer unit. In this case, the reception buffer means stops the input from the serial bus while receiving the data of one transfer unit, and normal reception cannot be performed. That is, there is a problem that the control line operation necessary for the handshake in the data transfer cannot be performed during the clock input / output. Therefore, there is a drawback that the load of the CPU inside the data transfer device becomes large.

The present invention solves the above conventional problems. That is, it is an object of the present invention to realize a data transfer device capable of performing normal data transfer even if a signal line related to handshake is operated during serial input / output.

[0010]

According to a first aspect of the present invention, data is intermittently serially transferred in units of one transfer unit between a plurality of data transfer devices connected by a data line, a clock line and a control line. In the transfer method, a data transfer device for transmitting data outputs one transfer unit of data to a data line in synchronization with a clock of one transfer unit supplied from a clock line or an internal clock generating means, and performs one transfer. If you try to change the output state of the output terminal of the control line while outputting the data of the unit, change the output state of the output terminal after the output of the data of one transfer unit is finished, The data transfer device for receiving one transfer is synchronized with the clock of one transfer unit supplied from the clock line or the internal clock generating means. It is characterized in that is used to input position data.

According to a second aspect of the present invention, there is provided a data transfer device for intermittently serially transferring data for each transfer unit between a plurality of data transfer devices connected by a data line, a clock line and a control line, Transmission buffer means for holding data to be transferred and serially outputting data of one transfer unit in synchronization with a clock supplied for one transfer unit; and clock for supplying a clock of one transfer unit to the transmission buffer means during data transfer Supply means,
A clock start detecting means for detecting the start of the clock input to the transmission buffer means and outputting a terminal operation prohibition instruction, and a terminal operation for detecting the completion of the input of the clock of one transfer unit to the transmission buffer means. Between the clock completion detecting means for outputting the enabling command and the terminal control signal of the control line, and from the input of the terminal operation enabling instruction from the clock completion detecting means to the input of the terminal operation prohibiting instruction from the clock start detecting means. Outputs the terminal control signal and outputs the terminal control signal immediately before the terminal operation prohibition instruction is input until the terminal operation permission instruction is input after the terminal operation prohibition instruction is input. When it changes, the terminal control means for controlling the output terminal of the control line by changing the output state after the terminal operation permission command is input. It is characterized in that it comprises a.

The invention according to claim 3 of the present application is a data transfer device for intermittently serially transferring data by one transfer unit between a plurality of data transfer devices connected by a data line, a clock line and a control line, Transmission buffer means for holding data to be transferred and serially outputting data of one transfer unit in synchronization with a clock supplied for one transfer unit; and clock for supplying a clock of one transfer unit to the transmission buffer means during data transfer Supply means,
A clock start detecting means for detecting the start of the clock input to the transmission buffer means and outputting a terminal operation prohibition instruction, and a terminal operation for detecting the completion of the input of the clock of one transfer unit to the transmission buffer means. Between the clock completion detecting means for outputting the enabling command and the terminal control signal of the control line, and from the input of the terminal operation enabling instruction from the clock completion detecting means to the input of the terminal operation prohibiting instruction from the clock start detecting means. Outputs the terminal control signal and outputs the terminal control signal immediately before the terminal operation prohibition instruction is input until the terminal operation permission instruction is input after the terminal operation prohibition instruction is input. When it changes, the terminal control means for controlling the output terminal of the control line by changing the output state after the terminal operation permission command is input. It is input terminal function signal, and characterized by comprising a selection means for outputting the output of the terminal control signal or terminal control means switching the output terminals in accordance with the terminal function signal.

According to a fourth aspect of the present invention, there is provided a data transfer device for intermittently serially transferring data for each transfer unit between a plurality of data transfer devices connected by a data line, a clock line and a control line, Transmission buffer means for holding data to be transferred and serially outputting data of one transfer unit in synchronization with a clock supplied for one transfer unit; and clock for supplying a clock of one transfer unit to the transmission buffer means during data transfer Supply means,
A clock start detecting means for detecting the start of the clock input to the transmission buffer means and outputting a terminal operation prohibition instruction, and a terminal operation for detecting the completion of the input of the clock of one transfer unit to the transmission buffer means. Between the clock completion detecting means for outputting the enabling command and the terminal control signal of the control line, and from the input of the terminal operation enabling instruction from the clock completion detecting means to the input of the terminal operation prohibiting instruction from the clock start detecting means. Outputs the terminal control signal and outputs the terminal control signal immediately before the terminal operation prohibition instruction is input until the terminal operation permission instruction is input after the terminal operation prohibition instruction is input. When it changes, the terminal control means for controlling the output terminal of the control line by changing the output state after the terminal operation permission command is input. It is characterized in that it comprises the terminal control signals, and the reading reading means the output state of the terminal control means.

[0014]

The present invention is realized by the procedure described below with the above configuration. When serial transmission / reception is started in the data transfer device of the present invention, the terminal control means maintains the output state of the terminal control signal immediately before the start of serial transmission / reception. If an attempt is made to manipulate the output state of the terminal during serial transmission / reception, the terminal control means maintains the output state of the terminal, so that the output state of the terminal does not change at that time.
In this case, the terminal control means changes the actual output state of the terminal only after the serial transmission / reception is completed. Further, in the invention of claim 3 of the present application, the selecting means selectively outputs the terminal control signal directly or through the output obtained through the terminal controlling means to the output terminal. Furthermore, in the invention of claim 4 of the application, a reading means for switching and reading the terminal control signal and the output of the terminal control means is provided.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a transmitting side microcomputer and a communication processing unit of a serial bus in a first embodiment of the present invention. Since the transmitting side microcomputer and serial bus of this embodiment shown in FIG. 1 have basically the same configuration as the conventional transmitting side microcomputer and serial bus shown in FIG. 5,
The same numbers are given to the same components and detailed explanations are omitted. The receiving-side microcomputer 102 is the same as the conventional example shown in FIG. In this embodiment, one transfer unit is defined as 8 bits.

In FIG. 1, the transmitting side microcomputer 300 is an example of a data transfer device, and the chip select signal output terminal 129 is an example of an output terminal. The transmission buffer means 107 is an example of the buffer means. The output of the clock supply means 111 is, in addition to the transmission buffer means 107, clock start detection means 301, clock completion detection means 30.
Also given to 2. The clock start detection means 301 is composed of, for example, a fall detector, detects a start point of a clock signal having a constant time width, and its output is given to the terminal control means 303. The clock completion detecting means 302 comprises, for example, a counter that counts the number of clocks in one transfer unit, counts a fixed number of clocks, and gives a detection signal to the terminal control means 303 when the counting is completed.
The terminal control means 303 is a terminal operation permission signal output means 304.
And a D-type flip-flop 305.
The terminal operation permission signal output means 304 comprises, for example, an RS flip-flop set by a clock start signal and reset by a clock completion signal, and its output is given to the control terminal G of the D-type flip-flop. D
The output of the terminal output means 116 is applied to the D input terminal of the flip-flop as in the above-mentioned conventional example, and the Q output thereof is applied to the chip select signal output terminal 129.

The operation of the data transfer apparatus of the present embodiment constructed as above will be described. FIG. 2 is a timing chart in this embodiment. When a request for transmitting serial data is issued to the transmitting-side microcomputer 300, the right to use the serial bus 106 is first acquired by some arbitration means (not shown). Next, the CPU (not shown) of the transmitting side microcomputer 300 outputs a chip select command 118 at time t _{1 as} shown in FIG. This chip select instruction 118 causes the terminal output means 116 to output the L level to the D latch 305 as shown in FIG.
t ₁ ). Since serial transfer is not performed at this point, the terminal operation permission signal output means 304 shown in FIG.
Is at the H level. Therefore, as shown in FIG. 2G, the chip select signal 306, which is the output of the D latch 305, transits to the L level at time t ₁ .

Next, the CPU of the transmitting side microcomputer 300 outputs the data output command 114 to write the data of one transfer unit in the transmitting buffer means 107. Upon receiving the data output command 114, the clock supply means 111 immediately starts supplying the unit clock 202 for one transfer unit. When the supply of the unit clock 202 from the clock supply unit 111 is started, the transmission buffer unit 107 starts the unit clock 202 as shown at times t _{2 to} t ₄ in FIGS. 2A and 2B.
The unit data 201 is output to the data output terminal 112 in synchronization with. The clock start detection means 301 monitors the falling edge of the output of the clock supply means 111, detects that the supply of the unit clock 202 is started at time t _{2 at} which this falling edge is detected, and immediately operates the terminals. The prohibition command 307 is output. Terminal operation prohibition command 30
The terminal operation permission signal output means 304 having received 7 immediately outputs the L level to the D latch 305. D
Upon receiving this signal, the latch 305 maintains the chip select signal 306 at L level irrespective of the state of the terminal control signal 120 of the terminal output means 116 until the terminal operation permission signal transits to H level. Here, the chip select signal 306 is maintained at the L level because the terminal control signal 120 was at the L level as shown in FIG. 2E immediately before the terminal operation permission signal transited to the L level.

At time t ₃ , that is, the unit data 201
The CPU of the transmitting side microcomputer 300 receives the chip select stop command 119 from the start to the end of the output of
Consider the case where is output. At time t ₃ , the terminal control signal 120 transits to H level, but the terminal operation permission signal is L level.
Since it is at the level, at this point the chip select signal 30
6 does not change. The clock completion detecting means 302 counts clocks by an internal counter (not shown). When the clocks for one transfer unit are counted,
The internal counter is cleared and the terminal operation permission instruction 308 is output. In this case, when the output of the unit data 201 ends at time t ₄ , the clock completion detecting means 3
02 detects this and outputs a terminal operation permission command 308. Upon receiving the terminal operation permission command 308, the terminal operation permission signal output means 304 immediately sets the terminal operation permission signal to the H level as shown in FIG. Since the terminal operation signal 120 is at the H level at time t ₄ , when the terminal operation permission signal becomes the H level, the chip select signal 306 is output.
Shifts to the H level.

As described above, according to the present embodiment, when the chip select signal is changed during serial data transfer, the actual output state of the chip select signal output terminal is changed to end the serial data transfer. By providing the terminal control means 303 which delays until later, it is possible to realize a data transfer device with less burden on the CPU.
That is, when outputting the chip select stop command after starting the data transfer, it is possible to realize a data transfer device that can normally transfer data even if the chip select stop command is output without waiting for the end of the data transfer. ..

Next, a second embodiment embodying the invention of claim 2 of the present application will be described with reference to the drawings. Figure 3
FIG. 7 is a block diagram of a transmission side microcomputer and a communication processing unit of a serial bus in the second embodiment. The transmitting side microcomputer, the serial bus and the receiving side microcomputer (not shown) of this embodiment shown in FIG. 3 are basically the same as the transmitting side microcomputer, the serial bus and the receiving side microcomputer of the first embodiment shown in FIG. Since they have the same configuration, the same components are designated by the same reference numerals and detailed description thereof will be omitted. In FIG. 3, the transmission side microcomputer 400 is an example of a data transfer device, and the chip select signal output terminal 129 is an example of an output terminal. In this embodiment, the outputs of the terminal output means 116 and the terminal control means 303 are given to the selection switch 402 of the selection means 401. The selection means 401 includes a switch control means 40.
3 are connected. The switch control means 403 selectively switches this switch on the basis of a function selection signal 404 from the outside and applies it to the terminal 129 as a chip select signal.

The operation of the data transfer apparatus of this embodiment having the above configuration will be described. Switch control means 4
03 is a selection switch 40 according to the function selection signal 404.
2 is controlled, and the following two states are switched. First, in the first state, the output of the terminal output means 116 is set to the terminal control means 30.
It is in a state of being connected to the chip select signal output terminal 129 via the terminal 3. In the first state, the transmitting-side microcomputer 400 of this embodiment has the same configuration and operates as the transmitting-side microcomputer 300 of the first embodiment of the present invention. Therefore, the description of the operation in the first state is omitted. The next second state is a state in which the output of the terminal output means 116 is directly connected to the chip select signal output terminal 129. When the selection switch 402 is switched to the second state, the output of the terminal output means 116 is directly output to the chip select signal output terminal 129.

As described above, according to the present embodiment, the output of the terminal output means 116 is connected to the chip select signal output terminal 129 via the terminal control means 303, or the chip is output directly without the terminal control means 303. By providing the selecting means 401 capable of selecting whether to connect to the select signal output terminal 129, the chip select signal output terminal 129
Can be used as the following two types of output terminals. First, the first type of output terminal, when the operation of the terminal output state is performed during the serial input / output described in the first embodiment of the present invention, the actual change of the terminal output state is terminated by the serial input / output. This is an output terminal that delays until time. Next, the second type output terminal is an output terminal in which the actual terminal output state changes when the terminal output state is manipulated regardless of serial input / output.
It is possible to realize a highly versatile data transfer device by selectively using these two types.

Next, a third embodiment embodying the invention of claim 4 of the present application will be described with reference to the drawings. Figure 4
FIG. 13 is a block diagram of a transmission side microcomputer and a communication processing unit of a serial bus in a third embodiment. The transmitting side microcomputer, the serial bus, and the receiving side microcomputer (not shown) of this embodiment shown in FIG. 4 are basically the same as those of the transmitting side microcomputer, the serial bus, and the conventional example of the first embodiment shown in FIG. Since it has the same configuration as the receiving-side microcomputer, the same components will be assigned the same reference numerals and detailed description thereof will be omitted. In FIG. 4, the transmission side microcomputer 500 is an example of a data transfer device, and the chip select signal output terminal 129 is an example of an output terminal. The reading means 501 is an example of a reading means for reading the terminal control signal or the state of the output terminal as set forth in claim 4 of the present invention. That is, the output of the terminal output means 116 and the output of the terminal control means 303 are given to the reading means 501. The reading means 501 is composed of a changeover switch for switching these inputs by an external read command 502, and the output thereof is given to the CPU in the transmitting side microcomputer 500 (not shown) as a read signal 503.

The operation of the data transfer apparatus of this embodiment having the above configuration will be described. The data transfer operation of the data transfer apparatus in this embodiment is the same as the operation of the data transfer apparatus shown in the first embodiment of the present invention, and therefore its explanation is omitted. The reading means 501 follows the read command 502 and outputs the terminal control signal 120 or the chip select signal 306.
Is output to a CPU (not shown) as a terminal output state signal 503. Terminal control signal 120 and chip select signal 30
When the six states are compared, they can be divided into the following two types of states. In one state, the terminal control signal 120 is output as it is as the chip select signal 306, that is, the level of the terminal control signal 120 and the chip select signal 306 match. The other state is a state in which the levels of the terminal control signal 120 and the chip select signal 306 do not match, that is, during the serial transfer, and both signals do not match until the serial transfer ends, but the serial transfer does not occur. When is completed, the levels of both signals match. In order to check which one of these states is present, first the state of the terminal output state signal 503 is checked, then the read means 501 is switched by the read command 502, and the terminal output state signal 503 is again displayed.
You can check the state of.

As described above, according to the present embodiment, by providing the reading means 501 for reading the state of the terminal control signal 120 or the chip select signal 306 by the read command 502, the output state of the chip select signal output terminal 129 is changed. It is possible to determine which of the terminal control signal 120 and the chip select signal 306 is in the matched state. By enabling determination of these two states, the following advantages occur. That is, it is possible to limit the range of the location of the failure or the location of the bug at the time of debugging in programming the microcomputer. For example, consider a case where the chip select signal 306 does not go to H level even if the chip select instruction 118 is issued. in this case,
If the terminal control signal 120 is at the H level, it can be limited that the terminal control means 303, the clock start detection means 301, or the clock completion detection means 302 has a cause, and if the terminal control signal 120 is at the L level. It can be limited that the terminal output means 116 has a cause.

In the first, second, and third embodiments, the clock completion detecting means 302 detects the completion of the transfer of data in one transfer unit by using the counter for counting the number of clocks. The means for detecting the completion of data transfer for one transfer unit is not limited to this. For example, if the clock line is H
It is also possible to detect the completion of the transfer of data in one transfer unit when the time at the level, that is, the time when the clock is not input is a certain time or more.

Although the microcomputer has been described as an example of the data transfer device in the first, second and third embodiments,
The data transfer device is not limited to the microcomputer. For example, serial input / output EEPROM (E-PROM,
Electorical Erasable Programable Read Only Memory
The present invention can also be applied to a general-purpose LSI such as a RAM) or a RAM (Random Access Memory) or a dedicated LSI such as a DSP (Digital Signal Processor).

In the first, second, and third embodiments, the terminal operation permission signal output means 304 and the D latch 305 are used as the terminal control means 303, but the method for realizing the terminal control means is this. Not limited to For example, an electric circuit that monitors and stores the state of the terminal control signal at a constant cycle and inputs a terminal operation prohibition instruction and a terminal operation permission instruction to determine the output state may be used as the terminal control means.

Although the switch control means and the selection switch are used as the selection means in the second embodiment,
The method of realizing the selection means is not limited to this. For example, an electric circuit for switching between the chip select signal output terminal and the terminal output means or the electrical connection via the terminal control means according to the terminal function signal may be used as the selection means.

[0031]

As described above, in the data transfer device according to the present invention, when the output state of the terminal is changed during the serial data transfer, the output state of the terminal is actually changed after the end of the serial data transfer. By providing the terminal control means for delaying the data transfer, it is possible to realize a data transfer device with a light load on data transfer. That is, when manipulating the output state of the terminal after starting the data transfer,
It is possible to realize a data transfer device that can perform normal data transfer even if an operation is performed without waiting until the data transfer is completed. As a result, the following two effects of the conventional data transfer device can be eliminated. The first is the burden of having to wait until the end of data transfer when attempting to operate the output state of the terminal after starting the data transfer. Second,
In order to avoid the first burden described above, consider the case where the end of data transfer is used as a trigger for interrupt processing and the output state of the terminal is manipulated during the interrupt processing. In this case, it takes time for the process to shift to the interrupt processing routine and time for the process to return from the interrupt processing routine to the normal routine, which is a burden on the data transfer device and the process itself becomes complicated. It is a burden.

Further, in the data transfer apparatus according to the third aspect of the present invention, whether the terminal control signal is output to the output terminal via the terminal control means or directly to the output terminal without the terminal control means. Is provided with a terminal function signal. Therefore, it is possible to select whether or not to delay the change in the actual terminal output state until the end of serial input / output when the terminal output state is manipulated during the serial input / output as the output terminal of the control signal. As described above, by properly using the output terminal as the two types of output terminals, the versatility of the data transfer device can be enhanced.

Further, the data transfer apparatus according to the invention of claim 4 of the present application is provided with an output terminal reading means for reading the terminal control signal and the output signal of the terminal control means. Therefore, it is possible to realize a data transfer device capable of determining whether the output terminal of the control signal matches the level of the terminal control signal or the output level of the terminal control means. That is, by distinguishing between these two states, the first state can easily identify the cause when the output level of the output terminal does not change. In other words, if the actual output state of the output terminal does not change when the operation to change the terminal control signal is performed, it does not change because the serial transfer is in progress, or the operation to change the terminal control signal is normal. The effect is that it is possible to easily identify whether or not the change does not occur due to the fact that it has not been performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a transmitting side microcomputer, a receiving side microcomputer and a serial bus in a first embodiment of the present invention.

FIG. 2 is a timing diagram of data transfer in the first embodiment of the present invention.

FIG. 3 is a block diagram of a transmitting side microcomputer, a receiving side microcomputer and a serial bus in a second embodiment of the present invention.

FIG. 4 is a block diagram of a transmitting side microcomputer, a receiving side microcomputer and a serial bus in a third embodiment of the present invention.

FIG. 5 is a block diagram of a transmitting side microcomputer, a receiving side microcomputer and a serial bus in a conventional data transfer device.

FIG. 6 is a timing chart of data transfer in the conventional data transfer device.

[Explanation of symbols]

 101, 300, 400, 500 Transmission side microcomputer 102 Reception side microcomputer 103 Data line 104 Clock line 105 Chip select line 106 Serial bus 107 Transmission buffer means 110 Data bus 111 Clock supply means 113 Address bus 116 Terminal output means 120 Terminal control signal 301 Clock start detection means 302 Clock completion detection means 303 Terminal control means 304 Terminal operation permission signal output means 305 D latch 401 Selection means 402 Selection switch 403 Switch control means 501 Reading means

Claims (4)

[Claims] 1. A data transfer method for intermittently serially transferring data for each transfer unit between a plurality of data transfer devices connected by a data line, a clock line, and a control line, the data transfer device transmitting data. Is outputting data of one transfer unit to the data line in synchronization with the clock of one transfer unit supplied from the clock line or an internal clock generating means, and outputting the data of one transfer unit. When the output state of the output terminal of the control line is to be changed to, the output state of the output terminal is changed after the output of the data of one transfer unit is completed, and the data transfer device that receives the data is Data of one transfer unit in synchronization with the clock of one transfer unit supplied from the clock line or the internal clock generation means Data transfer method, characterized in that is intended to enter. 2. A data transfer device for intermittently serially transferring data for each transfer unit between a plurality of data transfer devices connected by a data line, a clock line and a control line, and holding the data to be transferred. Transmission buffer means for serially outputting data of one transfer unit in synchronization with a clock supplied for one transfer unit; clock supply means for supplying a clock of one transfer unit to the transmission buffer means during data transfer; A clock start detection means for detecting that the clock input is started to the buffer means and outputting a terminal operation prohibition instruction, and a terminal for detecting that the input of the clock of one transfer unit is completed to the transmission buffer means. The clock completion detection means for outputting the operation permission command and the terminal control signal of the control line are input, Together during the period from the input terminal operation permission instruction from the serial clock completion detecting section until you enter the terminal operation prohibition instruction from said clock start detecting means outputs the terminal control signals,
After the terminal operation prohibition command is input, until the terminal operation permission command is input, the terminal control signal immediately before the terminal operation prohibition command is input is output, and when the terminal control signal changes during the period. And a terminal control unit that controls an output terminal of the control line by changing an output state after the terminal operation permission command is input. 3. A data transfer device for intermittently serially transferring data for each transfer unit between a plurality of data transfer devices connected by a data line, a clock line and a control line, and holding data to be transferred. Transmission buffer means for serially outputting data of one transfer unit in synchronization with a clock supplied for one transfer unit; clock supply means for supplying a clock of one transfer unit to the transmission buffer means during data transfer; A clock start detection means for detecting that the clock input is started to the buffer means and outputting a terminal operation prohibition instruction, and a terminal for detecting that the input of the clock of one transfer unit is completed to the transmission buffer means. The clock completion detection means for outputting the operation permission command and the terminal control signal of the control line are input, Together during the period from the input terminal operation permission instruction from the serial clock completion detecting section until you enter the terminal operation prohibition instruction from said clock start detecting means outputs the terminal control signals,
After the terminal operation prohibition command is input, until the terminal operation permission command is input, the terminal control signal immediately before the terminal operation prohibition command is input is output, and when the terminal control signal changes during the period. Is a terminal control unit that changes the output state after inputting the terminal operation permission command to control the output terminal of the control line, and a terminal function signal is input, and outputs the terminal control signal or the output of the terminal control unit to the terminal. A data transfer device, comprising: a selection unit that switches according to a function signal and outputs to an output terminal. 4. A data transfer device for intermittently serially transferring data for each transfer unit among a plurality of data transfer devices connected by a data line, a clock line and a control line, and holding data to be transferred. Transmission buffer means for serially outputting data of one transfer unit in synchronization with a clock supplied for one transfer unit; clock supply means for supplying a clock of one transfer unit to the transmission buffer means during data transfer; A clock start detection means for detecting that the clock input is started to the buffer means and outputting a terminal operation prohibition instruction, and a terminal for detecting that the input of the clock of one transfer unit is completed to the transmission buffer means. The clock completion detection means for outputting the operation permission command and the terminal control signal of the control line are input, Together during the period from the input terminal operation permission instruction from the serial clock completion detecting section until you enter the terminal operation prohibition instruction from said clock start detecting means outputs the terminal control signals,
After the terminal operation prohibition command is input, until the terminal operation permission command is input, the terminal control signal immediately before the terminal operation prohibition command is input is output, and when the terminal control signal changes during the period. The terminal control means controls the output terminal of the control line by changing the output state after the terminal operation permission command is input, and the reading means for reading the terminal control signal and the output state of the terminal control means. A data transfer device comprising: