JPH05282126A - Display control device - Google Patents

Abstract

PURPOSE:To rapidly display medium low resolution plotting data having a format different from that of a high resolution screen as a window on the screen. CONSTITUTION:The display position of a window screen for video graphic array(VGA) plotting data is compared with a coordinate address showing a scanning position for displaying a high resolution picture on a display 3 and whether the scanning position is on the outside or inside of the window screen is detected by a picture switching circuit 16 based upon the compared result. When the scanning position is included in the window screen, memory plane type VGA plotting data are read out instead of packed pixel type XGA (extended graphic array) plotting data and converted into a video signal by a VGA display circuit 182 and the video signal is displayed on the high resolution display screen of the display 3 as a window. Thereby the image of the VGA plotting data can directly be displayed on the high resolution screen based upon the XGA specification as a window.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
In particular, it relates to a display control device used in a computer system such as a personal computer.

[0002]

2. Description of the Related Art Generally, a flat panel type display such as a liquid crystal display or a plasma display or a CRT display is used as a display device of a computer system such as a personal computer. Currently, most of the display controls of these displays are VGA (Video Graphics Arra).
This is done using a display control subsystem called y). Therefore, many application programs started on the computer system are also created so as to conform to the VGA specifications. In this VGA, a mode such as 640 × 480 pixels and simultaneous display of 16 colors is prepared.

However, in recent computer systems, DTP (DeskTop Publics) is used.
Hing) is required for advanced operation using a high-saturation screen, and the resolution and the number of display colors provided by VGA are not suitable for such operation.

Therefore, recent computer systems have an XGA (Extended Graphics) having a display mode capable of realizing a higher resolution display than VGA.
Display control subsystems called Arrays are beginning to be used. In this XGA, 1024 × 76
Since a high-resolution mode such as simultaneous display of 8 pixels and 256 colors is prepared, many windows can be displayed on the same screen. Therefore, the XGA can sufficiently provide the performance required for the graphical user interface that heavily uses the window display including the operation of the DTP.

However, in the XGA display control subsystem, the window that can be displayed on the XGA high resolution screen is limited to the drawing data created by the application program that meets the XGA specifications, and conforms to the VGA specifications. The drawing data created by the conventional application program cannot be displayed on the XGA high resolution screen as one of the windows. Because XG
This is because not only the resolution but also various specifications such as the mapping format of the color information with respect to the image memory are different between A and the conventional VGA.

Therefore, in order to display the middle and low resolution drawing data created by the conventional application program conforming to the VGA specification on the XGA high resolution screen, the drawing data of the VGA specification is XGA by software. It is necessary to emulate the specifications.

However, in such an emulation process, it is necessary to convert the drawing data of the VGA specification into the XGA specification by software once and rewrite it in the image memory, so that the processing is often performed. Is required. For this reason, when software emulation is performed, there arises a problem that the operation speed becomes very slow and the performance required for the graphical user interface cannot be exhibited.

Therefore, in practice, in a computer system having an XGA display subsystem, a window of medium-low resolution drawing data created by a conventional application program conforming to VGA specifications is displayed on a high resolution screen of XGA. It was difficult to take an operational form such as displaying.

[0009]

Conventionally, in order to display the drawing data of medium and low resolution created by an existing application program on a high resolution screen having a specification different from that of the drawing data, an emulation process by software is used. It is necessary to convert the low-resolution drawing data so as to meet the specifications of the high-resolution drawing data, and there is a drawback that the operation speed becomes slow.

The present invention has been made in view of the above circumstances, and it is possible to display the drawing data of medium and low resolution at high speed on a high resolution screen having a specification different from that of the drawing data without performing emulation processing by software. It is an object of the present invention to provide a display control device capable of performing such a display control.

[0011]

Means and Actions for Solving the Problems
A display control device for controlling display of a display capable of displaying a screen at a first resolution, comprising:
An image memory having first and second storage areas in which the drawing data and the second drawing data having a second resolution lower than the first resolution are stored in different color information mapping formats; Means for generating a coordinate address indicating a scanning position on the display screen of the first resolution in synchronization with the scanning timing for displaying the screen of the first resolution on the display; and the first and second storage areas. Means for generating first and second read addresses for reading the first and second drawing data, respectively, and an address for selecting one of the first and second read addresses and supplying the selected one to the image memory. A selection means and a window image for window-displaying the second drawing data of the second resolution on the display screen of the first resolution of the display. Means for designating a display position, first and second video signal conversion means for converting the first and second drawing data into the first and second video signals in accordance with corresponding color information mapping formats, respectively. Video signal selecting means for selecting one of the first and second video signals and supplying it to the display, and a scanning position on the display screen of the first resolution based on the window screen display position and the coordinate address. Is outside the window screen or inside the window screen, the first
And a means for controlling the selection operation of the address selection means and the video signal selection means so that the first and second drawing data are switched and displayed on the display screen of the resolution outside the window screen and inside the window screen. It is characterized by

In this display control device, the display position of the window of the second drawing data designated by the display position designating means is the coordinate address indicating the scanning position for displaying the screen of the first resolution on the display. It is compared, and it is detected whether the scanning position is outside the window screen or inside the window screen based on the comparison result. When the scanning position is outside the window screen, the first drawing data designated by the first read address is read, and this is converted into the first video signal by the first converting means. Then, the first video signal is supplied to the display and displayed on the screen at the first resolution. On the other hand, when the scanning position is within the window screen, the second drawing data designated by the second read address is read out, and this is converted into the second video signal by the second converting means. .. Then, the second video signal is supplied to the display and is displayed in the window on the display screen of the first resolution. In this way, the first and second drawing data having different color information mapping formats are converted into the first and second video signals by different conversion means, and the first and second video signals are converted into the first and second video signals outside and inside the window screen area. Since the second video signal is switched and supplied to the display, the second drawing data with a lower resolution and a different specification can be speeded up on the first high resolution screen without performing emulation processing by software. The window can be displayed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a display control system according to an embodiment of the present invention. The display control system 10 is a display control subsystem conforming to the XGA specifications, and is realized in the form of an expansion board connected to a system bus 2 of a computer system such as a personal computer. The display control device 10 includes an address buffer 11, a data buffer 12, a system bus interface 13, a CRT / memory controller 1.
4, a drawing coprocessor 15, a screen switching circuit 16, a dual port image memory (VRAM) 17, a video signal conversion circuit 18, a video signal selector 19, and a video DAC 20.

The system bus interface 13 and the CRT / memory controller 14 control the entire display control system 10 and the display 3. CRT /
The memory controller 14 supplies to the display 3 various control signals (horizontal synchronization signal, vertical synchronization signal, etc.) for displaying a screen on the display 3 with a high resolution (for example, 1024 × 768 dots) that conforms to the XGA specifications. Access control of the dual port image memory (VRAM) 17 is performed. This CRT / memory controller 14
Is provided with an XGA display address generation circuit 141, a VGA display address generation circuit 142, and an address selector 14 in order to read drawing data from the dual port image memory (VRAM) 17.

The XGA display address generation circuit 141 generates an XY address indicating the coordinate position on the display screen corresponding to the scanning position in synchronization with the scanning timing for displaying the high resolution screen on the display 3. , XGA specification drawing data stored in the dual port image memory (VRAM) 17 is transferred to the serial port (S
O) to generate an XGA display address for reading. The update of the XGA display address is performed in synchronization with the update of the scan line when the image data for one display line can be read by one address input. X
The -Y address is supplied to the screen switching circuit 16, and the XGA display address is supplied to the first input of the selector 143.

The VGA display address generation circuit 142 generates a VGA display address for reading the drawing data of the VGA specification of the medium and low resolution stored in the dual port image memory (VRAM) 17 from its parallel port (DATA). .. This VGA display address is supplied to the second input of the address selector 143. The address selector 143, under the control of the screen switching circuit 16, outputs the X
Select one of the GA display address and the VGA display address and set it to the dual port image memory (VRAM) 17
Address input (ADDR).

Dual port image memory (VRAM) 1
When the drawing data of the XGA specification is read from 7, the dual port image memory (VRAM) 17 is set to the data transfer cycle mode by the CRT / memory controller 14, and the dual port image memory (VRAM) 17 of the dual port image memory (VRAM) 17 is set. X for address input (ADDR)
The GA display address is input.

In this data transfer cycle, XG
Data of a plurality of consecutive bytes starting from the storage position designated by the A display address (for example, 1024 x
Data for one display line on a high-resolution screen of 768 dots) is sequentially read from a 32-bit wide serial port (SO).

On the other hand, a dual port image memory (VRA
M) when reading VGA specification drawing data from the dual port image memory (VRAM) 17,
The RT / memory controller 14 sets the memory read cycle mode, and the address input (ADD) of the dual port image memory (VRAM) 17 is set.
In R), the VGA display address is input. In this memory read cycle, the drawing data at the storage position designated by the VGA display address is read.
In this case, a maximum of 32 bits of data can be read out by one read access.

The dual port image memory (VRA
M) 17 can be directly accessed by the host CPU 1. In this case, the host CPU1
Access is performed via the parallel port (DATA), so during the VGA data display period during which VGA specification drawing data is read from the parallel port (DATA), the idle time of the memory cycle is used. To be done.

The drawing coprocessor 15 is a host CPU 1
In response to the instruction from the dual port image memory (V
Various kinds of drawing functions are provided for drawing data in the RAM 17, pixel block transfer, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, X -Has functions such as addressing at the Y coordinate.

The screen switching circuit 16 sets the display position coordinates of the VGA window screen preset by the user and the XY address indicating the current scanning position on the display screen, which is supplied from the XGA display address generation circuit 141. Based on the comparison result, the selection operation of the selectors 143 and 19 is controlled so that the XGA specification drawing data is displayed outside the VGA window screen and the VGA specification drawing data is displayed inside the VGA window screen.

Dual port image memory (VRAM) 1
A serial port used for serial access and a parallel port for random access are provided at 7. This dual port image memory (VRAM)
In FIG. 17, drawing data of XGA specifications and drawing data of VGA specifications are drawn. In this case, the drawing data of the XGA specification is created by an application program or the like conforming to the XGA specification, and the dual port image memory (VRAM) 17 by the packed pixel method is used.
Is drawn to. The packed pixel method is a color information mapping format in which one pixel is represented by consecutive bits on a memory, and for example, one pixel is 1, 2, 4, 8, or 16 pixels.
The method represented by bits is adopted.

On the other hand, VGA specification drawing data is VGA
It is created by a conventional application program or the like conforming to the specifications, and is drawn in the dual port image memory (VRAM) 17 by the memory plane method. This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, when there are four planes, one pixel is represented by a total of 4 bits of data, one bit for each plane.

Video signal conversion circuit 18 and video DA
C20 is a dual port image memory (VRAM) 17
The drawing data read from the R, G. The video signal conversion circuit 18 is provided with an XGA display circuit 181 and a VGA display circuit 182, which is for converting to a B analog color signal.

The XGA display circuit 181 is a serial port (SO) of the dual port image memory (VRAM) 17.
The drawing data of the XGA specification read from is converted into video data pixel by pixel. This conversion process is controlled according to the contents of the packed pixel method in which the XGA specification drawing data is drawn. For example, 1 pixel is 8
In the case of 8 bits / pixel represented by bits, the 32-bit data read from the serial port (SO) of the dual port image memory (VRAM) 17 is XG.
It is divided into 8-bit units by the A display circuit 181,
The 8 bits are output as video data for one pixel.

The VGA display circuit 182 is a parallel port (DAT) of the dual port image memory (VRAM) 17.
The drawing data of the VGA specification read from A) is converted into video data pixel by pixel. This conversion process is controlled according to the number of planes on which the VGA specification drawing data is drawn. For example, if one pixel of data is 4
In the case of the 4-plane system in which the data is separately stored in the plane, 32-bit read data from the parallel port (DATA) of the dual port image memory (VRAM) 17 is first read by the VGA display circuit 182 in correspondence with each of the 4 planes. It is divided into bit data units, and thereafter, the 4-bit data is converted into 8-bit video data via the color palette.

Under the control of the screen switching circuit 16, the selector 19 has an XGA display circuit 181 and a VGA display circuit 1.
Select either output of 82 and set it to video DA
Supply to C20. The video DAC 20 has a selector 19
R, G, B analog video signals are generated from the video data input via.

The display 3 is a CRT or a flat panel display (such as a liquid crystal display or a plasma display) capable of high resolution display. On the display screen of this display 3, the drawing data of the XGA specification is 1 at maximum as shown in the figure.
024 × 768 dots are displayed on the screen, and the VGA specification drawing data is displayed on the screen in a window having a maximum size of 640 × 480 dots. In this case, the horizontal and vertical sync signals supplied to the display 3 are XG even when the VGA specification drawing data is displayed in the window.
It is the same timing as when the high-resolution drawing data of A specification is displayed on the screen.

The display position of the window screen is the start point coordinates (Xs, Ys) and the end point coordinates (X
e, Ye). Here, X indicates an address in the horizontal direction, and Y indicates an address in the vertical direction. FIG. 2 shows an example of a memory map of the dual port image memory (VRAM) 17.

As shown in the figure, in the dual port image memory (VRAM) 17, drawing data of XGA specifications and drawing data of VGA specifications are stored in separate storage areas. In this case, from the perspective of the CPU 1, the storage area for the VGA specification drawing data is displayed in hexadecimal at the address “A”.
A fixed space of 128 Kbytes from "0000" to "BFFFF" is allocated. On the other hand, the storage area of the drawing data of the XGA specification is seen from the CPU 1 in the protect mode as shown in the figure. 10
It is allocated to any designated space after 0000 ″.

As described above, since the storage areas for XGA and VGA are separately secured in the dual port image memory (VRAM) 17, the host CPU 1 operates in XGA.
The drawing data of the specifications and the drawing data of the VGA specifications are drawn in the corresponding storage areas. Next, with reference to FIG. 3, the principle of the packed pixel method used as the color information mapping method of the XGA specification drawing data will be described.

Here, the case of 8 bits / pixel is illustrated. In the case of 8 bits / pixel, as shown in the figure, the color information of each dot (dot 1, dot 2, ...) On the display screen is composed of 8 bits. Next, with reference to FIG. 4, the principle of the memory plane system used as the color information storage format of the VGA specification drawing data will be described.

Here, the case of the 4-plane system is illustrated. In case of 4-plane system, as shown in the figure,
Each dot on the display screen (dot 1, dot 2,
Color information of 4), one bit for each plane in total 4
It is composed of bit data. In this case, color information corresponding to R, G, B, I (luminance) can be assigned to each of the four planes. FIG. 5 is a diagram showing a circuit portion for reading out drawing data, which is a feature of the present invention, extracted from the configuration of the display control device 10 shown in FIG.

As shown, the screen switching circuit 16 is
Four registers 161-164 and four comparators 165
˜168 and a switching signal generating circuit 169. The registers 161 to 164 store the coordinate address indicating the window screen display position of the VGA drawing data. In this case, since the start point (Xs, Ys) and the end point (Xe, Ye) of the window screen display position are designated by the user, the registers 161 to 164 respectively correspond to Xs (corresponding to the designated coordinates) according to the designated coordinates. X start address), Xe (X end address), Ys (Y start address), and Ye (Y end address) are set by the host CPU 1. Registers 161 to 164
The set values of are respectively supplied to the first inputs of the comparators 165 to 168.

The second inputs of the comparators 165 and 166 are connected to X
The X address in the XY address indicating the scanning position on the display screen output from the GA display address generation circuit 141 is input. Further, the Y address in the XY address indicating the scanning position on the display screen output from the XGA display address generation circuit 141 is input to the second inputs of the comparators 167 and 168.

The comparator 165 generates a match signal of logical "1" when the X address output from the XGA display address generation circuit 141 matches the X start address.
Similarly, the comparator 166 uses the XGA display address generation circuit 1
When the X address output from 41 matches the X end address, a match signal of logic "1" is generated, and the comparator 16
7 generates a coincidence signal of logic "1" when the Y address output from the XGA display address generation circuit 141 coincides with the Y start address.
When the Y address output from the GA display address generation circuit 141 matches the Y end address, a match signal of logic "1" is generated.

The switching signal generating circuit 169 is provided in the comparator 1
Detecting the switching of the scanning position from outside the window screen area to the inside of the window screen area and the switching of the scanning position from the inside of the window screen area to the outside of the window screen area based on the combination of the coincidence signals respectively output from 65 to 168. .. When the switching of the scanning position from the outside of the window screen area to the inside of the window screen area is detected, the switching signal generating circuit 169 detects that the data displayed on the screen is X.
The selection operation of the selectors 143, 19 is switched from XGA to VGA so as to switch from GA to VGA drawing data. In addition, when the switching of the scanning position from the inside of the window screen area to the outside of the window screen area is detected,
The switching signal generating circuit 169 selects the selectors 143 and 19 from VGA to XGA so that the data displayed on the screen can be switched from VGA to XGA drawing data.
Switch to the side.

When the selection operation of the selectors 143, 19 is set to the XGA side by the switching signal generation circuit 169, the dual port image memory (VRAM) 1
By inputting the XGA display address in 7, XG
A specification drawing data is a dual port image memory (VR
(AM) 17 is sequentially read from a 32-bit wide serial port (SO). The drawing data of this XGA specification is
It is sent to the video DAC 20 through the parallel / serial conversion circuit (P / S) 182a of the XGA display circuit 182, and is converted into R, G, B analog video signals there.

On the other hand, when the selection operation of the selectors 143, 19 is set to the VGA side by the switching signal generation circuit 169, the dual port image memory (VRA
By inputting the VGA display address to M) 17, the VGA specification drawing data is read from the 32-bit parallel port (DATA) of the dual port image memory (VRAM) 17. The VGA specification drawing data includes parallel / serial conversion circuit (P / S) 181a and color palette 181b of the VGA display circuit 181.
To the video DAC 20 via R, G, B
Are converted to analog video signals.

Next, referring to FIG. 6, the VGA display circuit 1
82 parallel / serial conversion circuit (P / S) 182a
The operation of converting VGA drawing data into an analog video signal, which is executed by the color palette 182b and the video DAC 20, will be specifically described.

For example, as shown in FIG.
When the VGA specification drawing data is stored in each plane, 8 bits of the storage location designated by the VGA address are simultaneously read from each of the planes 0 to 3, and a total of 32 bits of data are dual port images. It is read from the parallel port (DATA) of the memory (VRAM) 17. This 32-bit data is parallel /
It is supplied to the serial conversion circuit 182a. The parallel / serial conversion circuit 182a converts 8-bit parallel data into serial data for each plane, and outputs 4-bit data corresponding to planes 0 to 3, respectively.
This 4-bit data indicates color information for one pixel.

The 4-bit data from the parallel / serial conversion circuit 182a is the decoder 3 in the palette 182b.
1 is input and decoded. As a result of decoding the 4-bit data, 1 in the color palette register group 32
One of the six color palette registers is selected. 6-bit color information is set in each color palette register. Which of the 16 color palette registers is selected is determined by the content of the 4-bit data, and thus 16-color simultaneous display can be realized.

The 6 bits set in the color palette register selected by the decoder 31 are read out, and the 2 bits set in the color select register 33 are added to this to generate a total of 8 bits of data. Is generated. The 8-bit data from the palette 181b is sent to the video DAC 20.

In the video DAC 20, 8-bit data is input to the decoder 41 and decoded. As a result of decoding the 8-bit data, one of 256 color registers in the color register group 42 is selected. In each color register, a total of 18 bits of color information, in which 6 bits of color information is assigned to each of R, G and B, is set. The 6-bit data of each R, G, B set in the color register selected by the decoder 41 corresponds to the corresponding digital / analog converter (DA).
C) Input to 43 to 45. From the digital / analog converter (DAC) 43 to 45, analog R, G,
B video signals are output respectively.

Next, referring to FIG. 7, the XGA display circuit 1
81 parallel / serial conversion circuit (P / S) 181a
And the conversion operation from the XGA drawing data to the analog video signal executed by the video DAC 20 will be specifically described.

For example, when drawing data of XGA specifications is stored at 8 bits / pixel as shown in the drawing, 32-bit data corresponding to image data of 4 dots is serial port of the dual port image memory (VRAM) 17. It is supplied from (SO) to the parallel / serial conversion circuit 181a. In the parallel / serial conversion circuit 181a, data is sequentially cut out in units of one pixel (8 bits) from the image data of 4 pixels (8 × 4 = 32 bits).
It is output serially in 8-bit units.

The 8-bit data from the parallel / serial conversion circuit 181a is sent to the video DAC 20 in the same manner as the output of the palette 182b in the case of VGA drawing data. In the video DAC 20, 8-bit data is input to the decoder 41 and decoded. This 8
As a result of decoding the bit data, the color register group 42
One of the 256 color registers in it is selected. In this way, depending on the contents of 8-bit data, 25
Since any one of the six color registers is selected, 256-color simultaneous display can be realized. In each color register, a total of 18 bits of color information, in which 6 bits of color information is assigned to each of R, G and B, is set. The 6-bit data of R, G, B set in the color register selected by the decoder 41 is input to the corresponding digital / analog converters (DAC) 43 to 45. Digital / analog converter (DAC) 43-
The analog video signals of R, G and B are output from 45.

Even when the drawing data of the XGA specification is 4 bits / pixel, the conversion processing to the video data can be performed in the same manner. However, in this case, since the 32-bit data read from the dual port image memory (VRAM) 17 is data for 8 pixels,
In the parallel / serial conversion circuit 181a, data is sequentially cut out in units of 1 pixel (4 bits) from the image data of 8 pixels and is serially output in units of 4 bits.

Next, with reference to FIGS. 8 to 10, the operation of the display control device 10 of FIG. 1 in the case of displaying the VGA low-medium resolution screen on the XGA high-resolution screen will be described.

Here, as shown in FIG.
It is assumed that a 640 × 480-dot VGA specification medium-low resolution window screen is displayed on a 024 × 768-dot XGA specification high-resolution screen. It is assumed that the display position of the window screen is specified by the starting point coordinates (Xs, Ys) and the ending point coordinates (Xe, Ye).

In this case, as shown in FIG. 9, when the Y coordinate on the display screen is in the range of Y0 to Ys-1 and in the range of Ye + 1 to Y767, the dual port image memory (VRAM) 17 is used. The XGA specification drawing data read out from the serial port (S0) is displayed on the screen.
Further, in the range of the Y coordinate on the display screen from Ys to Ye, when the X coordinate of the scanning position on the screen is X0 to Xs-1, the drawing data of the XGA specification is displayed on the screen and the scanning position on the screen is changed. When the X coordinate is between Xs and Xe, VGA specification drawing data read from the parallel port (DATA) of the dual port image memory (VRAM) 17 is displayed on the screen, and the X coordinate of the scanning position on the screen is Xe + 1. When it is in the range from to X1023, XGA specification drawing data is displayed again on the screen. FIG. 10 shows detailed operation timings when the screen display data is switched between XGA and VGA as shown in FIG.

In FIG. 10, (a) is a horizontal synchronizing signal (H-SYNC) supplied from the CRT / memory controller 14 to the display 3, and (b) is an actual data display period (1) in one horizontal scanning period. H-DISPLAY)
Is.

XGA specification 1024 × on the display 3
When displaying a high-resolution screen of 768 dots, the display 3 is set so that data display of 1024 dots is executed within this data display period (H-DISPLAY).
Are scanned. XGA is synchronized with this scanning timing.
From the display address generation circuit 141, the X address (X-ADDR) and the Y address (Y-ADD) indicating the scanning position on the XGA display screen as shown in (c) and (d) respectively.
R) is output. The X address (X-ADDR) is sequentially incremented according to the dot to be scanned. The Y address (Y-ADDR) is incremented every time the display line to be scanned is updated.

(E), (f) and (g) show the case where the Y coordinate indicating the scanning position is in the range of Y0 to Ys-1, respectively.
The memory cycles corresponding to the case of Ys to Ye and the case of Ye + 1 to Y767 are shown. Here, “XX” indicates a data transfer cycle when reading XGA drawing data from the serial port (SO). This data transfer cycle is set in the horizontal blanking period as shown in the figure, and the XGA address is updated every horizontal blanking period. In the data transfer cycle, one display line of XGA drawing data (1024 dots = 1024 × 8 bits) is read by inputting one XGA address.

As shown in (f), when the Y coordinate is in the range of Y0 to Ys-1, the X coordinate is X.
When it is in the range of s to Xe, the memory read cycle "VV" is set. This memory read cycle "V
V ”is a parallel port (DAT) for drawing VGA data.
This is a read cycle for reading from A), and 32-bit data can be read by one read access as described above.

During the read cycle "VV" when the X coordinate is in the range of Xs to Xe, as shown in (h), the VGA address (VGA ADDR).
Are input to the dual port image memory (VRAM) 17 while being sequentially updated every one read cycle “VV” such as “VA”, “VA + 1”, ... “VA + 79”. As described above, 32 bits = 8 bits × 4 (4 is the number of planes) is read by one read cycle “VV” with such a VGA address, but since one pixel is 4 bits, 1 The pixel data read out by one read cycle is for 8 dots. Therefore, when the X coordinate is in the range of Xs to Xe, 80 read cycles are performed per display line, and 640 dots of data are read by this.

Further, here, "VA" indicates the line start address of the storage area in the dual port image memory (VRAM) 17 in which the drawing data of the VGA specification is stored, and as shown in FIG. When the storage area is allocated, "V" for the display line of the coordinate Ys
"A" corresponds to the address "A0000". When the display line to be scanned is switched from Ys to Ys + 1, the offset value is added to the value of "VA". VRAM)
This is the address width in the X direction assigned to the 17 storage areas.

Further, in FIG. 10, "Tf" is V
This is the idle time of the memory cycle during the display period of the drawing data of the GA specifications. Since the VGA specification drawing data is read using the parallel port (DATA), during the VGA specification drawing data display period,
Dual port image memory (VR
Read / write access "CP" to AM17)
Will be executed during the free time "Tf" of the memory cycle. In this case, the access count of the read / write access “CP” by the host CPU 1 is determined by the length of the free time “Tf”. If “Tf” is short, the access is repeated several times to update the drawing data. It is executed separately.

As described above, in this embodiment, V
The display position of the GA drawing data on the window screen is compared with the coordinate address indicating the scanning position for displaying the high-resolution screen on the display 3, and based on the comparison result, is the scanning position outside the window screen or within the window screen? It is detected by the screen switching circuit 16. If the scan position is within the window screen, the packed pixel X
Memory plane VGA instead of GA drawing data
The drawing data is read out, and this is the VGA display circuit 182.
Is converted into a video signal and displayed as a window on the high resolution display screen of the display 3.

As described above, the drawing data having different specifications of XGA and VGA with different color information mapping formats are converted into video signals by different circuits, and the XGA and VGA drawing data are output outside and inside the window screen area. Since the image is switched and supplied to the display 3, the image of the VGA drawing data can be directly displayed on the XGA-specification high resolution screen without performing emulation processing by software.

Therefore, when this display control device 10 is installed in a computer system as a display subsystem, the window of medium-low resolution drawing data created by a conventional application program conforming to VGA specifications is displayed on a high resolution screen of XGA. It is possible to take an operational form such as displaying, and it becomes possible to sufficiently provide the performance required for a graphical user interface which makes heavy use of window display.

In this embodiment, XGA is taken as an example of the specifications of the high resolution drawing data and VGA is taken as an example of the specifications of the medium to low resolution drawing data. If there is, XG
As in the case of A and VGA, medium-to-low resolution drawing data having different specifications can be displayed on the high resolution screen at high speed. In this case, as the high resolution drawing data, for example, SVGA (Super Video Grap) is used.
Hics Array) specifications, and CGA (Color Graphics) for medium and low resolution drawing data.
Adaptor) / EGA (Enhanced Gr)
Apics Adapter) specifications can be applied.

Further, in this embodiment, the drawing data of the XGA specification is read from the serial port of the dual port image memory (VRAM) 17 for simplification of control,
Although the VGA specification drawing data is read from the parallel port and the read / write cycle for updating the drawing data by the host CPU 1 is sacrificed to some extent, both the XGA and VGA drawing data may be read from the serial port. It is possible.

However, in this case, complicated control is required to switch between the data transfer cycle for reading the XGA drawing data and the data transfer cycle for reading the VGA drawing data.

[0067]

As described above, according to the present invention, it is possible to quickly display, on a high-resolution screen, medium-to-low-resolution drawing data having different specifications from the high-resolution screen without performing emulation processing by software. Therefore, it is possible to effectively use the existing software resources that meet the specifications of the medium and low resolution drawing data and sufficiently provide the performance required for the graphical user interface.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall system configuration of a display control device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of allocation of storage areas on an image memory provided in the embodiment.

FIG. 3 is a diagram showing an example of a memory mapping format of high resolution drawing data displayed on a high resolution display screen in the embodiment.

FIG. 4 is a diagram showing an example of a memory mapping format of medium-to-low resolution drawing data displayed in a window on a high resolution display screen in the embodiment.

5 is a circuit configuration diagram showing a main part extracted from the system configuration of FIG.

FIG. 6 is a view for explaining the principle of the conversion operation from the medium / low resolution drawing data to the video signal, which is executed in the embodiment.

FIG. 7 is a view for explaining the principle of a conversion operation from high-resolution drawing data to a video signal executed in the same embodiment.

FIG. 8 is a diagram showing an example of a window screen assigned to a high resolution screen in the embodiment.

FIG. 9 is a diagram showing how the drawing data displayed on the high resolution screen in the embodiment is switched.

FIG. 10 is a timing chart for explaining a drawing data switching operation executed in the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Host CPU, 2 ... System bus, 3 ... Display, 10 ... Display control device, 14 ... CRT / memory controller, 16 ... Screen switching circuit, 17 ... Dual port image memory, 18 ... Video signal conversion circuit, 19 ... Video Signal selector, 20 ... Video DAC, 141 ... XGA
Display address generating circuit, 142 ... VGA display address generating circuit, 143 ... Address selector, 181 ... XGA display circuit, 182 ... VGA display circuit.

Claims (3)

[Claims] 1. A display control device for controlling display of a display capable of displaying a screen at a first resolution, comprising: a first drawing data having the first resolution; and a second resolution having a resolution lower than the first resolution. An image memory having first and second storage areas in which two drawing data are stored in different color information mapping formats, and in synchronization with scanning timing for displaying the screen of the first resolution on the display. Means for generating a coordinate address indicating a scanning position on the display screen having the first resolution, and the first and second storage areas from the first and second storage areas.
First and second for respectively reading the drawing data of
Means for generating a read address, address selecting means for selecting one of the first and second read addresses and supplying the read address to the image memory, and the second resolution on the display screen of the first resolution of the display.
Means for designating a window screen display position for window-displaying the second drawing data of resolution, and the first and second video signals according to the color information mapping formats corresponding to the first and second drawing data, respectively. First and second video signal converting means for converting into a video signal, video signal selecting means for selecting one of the first and second video signals and supplying the video signal to the display, the window screen display position and the coordinate address Detecting whether the scanning position on the display screen of the first resolution is outside the window screen or inside the window screen based on
Means for controlling the selection operation of the address selection means and the video signal selection means so that the first and second drawing data are switched and displayed on the display screen of the first resolution outside the window screen and inside the window screen. A display control device comprising: 2. The display control device according to claim 1, wherein the first drawing data is stored by a packed pixel system, and the second drawing data is stored by a memory plane system. 3. The image memory is a dual port memory having a serial input / output port for serial access and a parallel input / output port for random access, and the first and second drawing data are serial input / output ports. The display control device according to claim 1, wherein the display control device is read from an output port and the parallel input / output port, respectively.