JP3017882B2 - Display control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for a portable computer, and more particularly to a display control device capable of performing display control corresponding to various flat panel displays.

[0002]

2. Description of the Related Art In recent years, various types of portable laptop or notebook computers have been developed.

[0003] A typical portable computer of this kind is equipped with a flat panel display such as a plasma display (PDP) or a liquid crystal display (LCD) as standard equipment. The flat panel display is provided rotatably in a range between a closed position and a released position with respect to the computer main body. When the flat panel display is set to the closed position, the flat panel display is positioned so as to cover a keyboard integrated with the computer main body, thereby making the computer easy to carry. For this reason, the flat panel display is suitable for a portable computer in that its portability is improved.

Further, recent portable computers have a video output terminal to a color CRT display so that a color CRT display can be connected as needed. Since a color CRT display has been widely used as a monitor of a desktop personal computer, many application programs for the color CRT display have been developed. Therefore, a portable computer that can use a color CRT display can effectively use existing software resources, and can perform the same operation as a desktop type personal computer.

By the way, a flat panel display and a color CRT display require separate display control. In particular, in the case of flat panel displays, the types are abundant, and the specifications of each flat panel display ｛resolution, color / grayscale, display color / grayscale, panel type (TFT-LCD, ST-LCD)
Display control suitable for N-LCD, PDP, etc., timing (horizontal / vertical synchronization signal), polarity (horizontal / vertical synchronization signal, video data, clock, etc.) is required.

For this reason, the conventional display controller is configured so that the display timing and the like can be switched in accordance with the used flat panel display in order to perform display control corresponding to various flat panel displays. Conventionally, this switching is performed by a dip switch or the like provided in the display controller.
This has been done by setting on / off according to the flat panel display used.

However, such on / off setting by the dip switch causes a problem such as an increase in hardware configuration, and thus there is a limit to the type of display that can be determined. Therefore, it is obvious that it will not be possible to cope with the types of flat panel displays that are increasingly increasing in the future.

[0008]

Conventionally, the type of the flat panel display is determined by the on / off setting of the dip switch, and so on.
There is a drawback that there are few types of flat panel displays that can be distinguished.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a simple structure capable of automatically determining the specifications of various flat panel displays, and performing display control according to the used flat panel display. It is an object of the present invention to provide a display control system which can perform the display control.

[0010]

A display control system according to the present invention is provided with a flat panel display and a memory provided in the flat panel display and storing various control information necessary for display control of the flat panel display. A display control device for generating display data to be displayed on the flat panel display and a display timing control signal for controlling the display timing thereof, the display control device being provided between the flat panel display and the display control device; a bidirectional data line, wherein the control information read out the display data or from said memory device generated from the device is transferred, prior to
Transfer direction switching for switching the data transfer direction of the bidirectional data line so that the display data is transferred from the display control device to the flat panel display and the control information is transferred from the flat panel display to the display control device. Means in the display control device.
And the control information is transmitted to the flat panel display.
A) when transferring the data from the memory control device to the display control device.
Control signal for reading the control information from the memory
, And the display timing control signal is flattened.
Before through the signal line to supply to the panel display
Means for supplying to the flat panel display,
The readout provided in a flat panel display.
Read in synchronization with the control signal and supplied to the memory device.
And an address generation circuit for sequentially incrementing the output address value.
It is characterized by having.

In this display control system, a memory device is provided in the panel, and various control information necessary for display control is stored in the memory device. The panel display can be automatically determined, and display control can be performed according to the specifications of various flat panel displays. Further, since the data line to which the display data is transferred is a bidirectional data line, and the control information is read by switching the direction of the bidirectional data line, the signal line between the display control device and the flat panel display is connected. There is no increase in the number. Therefore, the flat panel display can be determined with a simple configuration. In addition, the address generation circuit
Read control signal provided in the
Just a signal to supply the display timing control signal
Supply to flat panel display via wire
Address is supplied to the memory device.
A dedicated address signal line is not required.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a display control device according to an embodiment of the present invention. The display control system 4 has, for example, 1024 × 768 dots, 256
XGA (eXtended G) with simultaneous color display mode
This is a display control system conforming to the specifications of (Raphics Array), and is connected to the system bus 3 of the portable computer.
The display control system 4 includes a flat panel display 40 provided as standard equipment on a portable computer main body and a color CRT display 5 optionally connected.
0, display control is performed for both. As the flat panel display 40, resolution, color / gradation, number of display colors / gradation, type of panel (TFT-LCD, ST
N-LCDs, PDPs, etc.), timings (horizontal / vertical synchronizing signals), and polarities (horizontal / vertical synchronizing signals, video data, clocks, etc.) can be used in various types having different specifications. In this case, these panels are interchangeable, for example from low resolution to high resolution,
Alternatively, the display can be changed from gradation display to color display.

The flat panel display 40 is provided with a ROM 401 in which various status information necessary for display control of the panel is stored. As described above, the status information includes resolution, color / gradation, display color number / gradation number, and panel type (TFT-LCD, STN
−LCD, PDP, etc.), timing (horizontal / vertical synchronization signal), and polarity (horizontal / vertical synchronization signal, video data, clock, etc.). The configuration around the ROM 401 of the flat panel display 40 will be described later with reference to FIG.

The display control system 4 includes a display controller 10 and a dual port image memory (VRA).
M) 30 and a DAC (D / A converter) 35. These display controllers 10,
Dual port image memory (VRAM) 30 and D
The AC 35 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array, and forms a main part of the display control system 4. The display controller 10 uses a dual-port image memory (VRAM) 30 and a DAC 35 in accordance with an instruction from the CPU 1 to
The display control for the T display 50 is executed. Further, the display controller 10 functions as a bus master, and can directly access the system memory 2.

A dual port image memory (VRAM) 3
0 has a serial port (serial DATA) used for serial access and a parallel port (DATA) for random access. The serial port (serial DATA) is used for reading data for refreshing the display screen, and the parallel port (DA
TA) is used for updating display data. This dual port image memory (VRAM) 30 is composed of a plurality of dual port DRAMs,
It has a storage capacity of M bytes. In the dual port image memory (VRAM) 30, display data to be displayed on the flat panel display 40 or the color CRT display 50 is drawn.

In this case, the drawing data of the XGA specification created by an application program or the like conforming to the XGA specification is stored in the dual port image memory (VRAM) 30 by the packed pixel method. The packed pixel method is a color information mapping format in which one pixel is represented by consecutive bits on a memory. For example, a method in which one pixel is represented by 1, 2, 4, 8, or 16 bits is employed. On the other hand, the drawing data of the VGA specification is created by a conventional application program or the like conforming to the VGA specification, and is drawn in the dual port image memory (VRAM) 30 by a memory plane method.
This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address, and color information of each pixel is assigned to these planes. For example, 4
If there are planes, one pixel is one for each plane.
It is represented by a total of 4 bits of data for each bit.

A dual port image memory (VRA)
M) 30 also stores text data. The text data for one character has a total size of 2 bytes consisting of an 8-bit code and an 8-bit attribute in both XGA and VGA specifications. The attribute is composed of 4-bit data specifying a foreground color and 4-bit data specifying a background color.

The DAC 35 converts the CRT video data generated by the display controller 10 into analog R, G, B signals and supplies the analog R, G, B signals to the CRT display 50.

The display controller 10 includes a register control circuit 11, a system bus interface 12,
A drawing coprocessor 13, a memory data bus control circuit 14, a CRT controller (CRTC) 15, a memory address bus control circuit 16, a memory control circuit 18, a sprite memory 19, a serializer 20, a latch circuit 21,
Foreground / background multiplexer 22,
It comprises a graphic / text multiplexer 23, a color palette 24, a sprite color register 25, a CRT video multiplexer 26, a sprite control circuit 27, and a flat panel emulation circuit 28.

The register control circuit 11 receives an address and data from the system bus 3 via the system bus interface 12, decodes the address, and performs read / write control on various registers specified by the decoding result. The system bus interface 12 controls the interface with the host system via the system bus 3 and supports a bus interface conforming to various specifications such as ISA, EISA, Micro Channel, and local bus.

The drawing coprocessor 13 responds to an instruction from the CPU 1 to receive a dual port image memory (VRA).
M) It provides various drawing functions to the drawing data in 30. Block transfer of pixels, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, X -Has a memory management function by addressing and paging at the Y coordinate.
The drawing coprocessor 13 includes a VGA / XGA compatible data operation circuit 131 and a two-dimensional address generation circuit 13.
1 and a paging unit 133 are provided.

The data operation circuit 131 performs data operations such as shift, logical arithmetic operation, bit mask, color comparison, etc., and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. Further, the two-dimensional address generation circuit 131 also performs an area check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual storage mechanism as the CPU 1, and converts a linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is enabled. When paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging.

The memory data bus control circuit 14 is for controlling the data bus of the parallel data port (DATA) of the dual port image memory (VRAM) 30. The memory data bus control circuit 14 has four maps of source, pattern, mask, and dest. Is provided with a buffer for accessing the data in a page mode. This buffer also functions as a write data buffer.

The CRT controller 15 is a CRTC for XGA that generates various display timing signals for displaying a screen on the flat panel display 40 or the CRT display 50 at a high resolution (for example, 1024 × 768 dots) conforming to the XGA specification. And a flat panel display 40 or a CRT display 5 with a medium resolution (for example, 640 × 480 dots) conforming to the VGA specification.
0 is provided with a VGA CRTC that generates various display timing signals for screen display. These display timing signals are generated using a horizontal / vertical counter provided in the CRT controller 15. Also,
The CRT controller 15 synchronizes with a display timing for XGA or VGA, an XY pixel address indicating a coordinate position on the display screen corresponding to the display target position in a pixel unit, or a dual port image memory (VRA).
M) A display address for reading drawing data to be displayed on the screen from the serial port (serial DATA) 30 is generated.

The display timing signals supplied to the CRT display 50 include a horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC, and the display timing signals supplied to the flat panel display 40 include a horizontal synchronizing signal LP and a vertical synchronizing signal. There are a signal FP and a shift clock SCK. The generation timing and polarity of the horizontal synchronization signal LP, the vertical synchronization signal FP, and the shift clock SCK for the flat panel display 40 are changed according to the specifications of the flat panel display 40.

The memory address bus control circuit 16 controls the CP supplied via the system bus interface 12.
The address from U1, the address from the drawing coprocessor 13, and the address from the CRTC controller are selected and supplied to the dual port image memory (VRAM) 30. The memory control circuit 18 includes various control signals (Cont) for read / write access to the dual port image memory (VRAM) 30, a clock SCK for controlling data read timing from the serial data port, and an output enable signal SOE. Occurs. Further, the memory control circuit 18 controls the sprite memory 1
9 and the sprite display timing control.

The sprite memory 19 stores sprite data in the graphic mode and fonts in the text mode. In this case, the sprite data is 1
In addition to one, a plurality of, for example, four sprite data are written in the sprite memory 19. In the text mode, the code of the text data read from the dual port image memory (VRAM) 30 is supplied as an index to the sprite memory 19, and the font corresponding to the code is read. This sprite memory 1
Reference numeral 9 has a storage capacity of 8 Kbytes. Since each sprite data is 1 Kbyte, in the graphic mode, 4 Kbyte (1 Kbyte × 4) is used as a sprite data storage area.

The serializer 20 is a parallel / serial conversion circuit that converts parallel pixel data for a plurality of pixels into pixel units (serial). In a graphic mode, a dual port image memory (VRAM) 30 is provided.
The memory data read from the serial data port (serial DATA) and the sprite data read from the sprite memory 19 are respectively subjected to parallel / serial conversion. In the text mode, the font data read from the sprite memory 19 is subjected to parallel / serial conversion.

The latch circuit 21 is for delaying the output timing of the attribute by the delay time of the conversion from the code data to the font data, and is a dual port image memory (VRAM) in the text mode.
30 holds the attribute of the text data read from 30. The foreground / background multiplexer 22 selects one of the attribute foreground color (front color) / background color (background color) in the text mode. This choice is for serializer 2
It is controlled by font data values “1” (foreground) and “0” (background) output from 0. The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode. In the graphic mode, the graphic data is selected from the memory data output from the serializer 20, and in the text mode, the foreground / background multiplexer 22 is selected. Select output.

The color pallet control circuit 24 performs color conversion of graphic or text data to generate video data. The color pallet control circuit 24 has a two-stage color pallet table. The first color pallet table is composed of 16 color pallet registers. Each color palette register stores 6-bit color palette data. The second color pallet table is composed of 256 color pallet registers. Each color palette register stores 18-bit color data composed of 6 bits for each of R, G, and B.

In the graphic mode, 8-bit / pixel XGA memory data is sent directly to the second color pallet table without passing through the first color pallet table, where R, G, and B are respectively stored in the memory. It is converted to color data composed of bits. Also,
The 4-bit / pixel memory data of the VGA specification is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from a color selection register built in the color pallet control circuit 19 is added, thereby forming a total of 8 bits of color data. Thereafter, the 8-bit color data is sent to the second color pallet table, where it is converted into color data composed of 6 bits each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA specifications can be converted to R and R via the first and second two-stage color palette tables.
G and B are converted into color data composed of 6 bits each.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel is not passed through the color pallet control circuit 24. Are supplied directly to the CRT video multiplexer 26.

The sprite color register 25 specifies a sprite display color. The sprite color register 25 is provided with eight sprite color registers. Two sprite color registers are allocated for every four sprite data. The CRT video multiplex operation circuit 26 selects the CRT video display output, and outputs the output of the color pallet control circuit 24,
Alternatively, selection of direct color output from the serializer 20, and video switching and calculation of sprite display are performed. The sprite control circuit 27 controls the CRT video multiplex operation circuit 2 according to the sprite data converted from parallel / serial by the serializer 20.
6 to control video switching during sprite display.

Flat panel emulation circuit 28
Converts the CRT video output to generate flat video data VD for the flat panel display 40.
In this case, the flat video data VD is large depending on whether the flat panel display 40 displays colors or gradations. In the case of color display, the number differs depending on the number of display colors and whether the panel is TFT or STN, and in the case of gradation display, the number of gradations differs depending on whether the panel is PDP or LCD. The data format of the flat video data VD is changed according to the specifications of such a panel. Next, FIG.
A configuration for identifying the specifications of the flat panel display 40 which is a feature of the present invention will be described with reference to FIG.

As shown in FIG. 2, the interface between the display controller 10 and the flat panel display 40 includes a data line 101, a horizontal synchronization signal line 102, a shift clock signal line 103, and a vertical synchronization signal line 104. , A direction control line 105 is provided.
The data line 101, the horizontal synchronizing signal line 102, the shift clock signal line 103, and the vertical synchronizing signal line 104 are conventionally provided. In this embodiment, the data line 101 is used to transfer video data from the ROM 401. Data line 1 to share the status data transfer
01 is used as a bidirectional data line.

To use the data line 101 as a bidirectional data line, the display controller 10 is provided with a three-state output buffer 201 and an input buffer 202, and the flat panel display 40 is provided with an input buffer 402 and a three-state output buffer. A buffer 403 is provided. The transfer direction of the data line 101 is switched by the direction control line 105.

That is, the signal DI on the direction control line 105
When R is "1", the three-state output buffer 201 is active, and the output of the three-state output buffer 403 becomes high impedance. Therefore, the transfer direction of the data line 101 is the same as the direction from the display controller 10 to the flat panel display 40. Become. This transfer direction is used when the video data VD generated by the flat panel emulation circuit 28 is transferred to the display circuit in the flat panel display 40 via the data line 101, that is, used for normal data display.

The signal DIR on the direction control line 105 is "0".
In the case of, the output of the three-state output buffer 201 is high impedance and the three-state output buffer 403 becomes active, so that the transfer direction of the data line 101 is the direction from the flat panel display 40 to the display controller 10. This transfer direction is determined by the ROM 401
Status data (STATUS) read from the display controller 10 via the data line 101.
Is used during initial setting for determining the specifications of the flat panel display 40.

The horizontal synchronizing signal line 102 is a horizontal synchronizing signal L for a flat panel display generated by the CRT controller 15 of the display controller 10.
P is supplied to the flat panel display 40. At the time of initial setting for determining the specifications of the flat panel display 40, the status read clock R
Used for transferring CK. The status read clock RCK is generated by the CRT controller 15 based on, for example, an I / O read signal from the CPU 1. The horizontal synchronization signal LP and the status read clock RCK are supplied to a selector 203, and the output of the selector 203 is supplied to a horizontal synchronization signal line 102. The selector 203 selects the horizontal synchronization signal LP when the signal DIR is “1”, and selects the status read clock RCK when the signal DIR is “0”. That is, the status read clock RCK is output during the initial setting for determining the specifications of the flat panel display 40, and the horizontal synchronization signal LP is output during the display operation. This status read clock RCK is stored in the ROM 4
Counter 404 for generating the read address 01
Supplied to This counter 404 increments the read address of the ROM 401 according to the number of status read clocks RCK.

The shift clock signal line 103 and the vertical synchronizing signal line 104 are connected to the display controller 10 respectively.
The vertical synchronizing signal FP is also used as a reset signal of the counter 404 to supply the shift clock SCK and the vertical synchronizing signal FP generated by the CRT controller 15 to the flat panel display 40.

Further, the CRT controller 15 of the display controller 10 includes a counter 204, a decoder 205, a resolution status register 206, a color / gradation, and the like as a structure for temporarily holding status data read from the ROM 401. A plurality of status registers including a status register 207 are provided. The counter 204 counts the number of the status read clocks RCK, and supplies the count value to the decoder 205. The decoder 205 controls the status registers 206 and 20 according to the count value.
7,... Are enabled in order. The resolution status register 206 holds status data indicating the resolution read from the ROM 401, and the color / gradation (gray) status register 207 stores the status data.
And status data indicating the distinction of color / gradation read out from.

The contents of these status registers are I
The data is read by the CPU 1 by an / O read or the like, whereby the specifications of the flat panel display 40 are determined by software. According to the result of the determination, the generation format (color / gradation) of video data, the output format (the number of pixels to be output simultaneously, the number of bits per pixel, etc.), the horizontal synchronization signal LP, the vertical synchronization signal FP, the shift clock The timing and polarity of SCK are controlled. As a control method, a plurality of data generation circuits and timing signal generation circuits are provided in advance, a configuration for selecting a circuit to be used according to the determination result, and a parameter according to the determination result are set in a register. A configuration in which the output format of the video data and the timing / polarity of the synchronizing signal are variably set according to the conditions can be used. Next, an operation for reading status data from the ROM 401 will be described with reference to the timing chart of FIG.

At the time of initialization for determining the specifications of the flat panel display 40, the signal DIR goes to "0" level, and the three-state output buffer 201 for outputting the video data VD enters a high impedance state. A three-state output buffer 4 for outputting status data read from the ROM 401
02 becomes active. In this state, the status read clock RCK is sequentially generated. The counters 204 and 40 are synchronized with the status read clock RCK.
The count value of 4 is sequentially counted up as “0”, “1”, “2”,.

The resolution status data, color / gradation status data,... Are sequentially read from the ROM 401 in accordance with the count values “0”, “1”,. The data is transferred to the controller 10. If the count value of the counter 204 is “0”, the resolution status register 206
Is set to the enable state, the resolution status data is latched by the resolution status register 206 when the register latch clock is input. . When the count value of the counter 204 is "1", the color / grayscale status register 207 is set to the enable state. It is latched by the gradation status register 207. In this manner, various status data in the ROM 401 is sent to the display controller 10 via the data line 101 and stored in the corresponding register.

These status registers 206 and 207
Are read by the CPU 1 to determine the specifications of the flat panel display 40. Then, display timing and data output format are controlled according to the result of the determination.

As described above, in this embodiment, the ROM 401 is provided in the flat panel display 40, and since various status data necessary for display control is stored in the ROM 401, the status data is read. This makes it possible to automatically determine the specifications of various flat panel displays, and to perform display control according to the specifications of various flat panel displays. Since the data line 101 to which the video data is transferred is a bidirectional data line and the control information is read by switching the direction of the bidirectional data line, the display controller 10
The number of signal lines between the display and the flat panel display 40 does not increase. Therefore, the flat panel display can be determined with a simple configuration.

[0050]

As described above, according to the present invention, the specifications of various flat panel displays can be automatically determined with a simple configuration, and display control can be performed according to the flat panel display used. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an entire display control system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an interface unit between a display controller and a flat panel display in the embodiment.

FIG. 3 is a timing chart illustrating an operation of reading status data from a ROM provided in a flat panel display in the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 4 ... Display control system, 10 ... Display controller, 15 ... CRT controller, 40 ... Flat panel display, 101 ... Data line, 206
... Resolution status register, 207 ... Color / gradation status register.

Claims (1)

(57) [Claims] A flat panel display; a memory device provided in the flat panel display for storing various control information necessary for display control of the flat panel display; display data to be displayed on the flat panel display; a display control unit for generating a display timing control signal for controlling the display timing, the provided flat panel display between the display control device, the display generated from the display control device
A bidirectional data line through which data or the control information read from the memory device is transferred; and wherein the display data is transferred from the display control device to the flat panel display, and the control information is transferred from the flat panel display to the display. Transfer direction switching means for switching the data transfer direction of the bidirectional data line so as to be transferred to the control device;
Transfer from the rat panel display to the display controller
When reading the control information from the memory device
A read control signal for the display timing
Supplying a control signal to the flat panel display
Through the signal line for the flat panel display
Means for supplying to the flat panel display,
Supply to the memory device in synchronization with the control signal
Address generation circuit for sequentially incrementing the read address value
A display control system comprising: