JPH05235897A - Demodulator for synchronization type spread spectrum modulation wave - Google Patents

Abstract

PURPOSE:To attain ideal demodulation with simple configuration by obtaining a non-modulation processing VCO output synchronously with an input angular modulation wave from a demodulation system PLL, obtaining a spread code generating clock through the frequency division of the said output as a signal equivalent to a local oscillation output at modulation. CONSTITUTION:A synchronization type spread spectrum (SS) modulation wave signal from an input terminal In2 is fed to a loop filter 24 as a signal subject to inverse spread by an inverse spread use multiplier 3 or the like, the loop filter 24 eliminates a phase error in a phase locked loop locking an angular modulation wave after the inverse spread and a carrier signal subject to no modulation is outputted from a VCO 22. The signal is frequency-divided by 1/N1 and 1/N2 frequency dividers 26, 27 and a clock equivalent to a local oscillation output at modulation is obtained, then jitter in a spread code generator 47 and the multiplier 3 or the like is suppressed and ideal demodulation of the synchronization SS spread modulation wave is attained with simple configuration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a demodulator for demodulating a synchronous spread spectrum (hereinafter abbreviated as "SS") modulated wave in which a carrier of a primary modulated wave and a spread code are in a synchronous relationship. In particular, the present invention relates to a demodulation device for a synchronous SS modulated wave that does not require a synchronization holding function. In the following description, the demodulation device of the present invention is applied to the receiving section of communication equipment, and the transmitting section (modulation circuit) will be described as necessary.

[0002]

TECHNICAL BACKGROUND Recently, in SS communication, mobile communication using the multiple access method by SS technology has reached a practical range. As is well known, since radio resources are limited, it is necessary to effectively use frequencies. In that respect, the SS signal is spread over a wide frequency band and the power spectrum density of the modulated wave is very small, so that it has little effect on other communication radio waves and the like, and can be mixed in existing communication frequency bands. In addition, it can contribute to the improvement of frequency utilization efficiency. Therefore, wireless communication by SS is becoming familiar, and in the future, it is expected to have great potential and developability such as application of communication between mobile bodies mounted on vehicles.

[0003]

2. Description of the Related Art In SS communication, synchronization acquisition and synchronization holding in reception are basically required, and various synchronization acquisition methods and holding methods have been proposed and put into practical use. Among them, during the modulation, the carrier for angle modulation (frequency modulation or phase modulation) which is the primary modulation and the spread code clock signal used for the SS modulation which is the secondary modulation are synchronized with each other to perform the SS modulation. Do so-called synchronous SS
The modulation / demodulation method is also known as a method that can simplify the circuit configuration to some extent in reception and demodulation.

The conventional technique will be described with reference to FIGS. FIG. 1 shows the circuit configuration of the transmission unit side (modulation device) that generates a transmission signal for the present demodulation device.
2 shows a circuit configuration of a conventional synchronous SS demodulation wave demodulator, and FIG. 3 shows a specific circuit configuration of a signal processing circuit which is a main part of a DLL (delay lock loop) type synchronous holding circuit.
Shows the sync holding characteristic in the DLL type sync holding circuit as shown in FIG.
Respectively show the correlation characteristics showing the sliding correlation type synchronous acquisition operation.

First, a synchronous spread spectrum modulator which is a transmitter will be described with reference to FIG. The information S (t) including the audio signal is supplied from the input terminal In1 to the angle modulation circuit 52 to be angle-modulated. The carrier for angle modulation is supplied from a local oscillator (OSC) 49,
Obtained as a carrier synchronized with the local oscillator output. The angle modulation output F (t) is supplied to the multiplier 6 for spread modulation, where spread modulation is performed by multiplication with the spread code P (t) output from the spread code generator (PNG) 48. PN
As a clock signal, a local oscillation output output from the OSC 49 is divided into 1 / N ₁ by the frequency divider 25 as a clock signal, and a divided output is obtained as a clock signal C (t). A synchronization relationship is maintained with the spreading code. Therefore, the SS modulation output obtained from the multiplier 6 via the BPF 11 becomes F (t) P (t) and is output from the output terminal Out1.

Such a synchronous SS modulated wave is transmitted to the demodulation section via a transmission medium such as radio waves (wireless) or wires (wired). Here, regarding the demodulation operation (conventional demodulation device), This will be described with reference to FIG. The SS modulated wave is received by an antenna (not shown) on the receiver side, is supplied from the input terminal In2 to the AGC (automatic gain control circuit) 20 through the BPF 12, and after being amplified as necessary here. , A multiplier for both sliding correlation and despread demodulation 3
And a DLL-type synchronization holding signal processing circuit (hereinafter simply referred to as “DL
L signal processing circuit ”).
A spreading code generated by a PNG (spreading code generator) 47 is also supplied to the multiplier 3, and the clock signal for this spreading code is slightly higher than that at the time of holding the synchronization until the synchronization is acquired. It is set by a VCO (voltage controlled oscillator) 21. Therefore, the sliding correlation and the despread demodulation are performed in time series.

The operation leading to synchronization acquisition (establishment) will now be described. The input SS modulated wave P (t) * d (t) cosωt from which unnecessary frequency band components have been attenuated or removed by the BPF 12 is used by the spread code P from the spread code generator 47 in the multiplier 3.
Correlation is performed by multiplication with (t). This spreading code P
(t) is the spreading code P (t) generated by the PNG 48 on the receiving side.
Is actually P (t−τ) with a delay of time τ, and is represented by adding Λ (hat) on the letter P of P (t), but here it is used in electronic applications. Due to the restriction of possible characters, it is represented by "ρ (t)". As a result, the multiplication output from the multiplier 3 is P (t) * ρ (t) * d (t) cosω
Expressed as t.

The multiplication output is supplied to the multipliers 4 and 5, and the multiplier 4 reproduces the carrier carrier cos from the VCO 22.
Synchronous detection is performed by multiplication with (ωt-φ). Therefore, from the multiplier 4, (1/2) P (t) * ρ (t) * d (t) * {cosφ + c
os (2ωt-φ)} is output and the LPF (low-pass filter) 17 at the next stage removes P (t) * ρ (t) * d (t) cos (2ωt-φ) / 2 components As a result, P (t) * ρ (t) * d (t) cosφ. If the value of φ is close to 0, the LPF17 output P (t) * ρ (t) *
The level of d (t) cosφ is about 1/2. On the other hand, the multiplier 5
Is supplied with a carrier of regenerated carrier cos (ωt-φ) from the voltage controlled oscillator (VCO) 22 and sin (ωt-φ) whose phase is shifted by π / 2 in the π / 2 phase shift circuit 23. ing.

Therefore, the output of the multiplier 5 is (-1/2) P (t) *.
ρ (t) * d (t) * {sinφ + sin (2ωt-φ)}, and LPF18
Outputs -P (t) * ρ (t) sinφ, but the actual level is close to zero. The outputs of the LPF 17 and LPF 18 are both supplied to the multiplier 6, where multiplication is performed, and the output is P ² (t) * ρ ² (t) * d ² (t) * (-1/2) sin 2φ
Is obtained as an error signal. Such an error signal is further reduced by the loop filter 24 which determines the response time constant of the loop.
After being converted into an error signal of Ksin2φ, it is supplied to the VCO 22 as a control signal. The carrier reproducing circuit 50 including such a loop of phase locked loop can simultaneously perform PSK demodulation in synchronization with the input carrier.

It is this carrier regenerating circuit 50 that first starts to work after the power of the receiving section in the communication device is turned on. Therefore, after carrier regeneration, the correlation output P (t) * ρ (t) obtained from the LPF 17, That is, 3 centered at the point t ₀ in FIG.
An output based on the angular output characteristic is supplied to a threshold level detection circuit (synchronization detection circuit) 34 for synchronous acquisition of sliding correlation, and after the synchronization acquisition point SL is detected here, an output (waveform) shaping circuit 35 is further provided. , And a constant DC output is obtained from the time of synchronization acquisition. This DC output is supplied to the adder circuit 42, where the DLL signal processing circuit 3
After being added to the correlation output from 6, the VCO 21 is supplied. The VCO 21 is controlled by the obtained addition output, and the controlled voltage-controlled oscillation output becomes a clock signal for generating the spread code at the time of normal synchronization holding.

Next, the synchronization holding operation will be described. The input SS modulated wave is supplied to the DLL signal processing circuit 36 via the BPF 12. Here, a specific circuit example of the DLL signal processing circuit 36 is shown in FIG. The SS modulated wave is input from the input terminal In3 to the multipliers 7 and 8
Is supplied to. On the other hand, the multiplier 3 is connected to the input terminal In4.
The spread code (a) having a phase Δt earlier than that of the regular spread code P (t) supplied to the terminal (a) and the spread code (b) having a phase Δt slower than P (t + Δt) at the input terminal In5. , PNG47
More supplied respectively. In the SS method, Δt is the time for one bit of the spread code, that is, one chip time, so
The output of the multiplier 7 is PSK which is the despreading output during normal operation.
It is a modulated wave, and the narrow band characteristic BPF1 that can transmit this.
Absolute value circuit (or envelope detection circuit) 3
8 are supplied. Similarly, the output of the multiplier 8 is also the BPF 14
Is supplied to the absolute value circuit 39 via.

Therefore, the output from the absolute value circuit 38 is approximately P (t) * P (t-Δt) in the component of twice the carrier frequency.
And the output of the absolute value circuit 39 is also obtained as a signal in which the component of twice the carrier frequency is multiplied by P (t) * P (t + Δt). The respective output signals are supplied to the subtraction circuit 40 to be subtracted, and the characteristics thereof are the inverse S-shaped correlation characteristics shown in FIG. The point (C) is a synchronization holding point. The correlation output thus obtained is output from the output terminal Out3 via the loop filter 28 for processing this into a control signal, and is added to the output of the waveform shaping circuit 35 by the adder circuit 42 of FIG. After that, it is supplied to the VCO 21 and the synchronization is maintained.

[0013]

Such a conventional SS demodulator requires a circuit for maintaining synchronization, an AGC 20, etc., which complicates the circuit configuration and increases the cost, and each circuit does not always follow the theory. However, there is a problem that it is difficult to operate the device stably because it does not function. Further, since both the VCO 22 for carrier reproduction and the VCO 21 for clock generation need oscillators and a synchronous holding circuit must be used together, there is a problem that the circuit scale increases. Therefore, it has been desired to simplify the SS synchronization circuit and realize a demodulation device that does not require the AGC circuit 2.

[0014]

A demodulator for a synchronous spread spectrum modulated wave according to the present invention uses a loop filter for a demodulation information component generated in a phase error output of a phase locked loop locked to an angle modulated wave obtained by despread demodulation. Carrier generating means for obtaining a carrier signal that has been sufficiently demodulated to obtain an unmodulated carrier signal, and clock signal generating means for obtaining the first and second clock signals by dividing the carrier signal by the first and second frequency division numbers. And a demodulation spreading code generating means for generating a spreading code for synchronization acquisition based on the first clock signal, and for generating a spreading code when synchronization is established based on the second clock signal; Synchronization acquisition means for performing synchronization acquisition based on a spread code by a clock signal, and despreading for detecting a synchronization establishment point by synchronization acquisition and switching to a second clock signal to perform despreading by establishment of synchronization. Means, an angle demodulation means for extracting an angle-modulated wave for demodulation from the obtained despread output to perform angle demodulation, and noise detection for synchronization acquisition from the angle demodulation output to detect the first and second clock signals. The above problem is solved by the configuration including a generation unit that generates a control signal (error voltage) for selection switching of the above.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 and subsequent figures, the synchronous SS of the present invention is shown.
A specific example of the demodulation device for the modulated wave will be described. FIG. 1 is a block diagram of a demodulator 1 for a synchronous SS modulated wave, which is a first embodiment of the present invention. In this figure, 2
6 to 29 are frequency dividers for dividing the input signal frequency into 1 / N ₁ , 1 / N ₂ or 1 / N ₃ , respectively, 43 is an amplitude limiting amplifier (LIM), 53 is an angle demodulation circuit, and Sw is a switch circuit. Other than that, the same components as those of the conventional device shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. The loop filter 24, the VCO 22, the frequency divider 29, and the phase comparator 6 form a PLL circuit (phase locked loop).
Are formed.

Synchronous SS modulated wave F (t) P from input terminal In2
(t) is supplied to the despreading multiplier 3 via the BPF 12, and the spreading code ρ (t) output from the spreading code generator 47.
Is multiplied by. The spread code ρ (t) is input through the switch circuit Sw as a clock signal obtained by dividing the free-run output of the VCO 21 by the frequency divider 24, and is generated by the spread code generator 47 based on this. . Therefore, the multiplier 3
Output is F (t) P (t) * ρ (t). This multiplication output is in the diffused state before synchronization acquisition, and the correlation state is obtained with the lapse of time, leading to reduction in demodulation noise of the angle demodulation circuit 53 in the subsequent stage.

This demodulation noise is supplied to the sync detection circuit 34 via the BPF 16 whose pass band is set slightly higher than the audio frequency band, and is further waveform-shaped by the shaping circuit 35 to form a control signal, which is obtained. The connection to the frequency divider 23 is switched by supplying the control signal to the switch circuit 25. As a result, the output of the VCO 21 is divided by N ₁ and supplied to the spread code generator 47 as a regular clock signal. Therefore, the spreading code output from the spreading code generator 47 is P (t), and the output of the multiplier 3 is P (t).
(t) * P (t) F (t).

As is well known, since P ² (t) = 1,
The output of the BPF 15 is obtained as SS demodulated F (t),
It is supplied to the angle demodulation circuit 53 and the frequency divider 28 via the amplitude limiting amplifier 43. The frequency divider 28 divides the angle-modulated wave F (t) by N.
₃ minutes and 1-divided in to lower the angle modulation wave deviation (the deviation) Delta] f to 1 of N ₃ minutes, a phase comparator (a multiplier)
The phase comparison range in 6 is not exceeded.
Therefore, the phase comparator 6 outputs the output of the VCO 22 to the frequency divider 2
The frequency is divided into N _1/3 via 9, the phase comparison is performed with the output of the frequency divider 28, the loop filter 24 converts it into an error voltage (control signal) and feeds it back to the VCO 22.

The output of the phase comparator 6 is obtained as a demodulated angle-modulated wave F (t), but the demodulation component can be greatly reduced by selecting a large time constant for the loop filter 24. Therefore, the output of the VCO 22 is obtained as an almost non-modulated one. This unmodulated VC
The O output is synchronized with the input angle modulated wave, and this VCO2
Since the output of 2 is set as the clock signal by setting the same frequency division number as the frequency divider 25 on the modulator side, the spreading code P (t) equal to that at the time of modulation can be obtained. On the other hand, the angle modulated wave F (t) supplied to the angle demodulation circuit 53 is angle demodulated here to s' (t), and is output from the output terminal Out2 via the LPF 19.

Next, a second embodiment of the demodulator of the synchronous SS modulated wave of the present invention will be described with reference to FIG. The main difference between the second embodiment device 2 and the first embodiment device 1 is that
As is clear from both figures, the subtraction circuit 41 is provided after the loop filter 24, the demodulation output s' (t) supplied to the output terminal Out2 is branched, and the level adjuster 30 adjusts the level appropriately. The demodulation components (demodulation information and demodulation noise) supplied to the subtraction circuit 41 and obtained by the phase comparator 6 are canceled here.

As a result, the time constant of the loop filter 24 can be reduced, so that the dynamic response characteristic of the PLL circuit can be speeded up, and the establishment time of SS synchronization can be shortened. Moreover, since there is no demodulation component in the error voltage supplied to the VCO 22, it can be obtained as a clock signal substantially equivalent to the clock signal at the time of modulation. In addition,
Since the other operations are the same as those of the first embodiment device 1, the same components are designated by the same reference numerals and detailed description thereof will be omitted.

In the configuration of the second embodiment device 2, the arrangement of the loop filter 24 and the subtraction circuit 41 is reversed, and the angle demodulation circuit 53 supplies the subtraction circuit 41 via the level adjuster 30. It can also be configured (this is the third embodiment). In this case, the subtraction circuit 41 cancels the demodulation component in advance, and then the loop filter 2
4, the loop response frequency (response time constant) of the PLL circuit including the loop filter 24 can be set sufficiently lower than the demodulation frequency band as compared with the demodulator 2 of FIG. .. As a result, when C / N deteriorates, V
Jitter that becomes noticeable in the output signal of the CO 22 can be suppressed by the value of the loop response time constant, and the SS synchronization establishment time can be made shorter than that of the demodulator 1. Therefore, from the viewpoint of jitter suppression and synchronization establishment time. In, a balanced demodulator can be provided.

[0023]

As described above, according to the demodulator of the synchronous SS modulated wave of the present invention, the common feature of each embodiment is that the PLL in the demodulator does not modulate in synchronization with the input angle modulated wave. Since the converted VCO output is obtained, the spread code generating clock signal obtained by dividing the VCO output can be used as a signal equivalent to the local oscillation output at the time of modulation, which is ideal for the incoming synchronous SS modulated wave. Demodulation can be achieved, and further, the DLL type synchronization holding circuit and the AGC circuit 20 for making the variation of the input SS modulated wave level constant in the conventional device are not required, so that the circuit scale can be greatly simplified. Have.

Further, as a feature of each embodiment, the demodulator of the first embodiment has the simplest circuit and the second embodiment of the device can minimize the synchronization establishment time. Furthermore, in the device of the third embodiment, the angle adjuster circuit 5 is used in the level adjuster 30.
By adjusting the output level of No. 3, the synchronization establishment time can be set to any value from the value of the device 2 of the second embodiment to the value of the device 1 of the first embodiment, whereby the jitter in the output of the VCO 22 is set. It has an excellent feature that it can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronous SS modulator that generates a transmission signal.

FIG. 2 is a block configuration diagram of a conventional typical demodulator for a synchronous SS modulated wave.

FIG. 3 is a specific configuration diagram of a DLL-type synchronization holding signal processing circuit which is a main part of a conventional device.

FIG. 4 is a characteristic diagram showing a sync holding characteristic in a DLL-type sync holding signal processing circuit.

FIG. 5 is a correlation characteristic diagram for explaining a sliding correlation type synchronous capturing operation.

FIG. 6 is a block diagram showing the first embodiment of the demodulation device of the present invention.

FIG. 7 is a block configuration diagram showing a second embodiment of the demodulation device of the present invention.

[Explanation of symbols]

 1, 2 Demodulator 3-9 Multiplier 11-16 BPF (Band filter) 17-19 LPF (Low-pass filter) 21,22 VCO (Voltage controlled oscillator) 24 Loop filter 25-29 Divider 30 Level adjustment 34 Sync detection circuit 35 Shaping circuit 40, 41 Subtraction circuit 43 Amplitude limiting amplifier 47, 48 PNG (spreading code generator) 50 Carrier regeneration circuit 52 Angle modulation circuit 53 Angle demodulation circuit Sw switch circuit

Claims (4)

[Claims] Claims: 1. A synchronous spread spectrum modulation signal is input and demodulated, in which a carrier of an angle-modulated wave for primary modulation and a spread code for secondary modulation are spread-modulated and transmitted while maintaining a synchronous relationship. In a demodulator for a synchronous spread spectrum modulated wave, a demodulated information component generated in a phase error output of a phase locked loop locked to an angle modulated wave obtained by despread demodulation is sufficiently removed by a loop filter to make it a non-modulated carrier signal. Based on the first clock signal, and carrier signal generating means for obtaining the first and second clock signals by dividing the carrier signal by the first and second frequency division numbers. A spreading code for demodulation, which generates a spreading code for acquisition of synchronization and a spreading code when synchronization is established based on the second clock signal, and an expansion by the first clock signal. Synchronization acquisition means for performing synchronization acquisition (sliding correlation) based on the scattered code; despreading means for detecting a synchronization establishment point by the synchronization acquisition and switching to the second clock signal to perform despreading by establishment of synchronization. An angle demodulating means for extracting an angle-modulated wave for demodulation from the obtained despread output to perform angle demodulation, and noise detection for synchronizing acquisition from the angle demodulated output for the first and second clock signals. A demodulation device for a synchronous spread spectrum modulated wave, which comprises a generation means for generating a control signal (error voltage) for selection switching of the above. 2. A synchronous spread spectrum modulation signal, which is spread-modulated and transmitted while maintaining a synchronous relationship between a carrier of an angle-modulated wave for primary modulation and a spread code for secondary modulation, and demodulates the same. In a demodulator for a synchronous spread spectrum modulation wave, the demodulation information component generated in the phase error output of the phase locked loop that locks to the angle modulation wave obtained by despread demodulation is canceled by subtraction with the angle demodulation output to make no modulation. Carrier generating means for obtaining the generated carrier signal, clock signal generating means for obtaining the first and second clock signals by dividing the carrier signal by the first and second frequency division numbers, and the first clock signal And a means for generating a spreading code for demodulation for generating a spreading code for synchronization acquisition based on the second clock signal and a spreading code at the time of establishing synchronization based on the second clock signal, and the obtained first clock signal. Yo Means for performing synchronization acquisition based on the spread code, despreading means for detecting the synchronization establishment point by synchronization acquisition and switching to the second clock signal for despreading by establishing synchronization, and the obtained despreading output Angle demodulation means for extracting the angle-modulated wave for demodulation to perform angle demodulation, and noise detection and control signal conversion for synchronous acquisition from the angle demodulation output to selectively switch the first and second clock signals. Demodulation device for a synchronous spread spectrum modulated wave, which comprises a generating means for generating a control signal. 3. A phase-locked loop means for locking the angle-modulated wave, comprising a frequency divider for reducing the frequency deviation of the angle-modulated wave, and the frequency-divided angle-modulated wave in the phase-locked loop having a phase comparator. The demodulator of the synchronous spread spectrum modulated wave according to claim 1 or 2, which is configured to be supplied to 4. The subtraction means for canceling the demodulation component in the phase locked loop locked to the angle modulated wave is obtained by adjusting the level of the loop filter output in the phase locked loop and the final angle demodulated output. The demodulation output is subtracted, or the phase comparator output in the phase-locked loop and the demodulation output obtained by level-adjusting the angle demodulation output are subtracted. 2. A demodulator for a synchronous spread spectrum modulated wave according to 2.