JPH05233329A - Microcomputer - Google Patents

Abstract

PURPOSE:To perform fast processing for task switching and the saving and restoration of a register, etc., by providing a switching control means which performs the fast processing for the task switching between a central processing unit and an operating system. CONSTITUTION:A task part executes the task switching when the occurrence of a system call to perform the task switching at a time when software interruption is performed is recognized, and a switching control part 1 applies wait to a CPU. The CPU saves the value of a stack pointer 8 to a stack pointer saving register 6, and copies the value of a register file address 5 on the stack pointer 8. The value of the register 8 is copied on the preservation area of a register file 7 indicated by the pointer 8, and processing of system call is executed. Thence, a bit with the highest priority in a ready task register 2 is set on a run task register 3, and the address of the register file 7 is set on the address 5. After the processing is completed, a restoration instruction is issued to the CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for an information processing apparatus, and more particularly to a microcomputer for an OS that controls a central processing unit (CPU) and an operating system (OS) of the information processing apparatus in real time. It is about.

[0002]

2. Description of the Related Art Generally, when controlling a CPU and an OS of an information processing apparatus, a task is selected and a register is saved / restored by software every time a task is switched by an operator system call. It was

[0003]

However, when a task is selected and registers are saved / restored in software, the current task is temporarily saved in software and then switched to the next task in software again. Will be done. Therefore, there is a problem that the processing time for task switching becomes long and the work efficiency is poor. Also, O
When software development for S control is performed, the register file based on the software development must be saved on the software, so that the load factor of software development itself is large. Therefore, an object of the present invention is to enable a microcomputer to perform high-speed processing for task switching, register saving / restoring, etc. under the control of the CPU and OS of the information processing apparatus, and to load the OS control software itself. It is to provide a microcomputer capable of reducing the above.

[0004]

According to a first aspect of the present invention, in a microcomputer that controls a CPU and an OS of an information processing apparatus in real time, a switching control that speeds up task switching between the CPU and the OS. Equipped with means. According to the second aspect of the invention, the microcomputer is provided with the storage area securing means for securing the storage area for the software development of the OS.

[0005]

In the microcomputer of the present invention, the switching control means can perform high-speed processing such as task switching for controlling the OS and saving / restoring of registers and the like. In addition, the software development for OS control can be saved by the storage area securing means to reduce the load of the software development itself.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the microcomputer of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a block diagram showing the switching control means of the microcomputer of this embodiment. FIG. 2 is a block diagram showing the storage area securing means of the microcomputer of this embodiment.

In FIG. 1, a switching control unit 1 as a switching control means of a microcomputer in an information processing device (not shown) has a ready task register 2 that indicates an execution format task in bits, and has the highest priority among the execution format tasks. Run task register 3, which indicates the task
Start address table 4 of register file of each task, register file address 5 corresponding to run task register 3, stack file when system call occurs
The SP save register 6 is provided for saving the value of the pointer (SP). 1 and 2, the storage area securing means of the microcomputer includes a register file 7 as a RAM, and the register file 7 has a stack pointer 8. The microcomputer including the switching control unit 1 and the register file 7 is mounted in the information processing device, and has a CPU and an OS of the information processing device.
Is electrically connected to the CPU core 9 to control the above.

Next, the operations of the switching controller 1 and the register file 7 will be described in detail. The operator of the information processing device
When the system call is interrupted by software (SWI) to switch the task, the task unit executes the SWI and the switching control unit 1 puts a wait on the CPU. Here, the CPU saves the value of the stack pointer 8
The value is saved in the register 6, the value of the register file address 5 (register file of the task being executed) is copied to the stack pointer 8, and the CPU wait is released. Then, the CPU copies the value of the SP save register 6 to the save area of the register file 7 indicated by the stack pointer 8 and executes the system call process, and the most of the ready task register 2 The priority bit is set in the run task register 3, and the address of the register file 7 corresponding to the run task register 3 is set in the register file address 5.

After the completion of this system call processing, a wait is given to give a return instruction (RTI) to the CPU,
Register file address 5 to stack pointer 8
The CPU wait state is released, the CPU recovers the value of each register from the register file 7, while copying the value of the SP save register 6 in the register file 7 to the stack pointer 8 for system call processing. Upon completion, the task is switched and the next task is executed.

As described above, when the system call occurs,
The task switching control can perform high-speed processing from the current task to the next task in the switching control unit 1, and the task switching work efficiency can be improved. Further, in the software development itself for OS control, the load in software development can be reduced by securing the storage area of the register file 7.

[0011]

According to the first aspect of the present invention, it is possible to perform high-speed processing such as task switching and register saving / restoring under the control of the CPU and OS of the information processing apparatus. According to the second aspect of the invention, it is possible to reduce the load of software development itself for OS control.

[Brief description of drawings]

FIG. 1 is a block diagram showing a switching control means of an embodiment in a microcomputer of the present invention.

FIG. 2 is a block diagram showing storage area securing means of an embodiment in the microcomputer of the present invention.

[Explanation of symbols]

 1 Switching Control Unit 2 Ready Task Register 3 Run Task Register 5 Register File Address 6 SP Save Register 7 Register File 8 Stack Pointer 9 CPU Core

Claims (2)

[Claims] 1. A microcomputer for controlling a central processing unit of an information processing apparatus and an operating system in real time, comprising a switching control means for performing high-speed processing such as task switching between the central processing unit and the operating system. Characteristic microcomputer. 2. The microcomputer according to claim 1, further comprising a storage area reserving means for reserving a storage area for software development of the operating system.